2T1R array based on memristor and parallel operation method and algorithm thereof

Abstract

The present invention provides a 2T1R array based on a memristor, wherein the 2T1R array includes interconnected 2T1R memristor unit circuits, the 2T1R memristor unit circuits are composed of a first transistor, a second transistor and a memristor, the 2T1R array is a cross structure, and the 2T1R memristor unit circuit is located at the cross point of the array. A parallel operation method and algorithm thereof are also provided. The 2T1R memristor array of the present invention can perform set or reset operations on all memristors in parallel at the same time. The parallel degree of in-memory computing reading and writing is improved, and the utilization rate of array devices is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of neural network, and in particular relates to a 2T1R array based on memristors and a parallel operation method and algorithm thereof. Background Art

[0002] Memristor is a non-volatile device whose conductance state can be adjusted by applying external stimuli. Operations involving a large number of multiplication and addition operations can generally be performed in parallel on a memristor array. As a representative of operations involving a large number of multiplication and addition operations, the parallel implementation of artificial neural network algorithms on memristor arrays reflects the advantages of parallel operations of memristor arrays.

[0003] When using the 1T1R array to implement a convolutional neural network algorithm, the image is divided into multiple sub-graphs of the same size as the convolution kernel, and then the convolution kernel is used to perform convolution calculations on each sub-graph. Although multiple convolution kernels can process each sub-graph in parallel, the sub-graphs still need to be input serially to the memristor array. While some memristors are participating in the convolution calculation, other memristors on the memristor array are forced to be in standby mode due to the lack of available input and output channels.

[0004] When adjusting the conductance value of the memristor in the 1T1R array, due to the different adjustment requirements of the conductance value of each memristor, when performing a set operation or a reset operation, at most only the memristors in the same column can be operated at the same time, and the memristors in other columns can only wait for the serial set operation or reset operation. Summary of the invention

[0005] In view of the above defects or improvement needs of the prior art, the present invention proposes a memristor array based on 2T1R units, which aims to greatly improve the parallelism of calculation and adjustment and the utilization rate of devices in the array when the number of device arrays is limited.

[0006] Before describing the present invention, the terms used in this article are defined as follows:

[0007] The term "2T1R array" refers to a structure in which two transistors are connected in series with a memristor or a resistive switching unit.

[0008] The term "1T1R array" refers to a structure in which a transistor is connected in series with a memristor or a resistive switching unit.

[0009] To achieve the above-mentioned object, a first aspect of the present invention provides a 2T1R array based on a memristor, wherein the 2T1R array comprises 2T1R memristor unit circuits connected to each other, wherein the 2T1R memristor unit circuits are composed of a first transistor, a second transistor and a memristor, and the 2T1R array is a cross structure, and the 2T1R memristor unit circuits are located at the cross points of the array.

[0010] The memristor-based 2T1R array according to the first aspect of the present invention, wherein the first transistor is the same as or different from the second transistor;

[0011] Preferably, the first transistor and / or the second transistor is a switching device, preferably one or more of the following: a thin film transistor, a field effect transistor, a bipolar transistor;

[0012] More preferably, the field effect transistor is a MOS field effect transistor.

[0013] According to the first aspect of the present invention, the 2T1R array based on memristors, wherein the sources of the first transistors located in the same column of the array are connected in parallel to the bottom electrode of the array, the gates of the first transistors located in the same column of the array are connected in parallel to the same electrode, the negative electrode of the memristor is connected in series to the drain of the first transistor, the positive electrode of the memristor is connected in series to the drain of the second transistor, the positive electrode of each memristor is connected to an electrode, the second transistors located in the same row of the array are connected in series through the sources and drains, and the gates of the second transistors located in the same column of the array are connected in parallel to the same electrode.

[0014] Preferably, in the 2T1R array, the top electrodes of the memristors in the same row are connected in series via a second transistor in the memristor unit circuit, and each top electrode in the same row can be connected to a different external electrode.

[0015] According to the first aspect of the present invention, a 2T1R array based on a memristor is provided, wherein the source of a first transistor is connected in series with the drain of a second transistor, the second transistors in the same column of the array are connected in series through the source and the drain, the source of each first transistor is connected to an electrode, the negative electrode of the memristor is connected in series with the drain of the first transistor, the positive electrodes of the memristors in the same row of the array are connected in series to the same electrode, the gates of the second transistors in the same row of the array are connected in parallel to the same electrode, and the gates of the first transistors in the same column of the array are connected in parallel to the same electrode.

[0016] Preferably, in the 2T1R array, the sources of the first transistors of the memristor unit circuits in the same column are connected in series via the second transistors in the unit circuits, and the source of each first transistor can be connected to different external electrodes.

[0017] A second aspect of the present invention provides a parallel operation method, wherein the parallel operation method uses the memristor-based 2T1R array described in the first aspect to perform parallel operation;

[0018] Preferably, the parallel operation method comprises: controlling the conduction and shutdown of the second transistor, functionally dividing the memristor array into a plurality of sub-arrays, each sub-array simultaneously performing a set operation or a reset operation, and realizing parallel acceleration state adjustment;

[0019] More preferably, the parallel operation method includes: functionally dividing the memristor array into multiple sub-arrays by controlling the on and off of the second transistor array in the array, each memristor unit circuit simultaneously receives different voltage excitations, thereby simultaneously performing set operations or reset operations to achieve parallel state adjustment.

[0020] According to the parallel operation method of the second aspect of the present invention, the parallel operation method comprises: controlling all the second transistors in the array to be turned on, so that the top electrodes of the memristor unit circuits located in the same row in the 2T1R memristor array receive voltage excitation through the same external electrode;

[0021] The second transistors in the control array are all turned off, so that the top electrodes of the memristor unit circuits in the same row in the 2T1R memristor array are respectively connected to different external electrodes, receive different voltage excitations, and will not affect the memristor unit circuits in adjacent columns; and / or

[0022] The second transistors located in different columns of the array are respectively controlled to be turned on and off, so that the 2T1R memristor array is functionally divided into different sub-arrays in units of columns, the second transistors inside the sub-arrays are turned on, and the second transistors between two adjacent sub-arrays are turned off, the top electrodes of the memristor unit circuits located in the same row inside each sub-array receive voltage excitation through the same external electrode, different sub-arrays are respectively connected to different external electrodes, receive different voltage excitations, and will not affect adjacent sub-arrays.

[0023] According to the parallel operation method of the second aspect of the present invention, the parallel operation method comprises:

[0024] Controlling all the second transistors in the array to be turned on, so that the bottom electrodes of the memristor unit circuits in the same column in the 2T1R memristor array are connected in parallel to the same external electrode to output a current signal;

[0025] All the second transistors in the control array are turned off, so that the bottom electrodes of the memristor unit circuits in the same column of the 2T1R memristor array are respectively connected to different external switches to output respective current signals, and will not be accumulated with the current signals output by the memristor unit circuits in adjacent rows; and / or

[0026] The second transistors located in different rows in the array are respectively controlled to be turned on and off, so that the 2T1R memristor array is functionally divided into different sub-arrays in units of rows, the second transistor array inside the sub-array is turned on, and the second transistor array between two adjacent sub-arrays is turned off, the bottom electrodes of the memristor unit circuits located in the same column inside each sub-array are connected in parallel to the same external electrode to output a current signal, different sub-arrays are respectively connected to different external electrodes, output different current signals, and will not affect adjacent sub-arrays.

[0027] The third aspect of the present invention provides a convolutional neural network algorithm, which uses the 2T1R array based on memristor described in the first aspect or the parallel operation method described in the second aspect to perform convolution calculations.

[0028] Specifically, the present invention provides two memristor arrays based on 2T1R units, and the present invention also provides an operation method for performing parallel acceleration using the 2T1R arrays.

[0029] The first 2T1R memristor array comprises: a first 2T1R memristor unit circuit connected to each other, the first 2T1R unit circuit comprising a first transistor, a second transistor and a memristor, the first 2T1R memristor array is a cross structure, the first 2T1R unit circuit is located at the cross point of the array, the source of the first transistor located in the same column of the array is connected in parallel to the bottom electrode of the array, the gate of the first transistor located in the same column of the array is connected in parallel to the same electrode, the negative electrode of the memristor is connected in series to the drain of the first transistor, the positive electrode of the memristor is connected in series to the drain of the second transistor, the positive electrode of each memristor is connected to an electrode, the second transistors located in the same row of the array are connected in series through the source and the drain, and the gate of the second transistor located in the same column of the array is connected in parallel to the same electrode;

[0030] The second 2T1R memristor array comprises: a second 2T1R unit circuit connected to each other; the second 2T1R unit circuit comprises a first transistor, a second transistor and a memristor, the second 2T1R memristor array is a cross structure, the second 2T1R unit circuit is located at the cross point of the array, the source of the first transistor is connected in series with the drain of the second transistor, the second transistors located in the same column of the array are connected in series through the source and the drain, the source of each first transistor is connected to an electrode, the negative electrode of the memristor is connected in series with the drain of the first transistor, the positive electrodes of the memristors located in the same row of the array are connected in series to the same electrode, the gates of the second transistors located in the same row of the array are connected in parallel to the same electrode, and the gates of the first transistors located in the same column of the array are connected in parallel to the same electrode;

[0031] The parallel operation method comprises:

[0032] Using the first type of 2T1R memristor array, by controlling the on and off of the second transistor in the same column of the array, the memristor array is functionally divided into multiple sub-arrays by column, and each sub-array can be simultaneously applied with different voltage excitations to achieve parallel accelerated computing;

[0033] Using the second type of 2T1R memristor array, by controlling the on and off of the second transistor in the same row of the array, the memristor is functionally divided into multiple sub-arrays by row, and each sub-array can output different current signals at the same time, thereby realizing parallel accelerated computing;

[0034] By using any of the 2T1R memristor arrays, the memristor array is functionally divided into a plurality of sub-arrays by controlling the on and off of the second transistor, and each sub-array can perform a set operation or a reset operation at the same time, thereby realizing parallel acceleration state adjustment.

[0035] For example, the first 2T1R memristor array provided by the present invention, wherein the difference between the 2T1R memristor array and the 1T1R memristor array in the prior art is that the top electrodes of the memristors located in the same row in the present invention are connected in series through the second transistor in the unit circuit, and the top electrode of each memristor can be connected to different external electrodes, while the top electrodes of the memristor unit circuits located in the same row in the 1T1R memristor array in the prior art are directly connected in parallel, and the top electrodes of the memristors located in the same row in the 1T1R array can only be connected to the same external electrode.

[0036] For example, the second 2T1R memristor array provided by the present invention, wherein the difference between the 2T1R memristor array and the 1T1R memristor array in the prior art lies in that the source of the first transistor of the memristor unit circuit located in the same column in the present invention is connected in series through the second transistor in the unit circuit, and the source of each first transistor can be connected to different external electrodes, while the bottom electrodes of the memristor unit circuits located in the same column in the 1T1R memristor array in the prior art are directly connected in parallel, and each bottom electrode located in the same column can only be connected to the same external electrode.

[0037] For example, the parallel operation method provided by the present invention uses the first 2T1R memristor array to control all the second transistors in the array to be turned on, so that the top electrodes of the memristors in the same row in the 2T1R memristor array receive voltage excitation through the same external electrode; the second transistors in the array can also be controlled to be turned off, so that the top electrodes of the memristors in the same row in the 2T1R memristor array are respectively connected to different external electrodes, thereby receiving different voltage excitations, and will not affect the memristor unit circuits in adjacent columns; the second transistors in different columns can also be controlled to be turned on and off as required, so that the 2T1R memristor array is functionally divided into different sub-arrays in units of columns, the second transistors inside the sub-array are turned on, and the second transistors between two adjacent sub-arrays are turned off, the top electrodes of the memristor unit circuits in the same row in each sub-array receive voltage excitation through the same external electrode, and different sub-arrays are respectively connected to different external electrodes, thereby receiving different voltage excitations, and will not affect adjacent sub-arrays.

[0038] For example, the parallel operation method provided by the present invention uses the second type of 2T1R memristor array to control all the second transistors in the array to be turned on, so that the bottom electrodes of the memristors located in the same column in the 2T1R memristor array are connected in parallel to the same external electrode to output a current signal; the second transistors in the array can also be controlled to be turned off, so that the bottom electrodes of the memristor unit circuits located in the same column in the 2T1R memristor array are respectively connected to different external electrodes, thereby outputting respective current signals, and will not be accumulated with the current signals output by the memristor unit circuits in adjacent rows; the turning on and off of the second transistors in the array located in different rows can also be controlled separately as required, so that the 2T1R memristor array is functionally divided into different sub-arrays in units of rows, the second transistors inside the sub-array are turned on, and the second transistors between two adjacent sub-arrays are turned off, the bottom electrodes of the memristor unit circuits located in the same column in each sub-array are connected in parallel to the same external electrode to output a current signal, and different sub-arrays are respectively connected to different external electrodes, thereby outputting different current signals, and will not affect adjacent sub-arrays.

[0039] For example, the parallel operation method provided by the present invention uses any one of the 2T1R memristor arrays to achieve parallel state adjustment. Using any one of the 2T1R memristor arrays, by controlling the on and off of the second transistor in the array, the memristor array is functionally divided into a plurality of sub-arrays, and each memristor unit circuit can receive different voltage excitations at the same time, so that a set operation or a reset operation can be performed at the same time to achieve parallel state adjustment.

[0040] The memristor-based 2T1R array of the present invention may have, but is not limited to, the following beneficial effects:

[0041] The 1T1R memristor array needs to complete the computing tasks serially, while the 2T1R memristor array can complete them in parallel without increasing the number of arrays, but only increasing the array size. The 1T1R memristor array needs to complete the set operation or reset operation row by row or column by column, while the 2T1R memristor array can set or reset all memristors in parallel at the same time. This improves the parallelism of in-memory computing reading and writing, and improves the utilization rate of array devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The embodiments of the present invention are described in detail below with reference to the accompanying drawings, wherein:

[0043] Figure 1 A schematic diagram of a unit circuit of a 2T1R memristor array of Example 1 is shown;

[0044] Figure 2A schematic diagram of a 2T1R memristor array of Experimental Example 1 is shown;

[0045] Figure 3 A schematic diagram of a unit circuit of a 2T1R memristor array of Example 2 is shown;

[0046] Figure 4 A schematic diagram of a 2T1R memristor array of Experimental Example 2 is shown;

[0047] FIG5 shows a schematic diagram of a single-layer calculation of a fully connected neural network in Experimental Example 3 and a schematic diagram of a fully connected calculation based on a 2T1R memristor array of the present invention; wherein, Figure 5A A schematic diagram showing a portion of fully connected calculations of a single layer of a fully connected neural network in Experimental Example 3 is shown; Figure 5B A schematic diagram of implementing fully connected computing based on the 2T1R memristor array in Example 1 in Experimental Example 3 is shown.

[0048] FIG6 shows a schematic diagram of convolution calculation of the convolution layer of the convolutional neural network in Experimental Example 4 and Experimental Example 5 and a schematic diagram of implementing convolution calculation based on the 2T1R memristor array of the present invention in Experimental Example 4; wherein, Fig. 6A A schematic diagram of convolution calculation of a convolution layer of a convolutional neural network in Experimental Example 4 and Experimental Example 5 is shown; Figure 6B A schematic diagram of implementing convolution calculation based on the 2T1R memristor array of Example 1 in Experimental Example 4 is shown.

[0049] Figure 7 A schematic diagram of implementing convolution calculation based on the 2T1R memristor array of Example 2 in Experimental Example 5 is shown.

[0050] Figure 8 A schematic diagram of implementing a parallel set operation based on a 2T1R memristor array of Example 1 in Experimental Example 6 is shown. DETAILED DESCRIPTION

[0051] The present invention is further described below by means of specific examples. However, it should be understood that these examples are only used for more detailed and specific description and should not be understood as limiting the present invention in any form.

[0052] This section generally describes the materials and test methods used in the experiments of the present invention. Although many materials and operating methods used to achieve the purpose of the present invention are well known in the art, the present invention is still described as detailed as possible. It is clear to those skilled in the art that in the context, if not specifically stated, the materials and operating methods used in the present invention are well known in the art.

[0053] Example 1

[0054] This embodiment is used to illustrate the structure of a 2T1R memristor array of the present invention.

[0055] Figure 1 Schematic diagram of the 2T1R unit circuit of the 2T1R memristor array of this embodiment. Figure 1 As shown, the 2T1R unit circuit includes a first transistor M1, a second transistor M2, and a memristor R1.

[0056] It should be noted that the transistors used in the test examples of the present invention can all be thin film transistors or field effect transistors (such as MOS field effect transistors) or other switching devices with the same characteristics. The two transistors used here can be the same or different. The source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be indistinguishable in structure. In the test examples of the present invention, in order to distinguish the electrodes of the two transistors, one of the poles of the first transistor M1 is directly described as the M11 pole and the other pole is the M12 pole, and one of the poles of the second transistor M2 is described as the M21 pole and the other pole is the M22 pole.

[0057] The test example of the present invention does not limit the type of transistor M1 used. For example, when the transistor M1 is an N-type transistor, its gate is connected to the word line terminal WL1. For example, when the word line terminal WL1 is input with a high level, the transistor M1 is turned on; the M11 pole of the transistor M1 can be a source and is configured to be connected to the source line terminal SL. For example, the transistor M1 can receive a reset voltage through the source line terminal SL; the M12 pole of the transistor M1 can be a drain and is configured to be connected to the second pole (for example, the negative pole) of the memristor R1, and the first pole (for example, the positive pole) of the memristor R1 is connected to the bit line terminals BL1 and BL2. For example, the memristor can receive a set voltage through the bit line terminal BL1, and can also receive a set voltage through the bit line terminal BL2. For example, when the transistor M1 is a P-type transistor, its gate is connected to the word line terminal WL1, for example, when a low level is input to the word line terminal WL1, the transistor M1 is turned on; the first electrode of the transistor M1 can be a drain and is configured to be connected to the source line SL1, for example, the transistor M1 can receive a reset voltage through the source line terminal SL1; the second electrode of the transistor M1 can be a source and is configured to be connected to the second electrode (for example, the negative electrode) of the memristor R1, and the first electrode (for example, the positive electrode) of the memristor R1 is connected to the bit line terminal BL, for example, the memristor R1 can receive a set voltage through the bit line terminal BL1.

[0058] The experimental example of the present invention does not limit the type of transistor M2 used. For example, when the transistor M2 is an N-type transistor, its gate is connected to the word line terminal WL2. For example, when a high level is input to the word line terminal WL2, the transistor M2 is turned on; the M21 pole of the transistor M2 can be a drain and is configured to be connected to the first pole (for example, the positive pole) of the memristor R1. For example, when a high level is input to the bit line terminal BL1 or BL2, the M21 pole of the transistor M2 will receive a high level; the M22 pole of the transistor M2 can be a source and is configured to be connected to the source line terminal SL2. For example, when the transistor M2 is turned on, the transistor M2 will output a level value to the source line terminal SL2. For example, when the transistor M2 is a P-type transistor, its gate is connected to the word line terminal WL2, for example, when a low level is input to the word line terminal WL2, the transistor M2 is turned on; the M21 electrode of the transistor M2 can be a drain and is configured to be connected to the first electrode (for example, the positive electrode) of the memristor R1, for example, when a high level is input to the bit line terminal BL1 or BL2, the M21 electrode of the transistor M2 will receive a high level; the M22 electrode of the transistor M2 can be a source and is configured to be connected to the source line terminal SL2, for example, when the transistor M2 is turned on, the transistor M2 will output a current signal to the source line terminal SL2.

[0059] The 2T1R memristor array of the present embodiment used in the following experimental examples is described by taking the example that the transistor M1 is an N-type transistor and the transistor M2 is an N-type transistor.

[0060] The function of the word line terminal WL1 is to apply a corresponding voltage to the gate of the transistor M1, thereby controlling the transistor M1 to be turned on or off. When operating the memristor R1, such as performing a set operation or a reset operation, it is necessary to turn on the transistor M1 first, that is, it is necessary to apply a turn-on voltage to the gate of the transistor M1 through the word line terminal WL1. After the transistor M1 is turned on, for example, a voltage can be applied to the memristor R1 at the source line terminal SL1 and the bit line terminal BL1 or BL2 to change the resistance state of the memristor R1. For example, a set voltage can be applied through the bit line terminal BL1 or BL2 to make the memristor R1 in a low resistance state; for another example, a reset voltage can be applied through the source line terminal SL1 to make the memristor R1 in a high resistance state.

[0061] The function of the word line terminal WL2 is to apply a corresponding voltage to the gate of the transistor M2, thereby controlling the transistor M2 to be turned on or off. For example, when the transistor M2 is turned on, the level of the source line terminal SL2 is related to the word line terminal BL1 or BL2; for another example, when the transistor M2 is turned off, the level of the source line terminal SL2 is independent of the word line terminal BL1 or BL2.

[0062] It should be noted that, in the experimental example of the present invention, by applying voltage simultaneously through the word line terminal WL1 and the bit line terminal BL1 or BL2, the resistance value of the memristor R1 becomes smaller and smaller, that is, the memristor R1 changes from a high resistance state to a low resistance state, which makes the operation of changing the memristor R1 from a high resistance state to a low resistance state a set operation; by applying voltage simultaneously through the word line terminal WL1 and the source line terminal SL1, the resistance value of the memristor R1 becomes larger and larger, that is, the memristor R1 changes from a low resistance state to a high resistance state, which makes the operation of changing the memristor R1 from a low resistance state to a high resistance state a reset operation. For example, the memristor R1 has a threshold voltage, and when the input voltage amplitude is less than the threshold voltage of the memristor R1, the resistance value (or conductance value) of the memristor R1 will not be changed. In this case, the resistance value (or conductance value) of the memristor R1 can be used for calculation by inputting a voltage less than the threshold voltage; the resistance value (or conductance value) of the memristor R1 can also be changed by inputting a voltage greater than the threshold voltage.

[0063] Figure 2 The first 2T1R memristor array is shown. The memristor array is composed of multiple Figure 1 The 2T1R memristor unit circuit shown in , for example, multiple memristor unit circuits form an array of m rows and n columns, m is an integer greater than 1, and n is an integer greater than 1. Figure 2 Where BL(1,1), BL(1,2)...BL(m,n) represent the bit lines of the first row and the first column, the first row and the second column...the mth row and the nth column respectively, the BL1 terminal in each memristor unit circuit is connected to the bit line at the corresponding position, and the SL2 terminal in each memristor unit circuit is connected to the BL2 terminal of the adjacent memristor in the same row; Figure 2 Where WL(1,1), WL(2,1) ... WL(n,1) represent the main word lines of the first column, the second column ... the nth column respectively, and the gate of the transistor M1 in each column of the memristor unit circuit is connected in parallel to the main word line corresponding to the column; Figure 2 WL(1,2), WL(2,2) ... WL(n,2) in the figure represent auxiliary word lines of the first column, the second column ... the nth column respectively, and the gate of the transistor M2 in each column of the memristor unit circuit is connected in parallel to the auxiliary word line corresponding to the column; Figure 2 SL(1), SL(2) ... SL(n) represent the main source lines of the first column, the second column ... the nth column respectively, and the source SL1 of the transistor M1 in the memristor unit circuit of each column is connected to the main source line corresponding to the column.

[0064] Example 2

[0065] This embodiment is used to illustrate the structure of a 2T1R memristor array of the present invention.

[0066] Figure 3Schematic diagram of the 2T1R unit circuit of the 2T1R memristor array of this embodiment. Figure 1 As shown, the 2T1R unit circuit includes a first transistor M1, a second transistor M2, and a memristor R1.

[0067] It should be noted that the transistors used in the test examples of the present invention can all be thin film transistors or field effect transistors (such as MOS field effect transistors) or other switching devices with the same characteristics. The two transistors used here can be the same or different. The source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be indistinguishable in structure. In the test examples of the present invention, in order to distinguish the electrodes of the two transistors, one of the poles of the first transistor M1 is directly described as the M11 pole and the other pole is the M12 pole, and one of the poles of the second transistor M2 is described as the M21 pole and the other pole is the M22 pole.

[0068] The test example of the present invention does not limit the type of transistor M1 used. For example, when the transistor M1 is an N-type transistor, its gate is connected to the word line terminal WL1, for example, when the word line terminal WL1 is input with a high level, the transistor M1 is turned on; the M11 pole of the transistor M1 can be a source and is configured to be connected to the source line terminal S1, and is connected to the M22 pole of the transistor M2, for example, the transistor M1 can output a current signal to the transistor M2, or receive a reset voltage from the source line terminal S1; the M12 pole of the transistor M1 can be a drain and is configured to be connected to the second pole (for example, the negative pole) of the memristor R1, and the first pole (for example, the positive pole) of the memristor R1 is connected to the bit line terminal BL1, for example, the memristor can receive a set voltage through the bit line terminal BL1. For example, when the transistor M1 is a P-type transistor, its gate is connected to the word line terminal WL1, for example, when a low level is input to the word line terminal WL1, the transistor M1 is turned on; the M11 pole of the transistor M1 can be a drain and is configured to be connected to the source line terminal S1, and is connected to the M22 pole of the transistor M2, for example, the transistor M1 can output a current signal to the transistor M2, or receive a reset voltage from the source line terminal S1; the M12 pole of the transistor M1 can be a source and is configured to be connected to the second pole (for example, the negative pole) of the memristor R1, and the first pole (for example, the positive pole) of the memristor R1 is connected to the bit line terminal BL1, for example, the memristor R1 can receive a set voltage through the bit line terminal BL1.

[0069] The experimental example of the present invention does not limit the type of transistor M2 used. For example, when the transistor M2 is an N-type transistor, its gate is connected to the word line terminal WL2. For example, when a high level is input to the word line terminal WL2, the transistor M2 is turned on; the M22 pole of the transistor M2 can be a drain and is configured to be connected to the bit line terminal BL2, and is connected to the M11 pole of the transistor M1. For example, when a current signal is input to the word line terminal BL2, the current will flow into the transistor M2 through the M22 pole of the transistor M2; the M21 pole of the transistor M2 can be a source and is configured to be connected to the source line terminal SL2. For example, when the transistor M2 is turned on, the transistor M2 will output a current signal to the source line terminal SL2. For example, when the transistor M2 is a P-type transistor, its gate is connected to the word line terminal WL2, for example, when a low level is input to the word line terminal WL2, the transistor M2 is turned on; the M22 pole of the transistor M2 can be a drain and is configured to be connected to the bit line terminal BL2, and is connected to the M11 pole of the transistor M1, for example, when a current signal is input to the word line terminal BL2, the current will flow into the transistor M2 through the M22 pole of the transistor M2; the M21 pole of the transistor M2 can be a source and is configured to be connected to the source line terminal SL2, for example, when the transistor M2 is turned on, the transistor M2 will output a current signal to the source line terminal SL2.

[0070] The 2T1R memristor array of the present embodiment used in the following experimental examples is described by taking the transistor M1 as an N-type transistor and the transistor M2 as an N-type transistor as an example.

[0071] The function of the word line terminal WL1 is to apply a corresponding voltage to the gate of the transistor M1, thereby controlling the transistor M1 to be turned on or off. When operating the memristor R1, such as performing a set operation or a reset operation, it is necessary to turn on the transistor M1 first, that is, it is necessary to apply a turn-on voltage to the gate of the transistor M1 through the word line terminal WL1. After the transistor M1 is turned on, for example, a voltage can be applied to the memristor R1 through the source line terminal SL1 or SL2 and the bit line terminal BL1 to change the resistance state of the memristor R1. For example, a set voltage can be applied through the bit line terminal BL1 to make the memristor R1 in a low resistance state; for another example, a reset voltage can be applied through the source line terminal SL1 or SL2 to make the memristor R1 in a high resistance state.

[0072] The function of the word line terminal WL2 is to apply a corresponding voltage to the gate of the transistor M2, thereby controlling the transistor M2 to be turned on or off. For example, when the transistor M2 is turned on, the level of the source line terminal SL2 is related to the source line terminal SL1 or the bit line terminal BL1; for another example, when the transistor M2 is turned off, the level of the source line terminal SL2 is independent of the source line terminal SL1 or the word line terminal BL1.

[0073] It should be noted that, in the experimental example of the present invention, by applying voltage simultaneously through the word line terminal WL1 and the bit line terminal BL1, the resistance value of the memristor R1 becomes smaller and smaller, that is, the memristor R1 changes from a high resistance state to a low resistance state, which makes the operation of changing the memristor R1 from a high resistance state to a low resistance state a set operation; by applying voltage simultaneously through the word line terminal WL1 and the source line terminal SL1 or SL2, the resistance value of the memristor R1 becomes larger and larger, that is, the memristor R1 changes from a low resistance state to a high resistance state, which makes the operation of changing the memristor R1 from a low resistance state to a high resistance state a reset operation. For example, the memristor R1 has a threshold voltage, and when the input voltage amplitude is less than the threshold voltage of the memristor R1, the resistance value (or conductance value) of the memristor R1 will not be changed. In this case, the resistance value (or conductance value) of the memristor R1 can be used for calculation by inputting a voltage less than the threshold voltage; the resistance value (or conductance value) of the memristor R1 can also be changed by inputting a voltage greater than the threshold voltage.

[0074] Figure 4 The 2T1R memristor array of this embodiment is shown, and the memristor array is composed of multiple Figure 3 The 2T1R memristor unit circuit shown in , for example, multiple memristor unit circuits form an array of m rows and n columns, m is an integer greater than 1, and n is an integer greater than 1. Figure 2 BL1, BL2, ..., BLm represent the bit lines of the first row, the first row, ..., the mth row, respectively, and the BL1 end of the memristor unit circuit located in the same row is connected in parallel to the bit line of the corresponding row; Figure 4 Where WL(1,1), WL(2,1) ... WL(n,1) represent the main word lines of the first column, the second column ... the nth column respectively, and the gate of the transistor M1 in each column of the memristor unit circuit is connected in parallel to the main word line corresponding to the column; Figure 4 WL(1,2), WL(2,2) ... WL(m-1,2) in the figure represent auxiliary word lines of the first row, the second row ... the m-1th row, respectively, and the gate of the transistor M2 in each row of memristor unit circuits is connected in parallel to the auxiliary word line corresponding to the row; Figure 4 SL(1,1), SL(1,2)...SL(m,n) in the figure represent the source lines of the first row and first column, the first row and second column...the mth row and nth column respectively. The SL1 terminal in each memristor unit circuit is connected to the source line at the corresponding position, and the SL2 terminal in each memristor unit circuit is connected to the BL2 terminal of the adjacent memristor in the same column.

[0075] Memristor arrays are good at running multiplication and accumulation operations in parallel, and 1T1R memristor arrays are usually used to implement various algorithms that include multiplication and accumulation operations. Single-layer calculations of fully connected neural networks and convolution calculations in convolutional neural networks contain a large number of multiplication and accumulation calculations. Therefore, the present invention takes matrix multiplication calculations, fully connected calculations, convolution calculations and set operations as examples to demonstrate how 2T1R memristor arrays can improve the degree of parallelism and accelerate the calculation process.

[0076] Test Example 1

[0077] The 2T1R memristor array can realize the function of the 1T1R memristor array. This experimental example uses the 2T1R memristor array of embodiment 1 with m rows and n columns to realize the multiplication calculation between a matrix with m rows and n columns and a vector with m rows and 1 column.

[0078] A matrix with m rows and n columns can be represented as Figure 2 The 2T1R memristor array with m rows and n columns is shown in Figure 1. For example, the m values ​​in the first column of the matrix are represented as Figure 2 The conductance values ​​of the m memristors in the first column of the memristor array shown in FIG. 1 and the m values ​​in the second column of the matrix are expressed as follows: Figure 2 The conductance values ​​of the m memristors in the second column of the memristor array shown in the figure are expressed as follows: Figure 2 The conductance values ​​of the m memristors in the nth column of the memristor array shown.

[0079] The vector of m rows and 1 column can be represented as a set of voltage excitations. For example, the voltage excitation is applied to the bit lines BL(1,1), BL(2,1) ... BL(m,1) of the 2T1R memristor array.

[0080] The result of the multiplication between an m-row, n-column matrix and an m-row, 1-column vector is an m-row, 1-column vector, which can be represented as a set of current outputs, for example, the current outputs collected on the source lines SL(1), SL(2) ... SL(n) of a 2T1R memristor array.

[0081] The operation method of the 2T1R memristor array is to apply voltage excitation and collect current output. For example, a high level is applied to all the main word lines and auxiliary word lines of the 2T1R memristor array to turn on all transistors, and voltage excitation is input to the bit lines BL(1,1), BL(2,1)...BL(m,1) of the 2T1R memristor array in parallel, and the output current representing the calculation result is collected on the source lines SL(1), SL(2)...SL(n) of the 2T1R memristor array. According to Kirchhoff's law, the 2T1R memristor array can complete multiplication and accumulation operations in parallel.

[0082] In the above operation method, the purpose of turning on the transistor of the main word line is to allow the memristor of the corresponding column to participate in the calculation, and the purpose of turning on the transistor of the auxiliary word line is to connect the bit lines on both sides of the transistor. When all the transistors corresponding to the auxiliary word lines are turned on, the 2T1R memristor array of embodiment 1 with m rows and n columns is similar to the 1T1R memristor array with m rows and n columns in operation method and function. In this experimental example, the 2T1R memristor array of embodiment 1 can complete the calculation task of the 1T1R memristor array in parallel to the same degree.

[0083] Test Example 2

[0084] The 2T1R memristor array can realize the function of the 1T1R memristor array. This experimental example uses the 2T1R memristor array of Example 2 with m rows and n columns to realize the multiplication calculation between a matrix with m rows and n columns and a vector with m rows and 1 column.

[0085] A matrix with m rows and n columns can be represented as Figure 4 The 2T1R memristor array with m rows and n columns is shown in Figure 1. For example, the m values ​​in the first column of the matrix are represented as Figure 4 The conductance values ​​of the m memristors in the first column of the memristor array shown in FIG. 1 and the m values ​​in the second column of the matrix are expressed as follows: Figure 4 The conductance values ​​of the m memristors in the second column of the memristor array shown in the figure are expressed as follows: Figure 4 The conductance values ​​of the m memristors in the nth column of the memristor array shown.

[0086] The vector of m rows and 1 column can be represented as a set of voltage excitations. For example, the voltage excitation is applied to the bit lines BL1, BL2, ..., BLm of the 2T1R memristor array.

[0087] The result of the multiplication between an m-row, n-column matrix and an m-row, 1-column vector is an m-row, 1-column vector, which can be represented as a set of current outputs. For example, the current outputs collected on the source lines SL(m,1), SL(m,2) ... SL(m,n) of a 2T1R memristor array.

[0088] The operation method of the 2T1R memristor array is to apply voltage excitation and collect current output. For example, a high level is applied to all the main word lines and auxiliary word lines of the 2T1R memristor array to turn on all transistors, and voltage excitation is input to the bit lines BL1, BL2...BLm of the 2T1R memristor array in parallel, and the output current representing the calculation result is collected on the source lines SL(m,1), SL(m,2)...SL(m,n) of the 2T1R memristor array. According to Kirchhoff's law, the 2T1R memristor array can complete multiplication and accumulation operations in parallel.

[0089] In the above operation method, the purpose of turning on the transistor of the main word line is to allow the memristor of the corresponding column to participate in the calculation, and the purpose of turning on the transistor of the auxiliary word line is to connect the bit lines on both sides of the transistor. When all the transistors corresponding to the auxiliary word lines are turned on, the 2T1R memristor array of embodiment 2 with m rows and n columns is similar to the 1T1R memristor array of m rows and n columns in operation method and function. In this experimental example, the 2T1R memristor array of embodiment 2 can complete the calculation task of the 1T1R memristor array in parallel to the same degree.

[0090] Test column 3

[0091] The single-layer calculation of a fully connected neural network includes a large number of multiplication and accumulation operations. This experimental example uses a 2T1R memristor array of Example 1 with m rows and n columns to implement a fully connected calculation with m×n input neuron nodes and 1 output neuron node.

[0092] Figure 5A A schematic diagram of a single-layer computation of a fully connected neural network. Figure 5B Implementation of the 2T1R memristor array based on Example 1 Figure 5A Schematic diagram of the fully connected computation in .

[0093] like Figure 5A As shown, a single layer of the fully connected neural network has m×n input neuron nodes and 1 output neuron node. Figure 5A The full connection calculation shown is equivalent to the vector multiplication between a 1-row, m×n-column matrix and an m×n-row, 1-column vector.

[0094] like Figure 5B As shown, a matrix of 1 row and m×n columns can be represented as a 2T1R memristor array of embodiment 1 with m rows and n columns. For example, the m values ​​of the matrix from row 1 and column 1 to row 1 and column m can be represented as Figure 5B The conductance values ​​of the m memristors in the first column of the memristor array shown in the figure, and the m values ​​from the first row, the m+1 column to the first row, the 2m+1 column can be expressed as Figure 5B The conductance values ​​of the m memristors in the second column of the memristor array shown in the figure are given in Table 1. Similarly, the m values ​​in the first row, the m(n-1)+1 column, and the first row, the m×n column can be expressed as Figure 5B The conductance values ​​of the m memristors in the nth column of the memristor array shown.

[0095] A vector of m×n rows and 1 column can be represented as n groups of voltage excitations. For example, the first group of m voltage excitations are applied to the bit lines BL(1,1), BL(2,1) ... BL(m,1) of the first column of the 2T1R memristor array, the second group of m voltage excitations are applied to the bit lines BL(1,2), BL(2,2) ... BL(m,2) of the second column of the 2T1R memristor array, and so on, the nth group of m voltage excitations are applied to the bit lines BL(1,n), BL(2,n) ... BL(m,n) of the nth column of the 2T1R memristor array.

[0096] The result of the multiplication between a 1-row, m×n-column matrix and an m×n-row, 1-column vector is a 1-row, 1-column vector, which can be represented as the sum of a set of current outputs. For example, the sum of the current outputs collected on the source lines SL(1), SL(2)…SL(n) of the 2T1R memristor array.

[0097] The operation method of the 2T1R memristor array is to apply voltage excitation and collect current output. For example, a high level is applied to all the main word lines of the 2T1R memristor array to turn on all the M1 transistors, and a low level is applied to all the auxiliary word lines of the 2T1R memristor array to turn off all the M2 transistors. The bit lines BL(1,1), BL(2,1)...BL(m,1)...BL(1,n), BL(2,n)...BL(m,n) of the 2T1R memristor array are input with voltage excitation in parallel, and the output current is collected on the source lines SL(1), SL(2)...SL(n) of the 2T1R memristor array and summed to obtain the calculation result. According to Kirchhoff's law, the 2T1R memristor array can complete in parallel Figure 5A The fully connected computation shown.

[0098] In the above operation method, the purpose of turning on the M1 transistor by the main word line is to allow the memristor of the corresponding column to participate in the calculation, and the purpose of turning off the M2 transistor by the auxiliary word line is to disconnect the bit lines on both sides of the M2 transistor. When all the M2 transistors corresponding to the auxiliary word lines are turned off, the 2T1R memristor array with m rows and n columns is similar to the 1T1R memristor array with n m rows and 1 column in operation method and function. Figure 5A For the fully connected computing task shown in the figure, since there are only m bit lines that can be stimulated by voltage, n different voltage stimulations need to be applied respectively to complete the entire computing task. In this experimental example, the 2T1R memristor array of Example 1 improves the degree of parallelism. The 2T1R memristor array of Example 1 completes Figure 5A The time required for the fully connected computing task shown is 1 / n of the time required for the 1T1R memristor array to complete the same computing task.

[0099] Test Example 4

[0100] Convolutional neural networks include a large number of convolution calculations, which are essentially multiplication and addition operations. This experimental example uses a 9-row and 2n-column 2T1R memristor array of Example 1 to implement convolution calculations. For example, the convolution calculation uses 1 convolution kernel group, which includes 2 convolution kernels of size 3×3.

[0101] Fig. 6A A schematic diagram of convolution calculation of a convolutional neural network. Figure 6B Implementation of the 2T1R memristor array based on Example 1 Fig. 6A Schematic diagram of the convolution calculation in .

[0102] like Fig. 6A As shown in the figure, the convolutional neural network in this test example uses 1 convolution kernel group to perform convolution operation on the processed image. The convolution kernel group in this test example contains 1 convolution kernel, and the convolution kernel size is 3×3. The convolution calculation in this test example can be equivalent to the multiplication and accumulation operation between the image pixel value and the convolution kernel.

[0103] like Figure 6B As shown, a 2T1R memristor array of embodiment 1 with 9 rows and 2n columns is used to represent the value in the convolution kernel. For example, the conductance values ​​of the 9 memristors in the 1st column of the 2T1R memristor array are used to represent the 9 weights w11, w12, ..., w19 in the convolution kernel 1, and the conductance values ​​of the 9 memristors in the 2nd column of the 2T1R array are used to represent the 9 weights w21, w22, ..., w29 in the convolution kernel 2; the conductance values ​​of the memristors in the 3rd column, the 5th column, ..., and the 2n-1th column of the 2T1R memristor array correspond to the same conductance values ​​of the memristors in the 1st column, and the conductance values ​​of the memristors in the 4th column, the 6th column, ..., and the 2nth column of the 2T1R memristor array correspond to the same conductance values ​​of the memristors in the 2nd column.

[0104] The convolution layer performs convolution processing on the image to be processed. It is necessary to divide the image to be processed into multiple sub-images, and the size of each sub-image is the same as the size of the convolution kernel. The pixel values ​​of the sub-image can be represented as a set of voltage excitations. For example, the 9 voltage excitations corresponding to the 9 pixel values ​​of the first sub-image are applied to the bit lines BL(1,1), BL(2,1)...BL(9,1) of the first column of the 2T1R memristor array, and the 9 voltage excitations corresponding to the 9 pixel values ​​of the second sub-image are applied to the bit lines BL(1,3), BL(2,3)...BL(9,3) of the third column of the 2T1R memristor array. Similarly, the 9 voltage excitations corresponding to the 9 pixel values ​​of the nth sub-image are applied to the bit lines BL(1,n), BL(2,n)...BL(9,n) of the 2n-1th column of the 2T1R memristor array.

[0105] The result of the convolution calculation corresponding to each convolution kernel is a set of scalar values, which can be represented as a set of current outputs, for example, the current output values ​​collected on the source lines SL(1) and SL(2) ... SL(2n) of the 2T1R memristor array.

[0106] The operation method of the 2T1R memristor array is to apply voltage excitation and collect current output. For example, a high level is applied to all the main word lines of the 2T1R memristor array to turn on all M1 transistors. A high level is applied to the auxiliary word lines of the 1st column, 3rd column, ..., 2n-1th column of the 2T1R memristor array to turn on the M2 transistors of the corresponding columns, and a low level is applied to the auxiliary word lines of the 2nd column, 4th column, ..., 2n-2th column of the 2T1R memristor array to turn off the M2 transistors of the corresponding columns. The output current value is collected on the source lines SL(1), SL(2) ... SL(2n) of the 2T1R memristor array as the calculation result. According to Kirchhoff's law, the 2T1R memristor array can complete in parallel. Fig. 6A The convolution calculation shown.

[0107] In the above operation method, the purpose of the main word line turning on the M1 transistor is to allow the corresponding column of memristors to participate in the calculation, the purpose of the auxiliary word line turning on some columns of M2 transistors is to connect the bit lines between the memristors corresponding to two convolution cores in the same convolution core group, and the purpose of the auxiliary word line turning off some columns of M2 transistors is to disconnect the bit lines between the memristors of different convolution core groups.

[0108] In this experimental example, the 2T1R memristor array of Example 1 with 9 rows and 2n columns is similar in operation method and function to n 1T1R memristor arrays with 9 rows and 2 columns. Fig. 6A For the convolution calculation task shown in the figure, since there are only 9 bit lines that can apply voltage excitation, the data of each sub-graph needs to be serially input into the 1T1R memristor array in batches, so n different voltage excitations need to be applied respectively to complete the entire calculation task. In this experimental example, the 2T1R memristor array of Example 1 improves the degree of parallelism. The 2T1R memristor array of Example 1 completes Fig. 6A The time required for the fully connected computing task shown is 1 / n of the time required for the 1T1R memristor array to complete the same computing task.

[0109] Test Example 5

[0110] This experimental example uses a 2T1R memristor array of Example 2 with 18 rows and 2 columns to implement convolution calculation. For example, the convolution calculation uses 1 convolution kernel group, and the convolution kernel group includes 2 convolution kernels of size 3×3.

[0111] Fig. 6AA schematic diagram of convolution calculation of a convolutional neural network. Figure 7 Implementation of the 2T1R memristor array based on Example 2 Fig. 6A Schematic diagram of the convolution calculation in .

[0112] like Fig. 6A As shown in the figure, the convolutional neural network in this test example uses 1 convolution kernel group to perform convolution operation on the processed image. The convolution kernel group in this test example contains 1 convolution kernel, and the convolution kernel size is 3×3. The convolution calculation in this test example can be equivalent to the multiplication and accumulation operation between the image pixel value and the convolution kernel.

[0113] like Figure 7 As shown, a 2T1R memristor array of embodiment 2 with 18 rows and 2 columns is used to represent the values ​​in the convolution kernel. For example, the conductance values ​​of the 9 memristors in the 1st column and the 1st row to the 1st column and the 9th row in the 2T1R memristor array are used to represent the 9 weights w1,1, w1,2...w1,9 in the convolution kernel 1, and the conductance values ​​of the 9 memristors in the 2nd column and the 1st row to the 2nd column and the 9th row in the 2T1R array are used to represent the 9 weights w2,1, w2,2...w2,9 in the convolution kernel 2; the conductance values ​​of the memristors in the 10th row to the 18th row in the 2T1R memristor array are the same as the conductance values ​​of the memristors in the 1st row to the 9th row.

[0114] The convolution layer performs convolution processing on the image to be processed. It is necessary to divide the image to be processed into multiple sub-images, and the size of each sub-image is the same as the size of the convolution kernel. The pixel values ​​of the sub-image can be represented as a set of voltage excitations. For example, the 9 voltage excitations corresponding to the 9 pixel values ​​of the first sub-image are applied to the bit lines BL1, BL2...BL9 of the 1st to 9th rows of the 2T1R memristor array, and the 9 voltage excitations corresponding to the 9 pixel values ​​of the second sub-image are applied to the bit lines BL10, BL11...BL18 of the 10th to 18th rows of the 2T1R memristor array.

[0115] The result of the convolution calculation corresponding to each convolution kernel is a set of scalar values, and the calculation result can be represented as a set of current outputs. For example, the current output values ​​collected on the source lines SL(9,1), SL(9,2), SL(18,1), SL(18,2) of the 2T1R memristor array.

[0116] The operation method of the 2T1R memristor array is to apply voltage excitation and collect current output. For example, a high level is applied to all the main word lines of the 2T1R memristor array to turn on all M1 transistors. A high level is applied to the auxiliary word lines of the 1st row, 2nd row... 8th row, 10th row, 11th row... 17th row of the 2T1R memristor array to turn on the M2 transistors of the corresponding columns, and a low level is applied to the auxiliary word line of the 9th row of the 2T1R memristor array to turn off the M2 transistors of the corresponding row. The output current values ​​are collected on the source lines SL(9,1), SL(9,2), SL(18,1), SL(18,2) of the 2T1R memristor array as calculation results. According to Kirchhoff's law, the 2T1R memristor array can complete in parallel. Fig. 6A The convolution calculation shown.

[0117] In the above operation method, the purpose of the main word line turning on the M1 transistor is to allow the corresponding column of memristors to participate in the calculation, the purpose of the auxiliary word line turning on some rows of M2 transistors is to connect the source lines between the memristors corresponding to the same convolution kernel, and the purpose of the auxiliary word line turning off some columns of M2 transistors is to disconnect the source lines between the memristors of different convolution kernels.

[0118] In this experimental example, the 2T1R memristor array of Example 2 with 18 rows and 2 columns is similar in operation method and function to two 1T1R memristor arrays with 18 rows and 2 columns. Fig. 6A The convolution calculation task shown in the figure has only two source lines that can output current signals, and the data of each sub-graph needs to be serially input into the 1T1R memristor array in batches, so n different voltage excitations need to be applied respectively to complete the entire calculation task. In this experimental example, the 2T1R memristor array of Example 2 improves the degree of parallelism. The 2T1R memristor array of Example 2 completes Fig. 6A The time required for the fully connected computing task shown is 1 / 2 of the time required for the 1T1R memristor array to complete the same computing task.

[0119] Test Example 6

[0120] The conductance value of each memristor in the memristor array needs to be adjusted through set operation and reset operation. In this test example, a 2T1R memristor array of embodiment 1 with m rows and n columns is set in parallel to adjust the conductance value of its memristor.

[0121] Figure 8 It is a schematic diagram of implementing a parallel set operation of a 2T1R memristor array based on Example 1.

[0122] like Figure 8As shown, in this experimental example, a parallel setting operation is performed on some memristors in the 2T1R memristor array of embodiment 1 with m rows and n columns to adjust the conductance value of the memristor.

[0123] When a set operation is performed on a column of memristors alone, the source line of this column is grounded, the bit lines of the rows where the memristors that need to be set in this column are located are connected to the set voltage, and the bit lines of the rows where the memristors that do not need to be set in this column are located are grounded.

[0124] Figure 8 The V shown represents the voltage applied to the corresponding bit line of the memristor during the set operation, and its value depends on whether the memristor needs a set operation in an actual application. If a set operation is required, the set voltage is connected, and if a set operation is not required, it is grounded.

[0125] The method for performing parallel set operation of 2T1R memristor array is to apply the required voltage excitation. For example, a high level is applied to all main word lines of 2T1R memristor array to turn on all M1 transistors, a low level is applied to all auxiliary word lines of 2T1R memristor array to turn off all M2 transistors, the required voltage excitation is input to the bit lines BL(1,1), BL(2,1)...BL(m,1)...BL(1,n), BL(2,n)...BL(m,n) of 2T1R memristor array in parallel, and the source lines SL(1), SL(2)...SL(n) of 2T1R memristor array are grounded. According to the above operation flow, 2T1R memristor array can complete the set operation in parallel.

[0126] In the above operation method, the purpose of the main word line turning on the M1 transistor is to allow the memristor of the corresponding column to participate in the set operation, and the purpose of the auxiliary word line turning off the M2 transistor is to disconnect the bit lines on both sides of the M2 transistor. When all the M2 transistors corresponding to the auxiliary word lines are turned off, the 2T1R memristor array of m rows and n columns is similar to the 1T1R memristor array of n m rows and 1 column in the method and effect of the set operation. If the 1T1R memristor array of m rows and n columns is to be set, since it has only m bit lines to apply voltage excitation, it is necessary to apply n different voltage excitations respectively to achieve the set operation of the memristors of all columns. In this experimental example, the 2T1R memristor array of Example 1 improves the degree of parallelism, and the time required for the 2T1R memristor array of Example 1 to complete the set operation task is 1 / n of the time required for the 1T1R memristor array to complete the same computing task.

[0127] Although the present invention has been described to a certain extent, it is obvious that appropriate changes in various conditions can be made without departing from the spirit and scope of the present invention. It is understood that the present invention is not limited to the embodiments described, but belongs to the scope of the claims, which includes equivalent replacements of each factor described.

Claims

1. A 2T1R array based on memristor, characterized in that: The 2T1R array includes interconnected 2T1R memristor unit circuits, the 2T1R memristor unit circuits are composed of a first transistor, a second transistor and a memristor, the 2T1R array is a cross structure, and the 2T1R memristor unit circuit is located at a cross point of the array; wherein, The source of the first transistor located in the same column of the array is connected in parallel to the bottom electrode of the array, the gate of the first transistor located in the same column of the array is connected in parallel to the same electrode, the negative electrode of the memristor is connected in series with the drain of the first transistor, the positive electrode of the memristor is connected in series with the drain of the second transistor, the positive electrode of each memristor is connected to an electrode, the second transistors located in the same row of the array are connected in series through the source and the drain, and the gate of the second transistor located in the same column of the array is connected in parallel to the same electrode.

2. The memristor-based 2T1R array according to claim 1, characterized in that: The first transistor is the same as or different from the second transistor.

3. The memristor-based 2T1R array according to claim 2, characterized in that: The first transistor and / or the second transistor is a switching device.

4. The memristor-based 2T1R array according to claim 3, characterized in that: The first transistor and / or the second transistor is selected from one or more of the following: a thin film transistor, a field effect transistor, and a bipolar transistor.

5. The memristor-based 2T1R array according to claim 4, characterized in that: The field effect transistor is a MOS field effect transistor.

6. The memristor-based 2T1R array according to claim 1, characterized in that: In the 2T1R array, the top electrodes of the memristors in the same row are connected in series through the second transistor in the memristor unit circuit, and each top electrode in the same row can be connected to a different external electrode.

7. A 2T1R array based on memristors, characterized in that: The 2T1R array includes interconnected 2T1R memristor unit circuits, the 2T1R memristor unit circuits are composed of a first transistor, a second transistor and a memristor, the 2T1R array is a cross structure, and the 2T1R memristor unit circuit is located at a cross point of the array; wherein, The source of the first transistor is connected in series with the drain of the second transistor, the second transistors in the same column of the array are connected in series through the source and the drain, the source of each first transistor is connected to an electrode, the negative electrode of the memristor is connected in series with the drain of the first transistor, the positive electrodes of the memristors in the same row of the array are connected in series to the same electrode, the gates of the second transistors in the same row of the array are connected in parallel to the same electrode, and the gates of the first transistors in the same column of the array are connected in parallel to the same electrode.

8. The memristor-based 2T1R array according to claim 7, characterized in that: In the 2T1R array, the sources of the first transistors of the memristor unit circuits in the same column are connected in series through the second transistors in the unit circuits, and the source of each first transistor can be connected to different external electrodes.

9. A parallel operation method, characterized in that: The parallel operation method uses the memristor-based 2T1R array according to any one of claims 1 to 8 to perform parallel operation.

10. The parallel operation method according to claim 9, characterized in that: The parallel operation method includes: controlling the on and off of the second transistor, functionally dividing the memristor array into a plurality of sub-arrays, and performing a set operation or a reset operation on each sub-array at the same time, so as to realize parallel acceleration state adjustment.

11. The parallel operation method according to claim 10, characterized in that: The parallel operation method includes: by controlling the conduction and closing of the second transistor array in the array, functionally dividing the memristor array into multiple sub-arrays, each memristor unit circuit simultaneously receives different voltage excitations, thereby simultaneously performing a set operation or a reset operation to achieve parallel state adjustment.

12. A parallel operation method, characterized in that: The parallel operation method uses the memristor-based 2T1R array according to any one of claims 1 to 6 to perform parallel operation; and the parallel operation method comprises: Controlling all the second transistors in the array to be turned on, so that the top electrodes of the memristor unit circuits in the same row in the 2T1R memristor array receive voltage excitation through the same external electrode; Controlling the second transistors in the array to be all turned off, so that the top electrodes of the memristor unit circuits in the same row in the 2T1R memristor array are respectively connected to different external electrodes, receive different voltage excitations, and do not affect the memristor unit circuits in adjacent columns; and / or The second transistors located in different columns of the array are respectively controlled to be turned on and off, so that the 2T1R memristor array is functionally divided into different sub-arrays in units of columns, the second transistors inside the sub-arrays are turned on, and the second transistors between two adjacent sub-arrays are turned off, the top electrodes of the memristor unit circuits located in the same row inside each sub-array receive voltage excitation through the same external electrode, different sub-arrays are respectively connected to different external electrodes, receive different voltage excitations, and will not affect adjacent sub-arrays.

13. A parallel operation method, characterized in that: The parallel operation method uses the memristor-based 2T1R array according to claim 7 or 8 to perform parallel operation; and the parallel operation method includes: Controlling all the second transistors in the array to be turned on, so that the bottom electrodes of the memristor unit circuits in the same column in the 2T1R memristor array are connected in parallel to the same external electrode to output a current signal; Controlling the second transistors in the array to be completely turned off, so that the bottom electrodes of the memristor unit circuits in the same column of the 2T1R memristor array are respectively connected to different external electrodes, outputting respective current signals, and not being accumulated with the current signals output by the memristor unit circuits in adjacent rows; and / or The second transistors located in different rows in the array are respectively controlled to be turned on and off, so that the 2T1R memristor array is functionally divided into different sub-arrays in units of rows, the second transistor array inside the sub-array is turned on, and the second transistor array between two adjacent sub-arrays is turned off, the bottom electrodes of the memristor unit circuits located in the same column inside each sub-array are connected in parallel to the same external electrode to output a current signal, different sub-arrays are respectively connected to different external electrodes, output different current signals, and will not affect adjacent sub-arrays.

14. A method for calculating a convolutional neural network, characterized in that: The computing method uses the memristor-based 2T1R array described in any one of claims 1 to 8 or the parallel operation method described in any one of claims 9 to 13 to perform convolution computing.

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