Mask plate pattern, semiconductor structure and method for forming semiconductor structure

Abstract

A mask layout, a semiconductor structure and a method for forming a semiconductor structure, wherein the mask layout includes: a first area, a second area and a third area arranged along a first direction, the third area is located between the first area and the second area; a plurality of first graphics located in the first area, the first graphics extending along the first direction; a plurality of second graphics located in the second area, the second graphics extending along the first direction; a plurality of third graphics located in the third area, each third graphic being connected to a first graphic and a second graphic at both ends, respectively. Thus, the reliability of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a mask pattern, a semiconductor structure and a method for forming the semiconductor structure. Background Art

[0002] With the continuous advancement of semiconductor integrated circuit manufacturing technology, the performance is constantly improving, and at the same time, the device is miniaturized and micro-miniaturized. More and more advanced processes require as many devices as possible to be implemented in the smallest possible area.

[0003] In ultra-large-scale integrated circuits, the use of metal interconnection layers is one of the methods for achieving electrical interconnection between devices. Usually, a cut layer is used to insulate adjacent metal interconnection layers, so that the spacing between the ends of adjacent metal interconnection layers needs to be smaller than the exposure limit size of the exposure process, so as to increase the density of the metal interconnection layer and improve the integration of the integrated circuit.

[0004] However, the reliability of existing semiconductor structures is still poor. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a mask pattern, a semiconductor structure and a method for forming the semiconductor structure, so as to improve the pattern accuracy of the cutting layer, reduce the short-circuit defects of the interconnection layer, and thus improve the reliability of the semiconductor structure.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a mask plate pattern, including: a first area, a second area and a third area arranged along a first direction, the third area is located between the first area and the second area; a plurality of first graphics located in the first area, the first graphics extending along the first direction; a plurality of second graphics located in the second area, the second graphics extending along the first direction; a plurality of third graphics located in the third area, each third graphic being connected to a first graphic and a second graphic at both ends respectively.

[0007] Optionally, each of the first figures has a first center line in the first direction, and each of the second figures has a second center line in the first direction, the first center lines and the second center lines are arranged along the second direction, and there are no more than two second center lines between every two adjacent first center lines, and the second direction is perpendicular to the first direction.

[0008] Optionally, the first graphic has a first end, the second graphic has a second end, the first ends and the second ends of adjacent first and second graphics are adjacent, and there is an end spacing between the adjacent first and second ends, and the maximum value of the end spacing is 50 nanometers.

[0009] Optionally, the third figure has a third end and a fourth end, the third end is connected to the first end, and the fourth end is connected to the second end.

[0010] Correspondingly, the technical solution of the present invention also provides a semiconductor structure, including: a substrate, the substrate including a first zone, a second zone and a third zone arranged along a first direction, the third zone being located between the first zone and the second zone; a plurality of first grooves located in the first zone, the first grooves extending along the first direction; a plurality of second grooves located in the second zone, the second grooves extending along the first direction; a plurality of third grooves located in the third zone, each of the third grooves being respectively connected to a first groove and a second groove; and a cutting layer located in the connected first grooves, second grooves and third grooves.

[0011] Optionally, the first groove has a first center line in the first direction, the second groove has a second center line in the first direction, the first center line and the second center line are arranged along the second direction, and there are no more than two second center lines between every two adjacent first center lines, and the second direction is perpendicular to the first direction.

[0012] Optionally, a minimum distance between adjacent first grooves and second grooves is less than 50 nanometers.

[0013] Optionally, the substrate further includes a base and a dielectric layer located on the base, and the first groove, the second groove and the third groove are located in the dielectric layer.

[0014] Optionally, the material of the dielectric layer is different from the material of the cutting layer.

[0015] Optionally, the material of the dielectric layer includes titanium oxide.

[0016] Optionally, the material of the cutting layer includes low-temperature filling oxide.

[0017] Optionally, the method further includes: a plurality of first interconnection openings located in the dielectric layer in the first region, and the first interconnection openings are located on both sides of the first groove.

[0018] Optionally, the method further includes: a first interconnection layer located in the first interconnection opening.

[0019] Optionally, the method further includes: a plurality of second interconnection openings located in the dielectric layer of the second region, and the second interconnection openings are located on both sides of the second groove.

[0020] Optionally, the method further includes: a second interconnect layer located in the second interconnect opening.

[0021] Optionally, the method further includes: a third interconnect opening located in the dielectric layer in the third region, and the third interconnect opening penetrates the cutting layer along the second direction.

[0022] Optionally, the method further includes: a third interconnect layer located in the third interconnect opening.

[0023] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a first region, a second region and a third region arranged along a first direction, the third region being located between the first region and the second region; forming a plurality of first grooves in the first region, the first grooves extending along the first direction; forming a plurality of second grooves in the second region, the second grooves extending along the first direction; forming a plurality of third grooves in the third region, each of the third grooves being respectively connected to a first groove and a second groove; and forming a cutting layer in the connected first grooves, second grooves and third grooves.

[0024] Optionally, the first groove has a first center line in the first direction, the second groove has a second center line in the first direction, the first center line and the second center line are arranged along the second direction, and there are no more than two second center lines between every two adjacent first center lines, and the second direction is perpendicular to the first direction.

[0025] Optionally, the substrate further includes a base and a dielectric layer located on the base, and the first groove, the second groove and the third groove are located in the dielectric layer.

[0026] Optionally, the method further includes: after forming the cutting layer, forming a plurality of first interconnection openings located on both sides of the first groove in the dielectric layer of the first region.

[0027] Optionally, the method for forming the first interconnect opening includes: forming a first interconnect patterned layer on the surface of the cutting layer, the first interconnect patterned layer having a plurality of first patterned openings of the cutting layer spanning the first region, the first patterned openings exposing the dielectric layer and the cutting layer surface; using the first interconnect patterned layer as a mask, etching the dielectric layer until the substrate surface is exposed.

[0028] Optionally, the method further includes: forming a first interconnect layer in the first interconnect opening.

[0029] Optionally, the method further includes: after forming the cutting layer, forming a plurality of second interconnection openings located on both sides of the second groove in the dielectric layer of the second region.

[0030] Optionally, the method for forming the second interconnect opening includes: forming a second interconnect patterned layer on the surface of the cutting layer, the second interconnect patterned layer having a plurality of second patterned openings of the cutting layer spanning the second region, the second patterned openings exposing the dielectric layer and the cutting layer surface; using the second interconnect patterned layer as a mask, etching the dielectric layer until the substrate surface is exposed.

[0031] Optionally, the method further includes: forming a second interconnect layer in the second interconnect opening.

[0032] Optionally, the method further includes: after forming the cutting layer, forming a third interconnect opening in the dielectric layer in the third region, and the third interconnect opening penetrates the cutting layer along the second direction.

[0033] Optionally, the method for forming the third interconnect opening includes: forming a third interconnect patterned layer on the surface of the cutting layer, the third interconnect patterned layer having a third patterned opening of the cutting layer spanning the third region, the third patterned opening exposing the dielectric layer and the cutting layer surface; using the third interconnect patterned layer as a mask, respectively etching the dielectric layer and the cutting layer until the substrate surface is exposed.

[0034] Optionally, the method further includes: forming a third interconnect layer in the third interconnect opening.

[0035] Optionally, the method for forming the first groove, the second groove and the third groove includes: forming a cutting patterned layer on the surface of the dielectric layer, the cutting patterned layer exposing a portion of the surface of the first area, a portion of the second area and a portion of the third area; using the cutting patterned layer as a mask, etching the dielectric layer until the substrate surface is exposed.

[0036] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0037] In the mask layout provided by the technical solution of the present invention, the first graphic, the second graphic, and the third graphic are used to form a cutting layer. Since each third graphic is connected to a first graphic and a second graphic at both ends, that is, the first graphic and the second graphic are connected by only one connecting structure (third graphic), the shape of the connecting structure is relatively simple, so as to increase the process window size of the subsequent exposure process. Therefore, in the subsequent exposure process, when the distance between the ends of the first graphic and the second graphic is small, the graphic accuracy of the third graphic can be improved while reducing the defect of shortening the ends of the first graphic and the second graphic, so as to form a cutting layer with high graphic accuracy and good morphology, thereby reducing the short-circuit defects of the interconnection layer and improving the reliability of the semiconductor structure.

[0038] Correspondingly, in the method for forming a semiconductor structure of the technical solution of the present invention, since each of the third grooves is respectively connected to one of the first grooves and one of the second grooves, that is, the first groove is connected to the second groove by only one connection structure (the third groove), and a cutting layer is formed in the connected first groove, second groove, and third groove. Therefore, the shape of the connection structure is relatively simple, which increases the process window size of the process for forming the cutting layer. Therefore, the cutting layer in the third groove, at the connection between the third groove and the first groove, and at the connection between the third groove and the second groove is filled more fully and has a better morphology. On the one hand, when the cutting layer is not full, the over-etching defect of the graphic layer below the cutting layer by the subsequent etching process is reduced. On the other hand, the short-circuit defect caused by the incomplete blocking of the subsequent interconnection layers is reduced, thereby improving the reliability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a mask pattern for cutting layer;

[0040] Figures 2 to 4 It is a structural schematic diagram of each step of a method for forming a semiconductor structure;

[0041] Figure 5 is a mask layout of an embodiment of the present invention;

[0042] Figure 6 is a mask pattern according to another embodiment of the present invention;

[0043] Figures 7 to 12 It is a schematic cross-sectional structure diagram of a semiconductor structure forming process according to an embodiment of the present invention. DETAILED DESCRIPTION

[0044] As described in the background art, the reliability of the existing semiconductor structure is still relatively poor. Now, an analysis and description will be given in conjunction with a specific embodiment.

[0045] It should be noted that the “surface” in this specification is used to describe the relative position relationship in space and is not limited to whether there is direct contact.

[0046] Figure 1 It is a mask pattern for cutting layer.

[0047] Please refer to Figure 1 , the mask plate Fig.10The invention comprises: a first zone I, a second zone II and a third zone III arranged along a first direction X, wherein the third zone III is located between the first zone I and the second zone II; a plurality of first graphics 11 located in the first zone I; a plurality of second graphics 12 located in the second zone II, and, along the second direction Y, the second graphics 12 are located between adjacent first graphics 11, and the second direction Y is perpendicular to the first direction X; a plurality of "Y"-shaped third graphics 13 located in the third zone III, and one third graphic 13 respectively connects two adjacent first graphics 11 and one second graphic 12.

[0048] Thus, by connecting the first graphic 11 and the second graphic 12, the defect of shortening of the ends of the photolithography graphics corresponding to the ends 15 and 16 due to the exposure limit when the spacing between the end 15 of the first graphic 11 and the end 16 of the second graphic 12 is small during the exposure process is reduced, thereby reducing the short circuit problem caused by the interconnection layer not being completely blocked by the cutting layer.

[0049] Figures 2 to 4 The present invention is a structural schematic diagram of each step of a method for forming a semiconductor structure.

[0050] Please refer to Figure 2 and Figure 3 , Figure 2 yes Figure 3 Schematic diagram of the cross-sectional structure along Q-Q1, Figure 3 yes Figure 2 A top view structural diagram of a substrate is provided, wherein the substrate has a base 22 and a dielectric layer 20 located on the surface of the base.

[0051] Please Figure 3 Based on reference Figure 4 , a groove 21 is formed in the dielectric layer 20 ; and a cutting layer (not shown) is formed in the groove 21 .

[0052] The method for forming the groove 21 includes: forming a photoresist material layer (not shown) on the surface of the dielectric layer 20; using a mask plate Fig.10 (like Figure 1 As shown), the photoresist material layer is exposed and developed, and the mask plate is Fig.10 The pattern is transferred to the photoresist material layer to form a patterned layer (not shown); the dielectric layer 20 is etched using the patterned layer as a mask until the surface of the substrate 22 is exposed.

[0053] However, in the above embodiment, since the structure of the third graphic 13 is relatively complex and the graphic density is relatively high, the process window at the third graphic 13 is small during the exposure process, so that the spacing between the side walls of the groove 21 in area A (corresponding to the third graphic 13) is uneven. On the one hand, the uneven spacing between the side walls of the groove 21 leads to poor precision and poor morphology of the cutting layer formed in area A, so that the subsequently formed interconnection layer is not completely blocked by the cutting layer, and the short-circuit defects generated increase. On the other hand, the uneven spacing between the side walls of the groove 21 leads to depressions caused by incomplete material filling on the surface of the cutting layer in area A, which not only easily causes the graphic layer below area A to be over-etched during the subsequent etching process, but also increases the short-circuit defects caused by the subsequent interconnection layer not being completely blocked by the cutting layer. In summary, the reliability of the above semiconductor structure is poor.

[0054] To solve the above problems, the technical solution of the present invention provides a mask layout, which increases the reliability of the semiconductor structure by forming a plurality of third graphics in the third area and making each third graphic have two ends connected to a first graphic and a second graphic respectively.

[0055] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0056] Figure 5 This is a mask layout according to an embodiment of the present invention.

[0057] Please refer to Figure 5 The mask pattern 100 includes: a first area I, a second area II and a third area III arranged along a first direction X, the third area III is located between the first area I and the second area II; a plurality of first graphics 101 located in the first area I, the first graphics 101 extending along the first direction X; a plurality of second graphics 102 located in the second area II, the second graphics 102 extending along the first direction X; a plurality of third graphics 103 located in the third area III, each third graphic 103 being connected to a first graphic 101 and a second graphic 102 at both ends thereof.

[0058] The first pattern 101, the second pattern 102, and the third pattern 103 are used to form a cutting layer. Since the two ends of each third pattern 103 are respectively connected to a first pattern 101 and a second pattern 102, that is, the first pattern 101 and the second pattern 102 are connected by only one connection structure (third pattern 103), the shape of the connection structure is relatively simple, so as to increase the process window size of the subsequent exposure process. Therefore, in the subsequent exposure process, when the distance between the ends of the first pattern 101 and the second pattern 102 is small, the pattern accuracy of the third pattern 103 can be improved while reducing the defect of shortening the ends of the first pattern 101 and the second pattern 102, so as to form a cutting layer with high pattern accuracy and good morphology, thereby reducing the short-circuit defects of the interconnection layer and improving the reliability of the semiconductor structure.

[0059] In this embodiment, each of the first figures 101 has a first center line CT1 in the first direction X, and each of the second figures 102 has a second center line CT2 in the first direction X. The first center line CT1 and the second center line CT2 are arranged along the second direction Y, and there are no more than two second center lines CT2 between every two adjacent first center lines CT1, and the second direction Y is perpendicular to the first direction X.

[0060] Specifically, in this embodiment, there is one second center line CT2 between every two adjacent first center lines CT1.

[0061] In another embodiment, there are two second center lines MT2 between every two adjacent first center lines MT1 (eg Figure 6 shown).

[0062] In this embodiment, the first graphic 101 has a first end 111, the second graphic 102 has a second end 112, the first ends 111 and the second ends 112 of the adjacent first graphic 101 and the second graphic 102 are adjacent to each other, and there is an end spacing D1 between the adjacent first ends 111 and the second ends 112, and the maximum value of the end spacing D1 is 50 nanometers.

[0063] If the maximum value of the end spacing D1 is too large, the occupied area of ​​the formed cutting layer will be increased, which is not conducive to improving the integration of the semiconductor structure. Therefore, selecting a suitable end spacing D1 can reduce the short circuit defects of the interconnection layer while improving the integration of the semiconductor structure.

[0064] It should be noted that, in this embodiment, the end distance D1 refers to the distance between the center point K1 of the first end 111 and the center point K2 of the second end 112 .

[0065] In this embodiment, the third graphic 103 has a third end 113 and a fourth end 114 , the third end 113 is connected to the first end 111 , and the fourth end 114 is connected to the second end 112 .

[0066] Specifically, in this embodiment, the inclination direction and inclination angle of each of the third graphics 103 relative to the second direction Y are the same.

[0067] Therefore, the third graphics 103 can be kept relatively uniform in density, thereby increasing the process window size of the subsequent exposure process, reducing the diffraction effect enhanced by the uneven density, and reducing the distortion of the lithography pattern relative to the mask plate.

[0068] It should be noted that the inclination direction of the third figure 103 relative to the second direction Y means that the end connection direction is toward the second direction Y, or the end connection direction is away from the second direction Y, and the end connection direction means that the fourth end 114 points to the direction of the third end 113; the inclination angle of the third figure 103 relative to the second direction Y means that the angle α1 between the center line CT3 of the third figure 103 and the second direction Y is less than or equal to 90 degrees.

[0069] In another embodiment, the third figures have the same inclination direction relative to the second direction, but different inclination angles, that is, in each of the first figures and the second figures connected by the third figures, the first figures are on the same side of the second figure. Thus, the shape of the third figure can be flexibly adjusted according to the positions of the first figure and the second figure.

[0070] In another embodiment, the third graphics 123 have different inclination directions relative to the second direction Y, but the same inclination angle β1, that is, in the first graphics 121 and the second graphics 122 connected by the third graphics 123, the first graphics 121 is on different sides of the second graphics 122 (such as Figure 6 Thus, the shape of the third graphic 123 can be flexibly adjusted according to the positions of the first graphic 121 and the second graphic 122.

[0071] In other embodiments, the inclination directions of the third figures relative to the second direction are different, that is, in the first figures and the second figures connected by the third figures, the first figures are on different sides of the second figures, and the inclination angles of the third figures relative to the second direction are also different. Thus, the shape of the third figure can be flexibly adjusted according to the positions of the first figure and the second figure.

[0072] Figures 7 to 12 It is a schematic cross-sectional structure diagram of a semiconductor structure forming process according to an embodiment of the present invention.

[0073] Accordingly, the present invention also provides a method for forming a semiconductor structure, please refer to Figure 7 and Figure 8 , Figure 7 is a schematic diagram of a top view of a semiconductor structure in an embodiment of the present invention, Figure 8 yes Figure 7 A schematic diagram of the cross-sectional structure along the Z-Z1 direction provides a substrate 200, wherein the substrate 200 includes a first region I, a second region 11, and a third region III arranged along a first direction X, wherein the third region III is located between the first region I and the second region II.

[0074] In this embodiment, the substrate 200 further includes a base 210 and a dielectric layer 220 located on the base 210 .

[0075] The material of the substrate 210 includes semiconductor material.

[0076] In this embodiment, the material of the substrate 210 includes silicon. In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of III-V group elements, silicon on insulator (SOI) or germanium on insulator. Among them, the multi-component semiconductor material composed of III-V group elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0077] In this embodiment, the substrate 210 has a device layer (not shown). The device layer may include a device structure, such as a PMOS transistor or an NMOS transistor. The device layer may also include an interconnection structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnection structure.

[0078] In this embodiment, the material of the dielectric layer 220 is titanium oxide.

[0079] In another embodiment, the material of the dielectric layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon carbon oxynitride.

[0080] Please refer to Fig. 9 A plurality of first grooves 221 are formed in the first zone I, and the first grooves 221 extend along the first direction X; a plurality of second grooves 222 are formed in the second zone II, and the second grooves 222 extend along the first direction X; a plurality of third grooves 223 are formed in the third zone III, and each of the third grooves 223 is respectively connected to one of the first grooves 221 and one of the second grooves 222.

[0081] It should be noted that, since the first groove 221, the second groove 222 and the third groove 223 are connected, for ease of understanding, Fig. 9 The dotted lines in FIG. 2 indicate the boundaries among the first groove 221 , the second groove 222 and the third groove 223 .

[0082] In this embodiment, the first groove 221 , the second groove 222 , and the third groove 223 are located in the dielectric layer 220 .

[0083] The first groove 221 has a first center line DT1 in the first direction X, and the second groove 222 has a second center line DT2 in the first direction X. The first center line DT1 and the second center line DT2 are arranged along the second direction Y, and there are no more than two second center lines DT2 between every two adjacent first center lines DT1, and the second direction Y is perpendicular to the first direction X.

[0084] Specifically, in this embodiment, there is one second center line DT2 between every two adjacent first center lines DT1.

[0085] In yet another embodiment, two second center lines are spaced between every two adjacent first center lines.

[0086] In this embodiment, a minimum distance T1 between adjacent first grooves 221 and second grooves 222 is less than 50 nanometers.

[0087] If the minimum spacing T1 is too large, the occupied area of ​​the subsequently formed cutting layer will increase, which is not conducive to improving the integration of the semiconductor structure. Therefore, selecting a suitable minimum spacing T1 can reduce the short-circuit defects of the interconnection layer while improving the integration of the semiconductor structure.

[0088] It should be noted that, in this embodiment, the minimum distance T1 refers to the distance between the center point P1 of the boundary line between the first groove 221 and the third groove 223 and the center point P2 of the boundary line between the second groove 222 and the third groove 223 .

[0089] In this embodiment, the inclination direction and inclination angle of each of the third grooves 223 relative to the second direction Y are the same. Therefore, the third grooves 223 are kept relatively uniformly spaced, so that when the mask pattern is transferred to the dielectric layer 220, the process window size of the exposure process can be increased, and the diffraction effect enhanced by the uneven density can be reduced to reduce the distortion of the lithography pattern relative to the mask pattern, so as to form the third grooves 223 with better morphology quality, and further, it is beneficial to the subsequent filling process of the cutting layer material in the third grooves 223.

[0090] It should be noted that the inclination direction of the third groove 223 relative to the second direction Y means that the connection direction is toward the second direction Y, or the connection direction is away from the second direction Y, and the connection direction is from the connecting end of the third groove 223 and the second groove 222 to the connecting end of the third groove 223 and the first groove 221; the inclination angle of the third groove 223 relative to the second direction Y means that the angle α2 between the center line DT3 of the third groove 223 and the second direction Y is less than or equal to 90 degrees.

[0091] In another embodiment, the inclination directions of the third grooves relative to the second direction are the same, but the inclination angles are different, that is, in the first grooves and the second grooves connected by the third grooves, the first grooves are on the same side of the second groove.

[0092] In another embodiment, the inclination directions of the third grooves relative to the second direction are different, but the inclination angles are the same, that is, in the first groove and the second groove connected by the third groove, the first groove is on different sides of the second groove.

[0093] In other embodiments, the inclination directions of each third groove relative to the second direction are different, that is, in each first groove and second groove connected by the third groove, the first groove is on different sides of the second groove, and the inclination angles of each third groove relative to the second direction are also different.

[0094] In this embodiment, the method for forming the first groove 221, the second groove 222 and the third groove 223 includes: forming a cutting patterned layer (not shown) on the surface of the dielectric layer 220, wherein the cutting patterned layer exposes a portion of the surface of the first region I, a portion of the second region II and a portion of the third region III; using the cutting patterned layer as a mask, etching the dielectric layer 220 until the surface of the substrate 210 is exposed.

[0095] In this embodiment, the Figure 5 The mask pattern of the embodiment shown forms the cutting patterning layer.

[0096] In this embodiment, the process of etching the dielectric layer 220 includes a dry etching process or a wet etching process.

[0097] Please refer to Fig.10 A cutting layer 230 is formed in the connected first groove 221 , the second groove 222 , and the third groove 223 .

[0098] Since each of the third grooves 223 is respectively connected to one of the first grooves 221 and one of the second grooves 222, that is, the first groove 221 is connected to the second groove 222 by only one connection structure (the third groove 223), and the cutting layer 230 is formed in the connected first grooves 221, second grooves 222, and third grooves 223, the shape of the connection structure is relatively simple, which increases the process window size of the process for forming the cutting layer 230, so that the cutting layer 230 in the third groove 223, at the connection between the third groove 223 and the first groove 221, and at the connection between the third groove 223 and the second groove 222 is filled more fully and has a better morphology. On the one hand, when the cutting layer 230 is not full, the over-etching defect of the graphic layer below the cutting layer 230 by the subsequent etching process is reduced, and on the other hand, the short circuit defect caused by the incomplete blocking between the subsequent interconnection layers is reduced, thereby improving the reliability of the semiconductor structure.

[0099] In this embodiment, the method for forming the cutting layer 230 includes: using a low-temperature oxidation process to form a cutting material layer (not shown) on the surface of the dielectric layer 220 and in the connected first groove 221, second groove 222, and third groove 223; etching back the cutting material layer until the surface of the dielectric layer 220 is exposed.

[0100] In another embodiment, the process of forming the cutting layer includes: a spin coating process, a deposition process or an epitaxial growth process.

[0101] In this embodiment, the cutting layer 230 and the dielectric layer 220 are made of different materials. Therefore, there is a large etching selectivity ratio between the dielectric layer 220 and the cutting layer 230. Therefore, when the dielectric layer 220 is subsequently etched to form the first interconnect opening, the second interconnect opening and the third interconnect opening, the damage of the etching process to the cutting layer 230 can be reduced.

[0102] In this embodiment, the material of the cutting layer 230 is low temperature filling oxide.

[0103] In another embodiment, the material of the cutting layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon carbon oxynitride.

[0104] Please refer to Fig.11After forming the cutting layer 230, a plurality of first interconnection openings 241 are formed in the dielectric layer 220 of the first zone I and located on both sides of the first groove 221; after forming the cutting layer 230, a plurality of second interconnection openings 242 are formed in the dielectric layer 220 of the second zone II and located on both sides of the second groove 222; after forming the cutting layer 230, a third interconnection opening 243 is formed in the dielectric layer 220 of the third zone III, and the third interconnection opening 243 penetrates the cutting layer 230 along the second direction Y.

[0105] In yet another embodiment, the first patterned opening or the second patterned opening is not formed.

[0106] In other embodiments, the third patterned opening is not formed.

[0107] In this embodiment, the method for forming the first interconnect opening 241 includes: forming a first interconnect patterned layer (not shown) on the surface of the cutting layer 230, the first interconnect patterned layer having a plurality of first patterned openings (not shown) spanning the cutting layer 230 of the first region I, the first patterned openings exposing the dielectric layer 220 and the surface of the cutting layer 230; using the first interconnect patterned layer as a mask, etching the dielectric layer 220 of the first region I until the surface of the substrate 210 is exposed.

[0108] In this embodiment, the process of etching the dielectric layer 220 using the first interconnect patterning layer as a mask includes a dry etching process or a wet etching process.

[0109] In this embodiment, the method for forming the second interconnect opening 242 includes: forming a second interconnect patterned layer (not shown) on the surface of the cutting layer 230, the second interconnect patterned layer having a plurality of second patterned openings (not shown) spanning the cutting layer 230 of the second region II, the second patterned openings exposing the dielectric layer 220 and the surface of the cutting layer 230; using the second interconnect patterned layer as a mask, etching the dielectric layer 220 of the second region II until the surface of the substrate 200 is exposed.

[0110] In this embodiment, the process of etching the dielectric layer 220 using the second interconnect patterned layer as a mask includes a dry etching process or a wet etching process.

[0111] In this embodiment, the method for forming the third interconnect opening 243 includes: forming a third interconnect patterned layer (not shown) on the surface of the cutting layer 230, the third interconnect patterned layer having a third patterned opening (not shown) spanning the cutting layer 230 of the third region III, the third patterned opening exposing the surfaces of the dielectric layer 220 and the cutting layer 230; using the third interconnect patterned layer as a mask, respectively etching the dielectric layer 220 and the cutting layer 230 of the third region III until the surface of the substrate 200 is exposed.

[0112] It should be noted that the order of forming the first patterned opening 241 , the second patterned opening 242 , and the third patterned opening 243 does not affect the effect of the present forming method.

[0113] In another embodiment, the first patterned layer and the second patterned layer are the same patterned layer, and therefore, the first patterned opening and the second patterned opening are formed in the same etching step.

[0114] Please refer to Fig.12 , a first interconnection layer 251 is formed in the first interconnection opening 241 ; a second interconnection layer 252 is formed in the second interconnection opening 242 ; and a third interconnection layer 253 is formed in the third interconnection opening 243 .

[0115] In this embodiment, the process of forming the first interconnection layer 251 , the second interconnection layer 252 and the third interconnection layer 253 includes a deposition process or an epitaxial growth process.

[0116] In this embodiment, the materials of the first interconnection layer 251 , the second interconnection layer 252 and the third interconnection layer 253 include metal materials, such as copper, aluminum or titanium.

[0117] Accordingly, the embodiment of the present invention also provides a semiconductor structure formed by the above-mentioned forming method, please continue to refer to Figures 9 to 12 The semiconductor structure includes: a substrate 200, the substrate 200 includes a first region I, a second region 11 and a third region III arranged along a first direction X, the third region III is located between the first region I and the second region II; a plurality of first grooves 221 located in the first region I, the first grooves 221 extending along the first direction X; a plurality of second grooves 222 located in the second region II, the second grooves 222 extending along the first direction X; a plurality of third grooves 223 located in the third region III, each of the third grooves 223 being connected to one of the first grooves 221 and one of the second grooves 222 respectively; and a cutting layer 230 located in the connected first grooves 221, second grooves 222 and third grooves 223.

[0118] In this embodiment, the substrate 200 further includes a base 210 and a dielectric layer 220 located on the base 210 .

[0119] The material of the substrate 210 includes semiconductor material.

[0120] In this embodiment, the material of the substrate 210 includes silicon. In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of III-V group elements, silicon on insulator (SOI) or germanium on insulator. Among them, the multi-component semiconductor material composed of III-V group elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0121] In this embodiment, the substrate 210 has a device layer (not shown). The device layer may include a device structure, such as a PMOS transistor or an NMOS transistor. The device layer may also include an interconnection structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnection structure.

[0122] In this embodiment, the material of the dielectric layer 220 is titanium oxide.

[0123] In another embodiment, the material of the dielectric layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon carbon oxynitride.

[0124] In this embodiment, the first groove 221 , the second groove 222 , and the third groove 223 are located in the dielectric layer 220 .

[0125] The first groove 221 has a first center line DT1 in the first direction X, and the second groove 222 has a second center line DT2 in the first direction X. The first center line DT1 and the second center line DT2 are arranged along the second direction Y, and there are no more than two second center lines DT2 between every two adjacent first center lines DT1, and the second direction Y is perpendicular to the first direction X.

[0126] Specifically, in this embodiment, there is one second center line DT2 between every two adjacent first center lines DT1.

[0127] In yet another embodiment, two second center lines are spaced between every two adjacent first center lines.

[0128] In this embodiment, a minimum distance T1 between adjacent first grooves 221 and second grooves 222 is less than 50 nanometers.

[0129] If the minimum spacing T1 is too large, the occupied area of ​​the cutting layer 230 will be increased, which is not conducive to improving the integration of the semiconductor structure. Therefore, selecting a suitable minimum spacing T1 can reduce the short-circuit defects of the interconnection layer and improve the integration of the semiconductor structure.

[0130] It should be noted that, in this embodiment, the minimum distance T1 refers to the distance between the center point P1 of the boundary line between the first groove 221 and the third groove 223 and the center point P2 of the boundary line between the second groove 222 and the third groove 223 .

[0131] In this embodiment, the inclination direction and inclination angle of each of the third grooves 223 relative to the second direction Y are the same. Therefore, the third grooves 223 are kept relatively uniformly spaced, so that when the mask pattern is transferred to the dielectric layer 220, the process window size of the exposure process can be increased, and the diffraction effect enhanced by the uneven density can be reduced to reduce the distortion of the photolithography pattern relative to the mask pattern, so as to form the third grooves 223 with good morphology quality, and further, it is beneficial to the filling process of the cutting layer material in the third grooves 223 to form a full and well-shaped cutting layer 230.

[0132] It should be noted that the inclination direction of the third groove 223 relative to the second direction Y means that the connection direction is toward the second direction Y, or the connection direction is away from the second direction Y, and the connection direction is from the connecting end of the third groove 223 and the second groove 222 to the connecting end of the third groove 223 and the first groove 221; the inclination angle of the third groove 223 relative to the second direction Y means that the angle α2 between the center line DT3 of the third groove 223 and the second direction Y is less than or equal to 90 degrees.

[0133] In another embodiment, the inclination directions of the third grooves relative to the second direction are the same, but the inclination angles are different, that is, in the first grooves and the second grooves connected by the third grooves, the first grooves are on the same side of the second groove.

[0134] In another embodiment, the inclination directions of the third grooves relative to the second direction are different, but the inclination angles are the same, that is, in the first groove and the second groove connected by the third groove, the first groove is on different sides of the second groove.

[0135] In other embodiments, the inclination directions of each third groove relative to the second direction are different, that is, in each first groove and second groove connected by the third groove, the first groove is on different sides of the second groove, and the inclination angles of each third groove relative to the second direction are also different.

[0136] In this embodiment, the material of the cutting layer 230 is low temperature filling oxide.

[0137] In another embodiment, the material of the cutting layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon carbon oxynitride.

[0138] In this embodiment, the semiconductor structure further includes: a plurality of first interconnect openings 241 located in the dielectric layer 220 in the first region I, and the first interconnect openings 241 are located on both sides of the first groove 221 .

[0139] In this embodiment, the semiconductor structure further includes: a first interconnect layer 251 located in the first interconnect opening 241 .

[0140] In yet another embodiment, the semiconductor structure does not include the first interconnect opening and the first interconnect layer.

[0141] In this embodiment, the semiconductor structure further includes: a plurality of second interconnect openings 242 located in the dielectric layer 220 in the second region II, and the second interconnect openings 242 are located on both sides of the second groove 222 .

[0142] In this embodiment, the semiconductor structure further includes: a second interconnect layer 252 located in the second interconnect opening 242 .

[0143] In yet another embodiment, the semiconductor structure does not include the second interconnect opening and the second interconnect layer.

[0144] In this embodiment, the semiconductor structure further includes: a third interconnect opening 253 located in the dielectric layer 220 in the third region III, and the third interconnect opening 253 penetrates the cutting layer 230 along the second direction Y.

[0145] In this embodiment, the semiconductor structure further includes: a third interconnect layer 253 located in the third interconnect opening 243 .

[0146] In other embodiments, the semiconductor structure does not include the third interconnect opening and the third interconnect layer.

[0147] In this embodiment, the materials of the first interconnection layer 251 , the second interconnection layer 252 and the third interconnection layer 253 include metal materials, such as copper, aluminum or titanium.

[0148] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising a first region, a second region and a third region arranged along a first direction, the third region being located between the first region and the second region; a plurality of first grooves located in the first area, the first grooves extending along the first direction; A plurality of second grooves located in the second area, the second grooves extending along the first direction; a plurality of third grooves located in the third area, each of the third grooves being connected to one of the first grooves and one of the second grooves respectively; A cutting layer located in the first, second and third grooves connected to each other; a first interconnection opening located in the first region, wherein the cutting layer in the first groove penetrates the first interconnection opening along the first direction; The second interconnection opening is located in the second area, and the cutting layer in the second groove penetrates the second interconnection opening along the first direction.

2. The semiconductor structure according to claim 1, wherein: The first groove has a first center line in the first direction, the second groove has a second center line in the first direction, the first center line and the second center line are arranged along the second direction, and there are no more than two second center lines between every two adjacent first center lines, and the second direction is perpendicular to the first direction.

3. The semiconductor structure according to claim 1, wherein: The minimum distance between adjacent first grooves and second grooves is less than 50 nanometers.

4. The semiconductor structure according to claim 1, wherein: The substrate further includes a base and a dielectric layer located on the base, and the first groove, the second groove and the third groove are located in the dielectric layer.

5. The semiconductor structure according to claim 4, characterized in that The material of the dielectric layer is different from that of the cutting layer.

6. The semiconductor structure according to claim 5, characterized in that The material of the dielectric layer includes titanium oxide.

7. The semiconductor structure according to claim 5, characterized in that The material of the cutting layer includes a low temperature filling oxide.

8. The semiconductor structure according to claim 4, wherein: Also includes: A plurality of first interconnect openings are located in the dielectric layer in the first region, and the first interconnect openings are located on both sides of the first groove.

9. The semiconductor structure according to claim 8, characterized in that Also includes: A first interconnect layer is located within the first interconnect opening.

10. The semiconductor structure according to claim 4, wherein: Also includes: A plurality of second interconnect openings are located in the dielectric layer of the second region, and the second interconnect openings are located on both sides of the second groove.

11. The semiconductor structure according to claim 10, characterized in that Also includes: A second interconnect layer is located within the second interconnect opening.

12. The semiconductor structure according to claim 4, wherein: Also includes: A third interconnect opening is located in the dielectric layer in the third region, and the third interconnect opening penetrates the cutting layer along the second direction.

13. The semiconductor structure according to claim 12, wherein: Also includes: A third interconnect layer is located within the third interconnect opening.

14. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first region, a second region and a third region arranged along a first direction, the third region being located between the first region and the second region; forming a plurality of first grooves in the first area, wherein the first grooves extend along the first direction; A plurality of second grooves are formed in the second area, and the second grooves extend along the first direction; a plurality of third grooves are formed in the third area, and each of the third grooves is connected to one of the first grooves and one of the second grooves respectively; forming a cutting layer in the connected first groove, the second groove, and the third groove; After the cutting layer is formed, a first interconnect opening in the first area and a second interconnect opening in the second area are formed, the cutting layer in the first groove penetrates the first interconnect opening along the first direction, and the cutting layer in the second groove penetrates the second interconnect opening along the first direction.

15. The method for forming a semiconductor structure according to claim 14, wherein: The first groove has a first center line in the first direction, the second groove has a second center line in the first direction, the first center line and the second center line are arranged along the second direction, and there are no more than two second center lines between every two adjacent first center lines, and the second direction is perpendicular to the first direction.

16. The method for forming a semiconductor structure according to claim 14, wherein: The substrate further includes a base and a dielectric layer located on the base, and the first groove, the second groove and the third groove are located in the dielectric layer.

17. The method for forming a semiconductor structure according to claim 16, wherein: Also includes: After the cutting layer is formed, a plurality of first interconnection openings located on both sides of the first groove are formed in the dielectric layer of the first region.

18. The method for forming a semiconductor structure according to claim 17, wherein: The method for forming the first interconnect opening comprises: forming a first interconnect patterned layer on the surface of the cutting layer, the first interconnect patterned layer having a plurality of first patterned openings of the cutting layer spanning the first region, the first patterned openings exposing the dielectric layer and the cutting layer surface; using the first interconnect patterned layer as a mask, etching the dielectric layer until the substrate surface is exposed.

19. The method for forming a semiconductor structure according to claim 17, wherein: Also includes: A first interconnect layer is formed in the first interconnect opening.

20. The method for forming a semiconductor structure according to claim 16, wherein: Also includes: After the cutting layer is formed, a plurality of second interconnection openings located at both sides of the second groove are formed in the dielectric layer of the second region.

21. The method for forming a semiconductor structure according to claim 20, wherein: The method for forming the second interconnect opening comprises: forming a second interconnect patterned layer on the surface of the cutting layer, the second interconnect patterned layer having a plurality of second patterned openings of the cutting layer spanning the second region, the second patterned openings exposing the dielectric layer and the cutting layer surface; using the second interconnect patterned layer as a mask, etching the dielectric layer until the substrate surface is exposed.

22. The method for forming a semiconductor structure according to claim 20, wherein: Also includes: A second interconnect layer is formed in the second interconnect opening.

23. The method for forming a semiconductor structure according to claim 16, wherein: Also includes: After the cutting layer is formed, a third interconnect opening is formed in the dielectric layer in the third region, and the third interconnect opening penetrates the cutting layer along the second direction.

24. The method for forming a semiconductor structure according to claim 23, wherein: The method for forming the third interconnect opening comprises: forming a third interconnect patterned layer on the surface of the cutting layer, the third interconnect patterned layer having a third patterned opening of the cutting layer spanning the third region, the third patterned opening exposing the dielectric layer and the cutting layer surface; using the third interconnect patterned layer as a mask, respectively etching the dielectric layer and the cutting layer until the substrate surface is exposed.

25. The method for forming a semiconductor structure according to claim 23, wherein: Also includes: A third interconnect layer is formed in the third interconnect opening.

26. The method for forming a semiconductor structure according to claim 16, wherein: The method for forming the first groove, the second groove and the third groove includes: forming a cutting patterned layer on the surface of the dielectric layer, the cutting patterned layer exposing a portion of the first area, a portion of the second area and a portion of the third area surface; using the cutting patterned layer as a mask, etching the dielectric layer until the substrate surface is exposed.

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