Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate, an etch stop material layer located on the substrate, a first anti-etching material layer located on the etch stop material layer, and a doping layer located on the first anti-etching material layer; using the doping layer as a mask, etching the first anti-etching material layer to form the first anti-etching layer; using the first anti-etching layer as a mask, etching the etch stop material layer to form an etch stop structure. In the process of forming the first anti-etching layer, the embodiment of the present invention uses the top of the etch stop material layer as the etch stop position, so that the bottom convex corners in the doping layer are not easily transferred to the first anti-etching layer, so that the formation quality of the first anti-etching layer is better; similarly, in the process of forming the etch stop structure, the top of the substrate is used as the etch stop position, which further reduces the influence of the bottom convex corner phenomenon on the etch stop structure, and finally the formation quality of the etch stop structure is better.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] As semiconductor manufacturing technology becomes more and more sophisticated, integrated circuits are also undergoing major changes. The number of components integrated on the same chip has increased from dozens or hundreds of components to millions of components today. In order to meet the requirements of circuit density, the manufacturing process of semiconductor integrated circuit chips uses batch processing technology to form various types of complex devices on the substrate and interconnect them to have complete electronic functions. Currently, most of them use ultra-low-k interlayer dielectric layers between wires as dielectric materials to isolate each metal interconnection, and the interconnection structure is used to provide wiring between the devices on the IC chip and the entire package. In this technology, devices such as field effect transistors (FETs) are first formed on the surface of the semiconductor substrate, and then the interconnection structure is formed in the back end of line (BEOL) process of integrated circuit manufacturing.

[0003] As predicted by Moore's Law, the size of semiconductor substrates continues to shrink, and more transistors are formed on the semiconductor substrate to improve the performance of the device. It is inevitable to use interconnect structures to connect transistors. However, compared with the miniaturization and integration of components, the number of conductor connections in the circuit continues to increase. The quality of the formation of the interconnect structure has a great impact on the performance of the back-end (BEOL) circuit, and in severe cases, it will affect the normal operation of semiconductor devices. Summary of the invention

[0004] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure to improve the electrical performance of the semiconductor structure.

[0005] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, an etch stop material layer located on the substrate, a first anti-etching material layer located on the etch stop material layer, and a graphic definition layer located on the first anti-etching material layer; doping ions into a plurality of spaced-apart regions of the graphic definition layer, wherein the graphic definition layer doped with ions serves as a doping layer, and the etching resistance of the doping layer is greater than that of the graphic definition layer; after forming the doping layer, removing the graphic definition layer; after removing the graphic definition layer, taking the top of the etch stop material layer as an etching stop position and the doping layer as a mask, etching the first anti-etching material layer to form a first anti-etching layer; taking the top of the substrate as an etching stop position and the first anti-etching layer as a mask, etching the etch stop material layer to form an etching stop structure.

[0006] Optionally, the etch stop material layer includes a plurality of stacked etch stop sub-film layers, and an etch selectivity ratio exists between adjacent etch stop sub-film layers.

[0007] Optionally, the plurality of etch stop sub-film layers constitute one or more stacked material layers, and the stacked material layers include a second etch-resistant material layer and a third etch-resistant material layer located on the second etch-resistant material layer.

[0008] Optionally, the etch stop material layer is etched using an anisotropic dry etching process to form the etch stop structure.

[0009] Optionally, the step of etching the etch stop material layer using an anisotropic dry etching process includes: performing one or more etching treatments, the etching treatment being used to etch one of the stacked material layers, the etching treatment including: taking the top of the second anti-etching material layer as the etching stop position, performing a first etching treatment on the third anti-etching material layer to form a third anti-etching layer; after the first etching treatment, taking the top of the third anti-etching material layer or the top of the substrate as the etching stop position, performing a second etching treatment on the second anti-etching material layer to form a second anti-etching layer.

[0010] Optionally, the process parameters of the first etching treatment include: the etching gas includes one or more of SiF4, NF3, CHF3 and C2F6, the etching gas flow rate is less than 1000sccm, and the chamber pressure is less than 50mTorr; the process parameters of the second etching treatment include: the etching gas includes one or more of CF4, C3F8, C4F8, CHF3 and NF3, the etching gas flow rate is less than 1000sccm, and the chamber pressure is less than 50mTorr.

[0011] Optionally, the material of the second anti-etching material layer includes: Si, Ge, SiO or SiN; the material of the third anti-etching material layer includes: Si, Ge, SiO or SiN.

[0012] Optionally, the step of forming the doping layer includes: forming a discrete first mask layer on the graphic definition layer; using the first mask layer as a mask, injecting ions into the graphic definition layer exposed by the first mask layer to form the doping layer; the method for forming the semiconductor structure includes: after forming the doping layer, removing the first mask layer.

[0013] Optionally, the step of removing the first mask layer includes: forming a sacrificial material layer on the first mask layer and the doping layer between the first mask layer, the sacrificial material layer and the first mask layer having the same material, and the top surface of the sacrificial material layer being higher than or flush with the top surface of the first mask layer; and removing the sacrificial material layer and the first mask layer using a maskless dry etching process.

[0014] Optionally, the method for forming the semiconductor structure also includes: after forming the first mask layer, before injecting ions into the graphic definition layer between the first mask layers, forming a first sidewall layer on the side wall of the first mask layer, the etching resistance of the first sidewall layer being greater than the etching resistance of the first mask layer; in the step of injecting ions into the graphic definition layer between the first mask layers, doping ions into the graphic definition layer exposed by the first mask layer and the first sidewall layer.

[0015] Optionally, the process parameters for doping ions in multiple spaced-apart regions of the graphic definition layer include: the injected ions include one or more of B, P, C and N, the ion implantation energy is less than 30 KeV, and the angle between the ion implantation angle and the normal to the substrate surface is less than 30 degrees.

[0016] Optionally, after forming the doping layer and before removing the graphic definition layer, it also includes: forming a second mask layer on the doping layer and the graphic definition layer; using the top of the first anti-etching material layer as an etching stop position, and etching the doping layer using the second mask layer as a mask; the method for forming the semiconductor structure also includes: after etching the doping layer using the second mask layer as a mask, removing the second mask layer.

[0017] Optionally, after etching the doped layer with the second mask layer as a mask and before removing the graphic definition layer, it also includes: forming a second sidewall layer on the exposed sidewalls of the graphic definition layer and the sidewalls of the doped layer, the etching resistance of the second sidewall layer is greater than that of the graphic definition layer; in the step of etching the first anti-etching material layer with the doped layer as a mask, etching the first anti-etching material layer with the doped layer and the second sidewall layer as masks.

[0018] Optionally, the pattern definition layer is removed by a wet etching process.

[0019] Optionally, the method for forming the semiconductor structure also includes: etching the substrate using the etch stop structure as a mask to form a target pattern; or, the method for forming the semiconductor structure also includes: forming a third side wall on the side wall of the etch stop structure; after forming the third side wall, removing the etch stop structure; after removing the etch stop structure, etching the substrate using the third side wall as a mask to form a target pattern.

[0020] Optionally, the substrate includes a dielectric layer; and the step of etching the substrate to form a target pattern includes: etching the dielectric layer to form an interconnect opening, and the interconnect opening serves as the target pattern.

[0021] Accordingly, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate; an etch stop material layer, located on the substrate; a first anti-etching material layer, located on the etch stop material layer; a graphic definition layer, located on the first anti-etching material layer; a plurality of spaced-apart doping layers, penetrating the graphic definition layer, the doping layers being obtained by doping ions into a plurality of spaced-apart regions of the graphic definition layer, the etching resistance of the doping layers being greater than the etching resistance of the graphic definition layer.

[0022] Optionally, the etch stop material layer includes a plurality of stacked etch stop sub-film layers, and an etch selectivity ratio exists between adjacent etch stop sub-film layers.

[0023] Optionally, the plurality of etch stop sub-film layers constitute one or more stacked material layers, and the stacked material layers include a second etch-resistant material layer and a third etch-resistant material layer located on the second etch-resistant material layer.

[0024] Optionally, the material of the second anti-etching material layer includes: Si, Ge, SiO or SiN; the material of the third anti-etching material layer includes: Si, Ge, SiO or SiN.

[0025] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0026] In the method for forming the semiconductor structure provided by the embodiment of the present invention, the doping layer is formed by doping ions. Due to the angle of ion implantation, the doping layer formed is likely to have a bottom convex angle. Considering the problem of the bottom convex angle, the embodiment of the present invention forms an etching stop material layer between the substrate and the first anti-etching material layer. Therefore, in the process of forming the first anti-etching layer, the top of the etching stop material layer is used as the etching stop position, so that the bottom convex angle in the doping layer is not easily transferred to the first anti-etching layer, and the problem of excessive or insufficient etching caused by inconsistent etching rates in various regions can be avoided, so that the formation quality of the first anti-etching layer is better; similarly, in the process of forming the etching stop structure, the top of the substrate is used as the etching stop position, which further reduces the influence of the bottom convex angle phenomenon on the etching stop structure, and can also avoid the problem of excessive or insufficient etching caused by inconsistent etching rates in various regions, and finally the formation quality of the etching stop structure is better. In summary, the interconnect openings formed by etching the substrate using the etch stop structure as a mask have good formation quality. The interconnect openings serve as target patterns, and the interconnect structures subsequently formed in the interconnect openings are less likely to have bridging or short circuits, which is beneficial to improving the electrical performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figures 1 to 5 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0028] Figures 6 to 8 It is a schematic structural diagram corresponding to each step in another method for forming a semiconductor structure;

[0029] Figures 9 to 21 Schematic diagram of the structure corresponding to each step in the first embodiment of the method for forming a semiconductor structure of the present invention DETAILED DESCRIPTION

[0030] The devices currently formed still have the problem of poor performance. The reasons for the poor performance of the devices are now analyzed in combination with a method for forming a semiconductor structure.

[0031] refer to Figures 1 to 5 , showing a structural schematic diagram corresponding to each step in a method for forming a semiconductor structure.

[0032] like Figure 1 As shown, a substrate 1 , an anti-etching material layer 2 located on the substrate 1 , and a pattern definition layer 3 located on the anti-etching material layer 2 are provided; and a mask layer 4 is formed on the pattern definition layer 3 .

[0033] like Figure 2As shown, the mask layer 4 is used as an implantation mask, and ions are doped into the pattern definition layer 3 between the mask layers 4 to form a doping layer 5 , wherein the etching resistance of the doping layer 5 is greater than that of the pattern definition layer 3 .

[0034] like Figure 3 As shown, after the doping layer 5 is formed, the mask layer 4 is removed; after the mask layer 4 is removed, the pattern definition layer 3 is removed.

[0035] like Figure 4 As shown, the anti-etching material layer 2 is etched using the doping layer 5 as a mask to form an anti-etching layer 9.

[0036] like Figure 5 As shown, the base 1 is etched using the doping layer 5 and the anti-etching layer 9 as masks to form a substrate 6 and target patterns 7 on the substrate 6 ; and an interconnection structure 8 is formed on the substrate 6 between the target patterns 7 .

[0037] The doping layer 5 is formed by an ion implantation process. Due to the ion implantation angle, the pattern definition layer 3 at the bottom of the mask layer 4 is easily doped with ions, resulting in the doping layer 5 having a bottom convex angle, and also easily causing the doping layers 5 on both sides of the thinner mask layer 4 to be connected together (such as Figure 2 In the process of forming the anti-etching layer 9, the etching rate of the anti-etching material layer 2 is greater than the etching rate of the doping layer 5, and the doping layer 5 in the connection area B acts as a mask. Accordingly, after the anti-etching layer 9 is formed, the etching amount of the anti-etching material layer 2 at the bottom of the connection area B is small, resulting in the existence of a connecting area C between the formed anti-etching layers 9 (as shown in FIG. Figure 4 As shown). In the process of forming the target pattern 7, the etching rate of the substrate 1 is greater than the etching rate of the anti-etching layer 9, and the connected area C acts as a mask, which may cause the substrate 1 at the bottom of the area C to not be etched. In the process of forming the interconnection structure 8, the area A in the substrate 1 does not form the interconnection structure 8, and there is a short circuit in the interconnection structure 8, resulting in poor electrical performance of the semiconductor structure.

[0038] refer to Figures 6 to 8 , shows a schematic diagram of the structure corresponding to each step in another method for forming a semiconductor structure. The similarities between this method and the previous method are not repeated here. The difference between this method and the previous method is that:

[0039] The doping layer 50 is formed by an ion implantation process. During the doping process, the energy of the doping ions gradually decays, resulting in a doping dose of the doping ions at the top of the pattern definition layer (not shown in the figure) being higher than that of the doping ions at the bottom of the pattern definition layer. Therefore, in the process of etching and removing the pattern definition layer, the etching resistance at the bottom of the doping layer 50 is less than that at the top of the doping layer 50. In order to prevent the doping layer 50 from having a bottom convex corner, the process time for etching the pattern definition layer 30 is usually increased, which results in the bottom size of the doping layer 50 being smaller than the top size of the doping layer 50 after the pattern definition layer is removed. Subsequently, the anti-etching material layer 20 is etched using the doping layer 50 as a mask, and the bottom size of the formed anti-etching layer 90 is smaller than the top size of the anti-etching layer 90. In the process of etching the base 10 using the anti-etching layer 90 and the doping layer 50 as masks to form the substrate 60 and the target pattern 70 located on the substrate 60, the bottom size of the target pattern 70 formed will be smaller than the top size of the target pattern 70. Accordingly, the bottoms of the interconnection structures 80 formed between the target patterns 70 are too close to each other, which may easily lead to bridging, resulting in poor electrical performance of the semiconductor structure.

[0040] In order to solve the technical problem, a substrate, an etch stop material layer located on the substrate, a first anti-etching material layer located on the etch stop material layer, and a graphic definition layer located on the first anti-etching material layer are provided; ions are doped into a plurality of spaced-apart regions of the graphic definition layer, the graphic definition layer doped with ions serves as a doping layer, and the etching resistance of the doping layer is greater than that of the graphic definition layer; after forming the doping layer, the graphic definition layer is removed; after removing the graphic definition layer, the first anti-etching material layer is etched with the top of the etch stop material layer as an etching stop position and the doping layer as a mask to form a first anti-etching layer; the etch stop material layer is etched with the top of the substrate as an etching stop position and the first anti-etching layer as a mask to form an etching stop structure.

[0041] In the method for forming the semiconductor structure provided by the embodiment of the present invention, the doping layer is formed by doping ions. Due to the angle of ion implantation, the doping layer formed is likely to have a bottom convex angle. Considering the problem of the bottom convex angle, the embodiment of the present invention forms an etching stop material layer between the substrate and the first anti-etching material layer. Therefore, in the process of forming the first anti-etching layer, the top of the etching stop material layer is used as the etching stop position, so that the bottom convex angle in the doping layer is not easily transferred to the first anti-etching layer, and the problem of excessive or insufficient etching caused by inconsistent etching rates in various regions can be avoided, so that the formation quality of the first anti-etching layer is better; similarly, in the process of forming the etching stop structure, the top of the substrate is used as the etching stop position, which further reduces the influence of the bottom convex angle phenomenon on the etching stop structure, and can also avoid the problem of excessive or insufficient etching caused by inconsistent etching rates in various regions, and finally the formation quality of the etching stop structure is better. In summary, the interconnect openings formed by etching the substrate using the etch stop structure as a mask have good formation quality. The interconnect openings serve as target patterns, and the interconnect structures subsequently formed in the interconnect openings are less likely to have bridging or short circuits, which is beneficial to improving the electrical performance of the semiconductor structure.

[0042] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0043] Figures 9 to 21 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0044] refer to Fig. 9 , providing a substrate 100, an etch stop material layer (not shown in the figure) located on the substrate 100, a first anti-etching material layer 102 located on the etch stop material layer, and a graphic definition layer 103 located on the first anti-etching material layer 102.

[0045] The substrate 100 is prepared for subsequent etching to form a target pattern.

[0046] In this embodiment, the substrate 100 includes a dielectric layer. Specifically, the dielectric layer is made of a low-k dielectric material, which is beneficial to reducing the parasitic capacitance between the conductive layers, thereby reducing the RC delay of the subsequent stage.

[0047] In this embodiment, the material of the dielectric layer includes SiCOH.

[0048] The etch stop material layer is prepared for the subsequent formation of an etch stop structure.

[0049] The etch stop material layer includes a plurality of stacked etch stop sub-film layers, and an etch selectivity ratio exists between adjacent etch stop sub-film layers.

[0050] In the subsequent etching process of the etch stop material layer, the multiple etch stop sub-film layers are etched, and there is an etching selectivity ratio between adjacent etch stop sub-film layers, which can avoid the problem of over-etching or under-etching caused by inconsistent etching rates in different regions, and is beneficial to improving the formation quality of the etch stop structure.

[0051] Specifically, the plurality of etch stop sub-film layers constitute one or more stacked material layers 101, and the stacked material layer 101 includes a second anti-etching material layer 1011 and a third anti-etching material layer 1012 ( Fig. 9 Only one stacked material layer 101 is shown in the figure. The stacked material layer 101 includes a second anti-etching material layer 1011 and a third anti-etching material layer 1012, that is, the etch stop material layer includes two etch stop sub-film layers, and the stacked material layer 101 does not need to be formed through too many process flows, which is conducive to improving the process compatibility of forming the etch stop material layer. In other embodiments, the number of etch stop sub-film layers in the one stacked material layer can also be three, four or five.

[0052] Specifically, the material of the second anti-etching material layer 1011 includes Si, Ge, SiO or SiN. In this embodiment, the material of the second anti-etching material layer 1011 includes SiO.

[0053] Specifically, the material of the third anti-etching material layer 1012 includes: Si, Ge, SiO or SiN. In this embodiment, the material of the third anti-etching material layer 1012 includes Si.

[0054] The first anti-etching material layer 102 is prepared for the subsequent formation of a first anti-etching layer.

[0055] Specifically, the material of the first anti-etching material layer 102 includes SiON, SiBCN, SiCN, and SiN. In this embodiment, the material of the first anti-etching material layer 102 includes SiON.

[0056] The pattern definition layer 103 is used to provide a process platform for the subsequent formation of a doping layer.

[0057] In this embodiment, the material of the pattern definition layer 103 is amorphous silicon. Amorphous silicon is a commonly used material in the process, and the formation process is simple, which is conducive to reducing the process cost of the semiconductor structure. In other embodiments, the material of the pattern definition layer can also be silicon oxide.

[0058] refer to Figures 10 to 13 , ions are doped into a plurality of spaced-apart regions of the pattern definition layer 103 , and the pattern definition layer 103 doped with ions serves as a doping layer 104 , and the etching resistance of the doping layer 104 is greater than that of the pattern definition layer 103 .

[0059] The doping layer 104 is used as an etching mask for subsequent etching of the first anti-etching material layer 102 .

[0060] The step of forming the doping layer 104 includes: forming a separate first mask layer 105 (such as Fig.11 ions are injected into the pattern definition layer 103 exposed by the first mask layer 105 to form the doping layer 104; using the first mask layer 105 as a mask;

[0061] like Fig.10 and Fig.11 As shown, the steps of forming the first mask layer 105 include: forming a first organic material layer 106 on the graphic definition layer 103, a first bottom anti-reflection layer 107 located on the first organic material layer 106, and a first photoresist layer 108 located on the first bottom anti-reflection layer 107, wherein the first photoresist layer 108 has a first opening 109; etching the first bottom anti-reflection layer 107 and the first organic material layer 106 exposed by the first opening 109, and the remaining first organic material layer 106 serves as the first mask layer 105.

[0062] In this embodiment, the first photoresist layer 108 and the first bottom anti-reflection layer 107 are both consumed in the step of forming the first mask layer 105. In other embodiments, the first bottom anti-reflection layer may still exist after the first mask layer is formed.

[0063] like Fig.12 As shown, ions are doped into the pattern definition layer 103 exposed by the first mask layer 105 by ion implantation to form a doping layer 104. The ion implantation process has the characteristics of simple operation and low process cost.

[0064] The process parameters for implanting ions in the pattern definition layer 103 exposed by the first mask layer 105 include: the implanted ions include one or more of B, P, C and N.

[0065] It should be noted that the injection energy of the doping ions should not be too large. If the injection energy of the doping ions is too large, it is easy for the doping ions to pass through the pattern definition layer 103 and enter the first anti-etching material layer 102, which is not conducive to increasing the etching selectivity ratio of the doping layer 104 to the pattern definition layer 103. When the first anti-etching material layer 102 is subsequently etched using the doping layer 104 as a mask, the doping layer 104 is easily consumed prematurely, and the doping layer 104 is not easy to play a good role as a mask, resulting in poor formation quality of the first anti-etching layer, and poor formation quality of the target pattern subsequently obtained based on the first anti-etching layer pattern transfer. In this embodiment, the injection energy of the doping ions is less than 30Kev.

[0066] The angle between the ion implantation direction and the surface normal of the substrate 100 should not be too large. Subsequently, the first anti-etching material layer 102 is etched using the doping layer 104 as a mask to form a first anti-etching layer. If the angle between the ion implantation direction and the surface normal of the substrate 100 is too large, due to the shadow effect, ions are not easily implanted into the pattern definition layer 103, so that the etching selectivity of the pattern definition layer 103 and the doping layer 104 is relatively small. In the process of etching the first anti-etching material layer 102 using the doping layer 104 as a mask, the doping layer 104 is not easy to play a good role as a mask, resulting in poor formation quality of the first anti-etching layer, and poor formation quality of the target pattern subsequently obtained by transferring the first anti-etching layer pattern. In this embodiment, the angle between the ion implantation direction and the surface normal of the substrate 100 is less than 30 degrees.

[0067] The method for forming the semiconductor structure also includes: after forming the first mask layer 105, before injecting ions into the graphic definition layer 103 between the first mask layers 105, forming a first sidewall layer 110 on the sidewall of the first mask layer 105, and the etching resistance of the first sidewall layer 110 is greater than the etching resistance of the first mask layer 105.

[0068] During the subsequent process of doping ions into the graphic definition layer 103 between the first mask layer 105, the first side wall layer 110 can prevent the doped ions from entering the first mask layer 105, thereby making it easy to remove the first mask layer 105. In addition, with the extension direction perpendicular to the first mask layer 105 as the lateral direction, the first side wall layer 110 reduces the exposed area of ​​the graphic definition layer 103, thereby making the lateral width of the doped layer 104 smaller.

[0069] Correspondingly, in the step of injecting ions into the pattern definition layer 103 between the first mask layers 105 , the pattern definition layer 103 exposed by the first mask layer 105 and the first spacer layer 110 is doped with ions.

[0070] The material of the first spacer layer 110 includes: TiN, TiO or SiN. In this embodiment, the material of the first spacer layer 110 is SiN.

[0071] The steps of forming the first sidewall layer 110 include: forming a first sidewall material layer (not shown in the figure) on the first mask layer 105 and the graphic definition layer 103 exposed by the first mask layer 105; removing the top surface of the first mask layer 105 and the first sidewall material layer on the surface of the graphic definition layer 103, and the remaining first sidewall material layer located on the side wall of the first mask layer 105 serves as the first sidewall layer 110.

[0072] like Fig.13 As shown, the method for forming the semiconductor structure further includes: after forming the doping layer 104 , removing the first mask layer 105 .

[0073] The step of removing the first mask layer 105 includes: forming a sacrificial material layer (not shown in the figure) on the first mask layer 105 and the doping layer 104 between the first mask layer 105, the sacrificial material layer and the first mask layer 105 are made of the same material, and the top surface of the sacrificial material layer is higher than or flush with the top surface of the first mask layer; and removing the sacrificial material layer and the first mask layer 105 using a maskless dry etching process.

[0074] The sacrificial material layer can make the doping layer 104 not easily exposed, and the doping layer 104 is not easily damaged during the removal of the first mask layer 105. Because the sacrificial material layer and the first mask layer 105 are made of the same material, and the sacrificial material layer is made of a different material from the graphic definition layer 103, in the process of etching the sacrificial material layer and the first mask layer 105 using a maskless etching process, the top of the graphic definition layer 103 and the doping layer 104 can be used as the etching stop position, thereby avoiding the problem of over-etching or under-etching caused by inconsistent etching rates in different regions.

[0075] In other embodiments, because the first mask layer is formed by etching the first organic material layer, the material of the first mask layer is also an organic material, and after the sacrificial material layer is formed, the first mask layer and the sacrificial material layer can be removed by an ashing process.

[0076] It should be noted that, in the process of removing the first mask layer 105 and the sacrificial material layer, the first spacer layer 110 is also removed.

[0077] refer to Fig.14 and Fig.15The method for forming the semiconductor structure also includes: after forming the doping layer 104 and before removing the graphic definition layer 103, forming a second mask layer (not shown in the figure) on the doping layer 104 and the graphic definition layer 103; using the top of the first anti-etching material layer 102 as the etching stop position and etching the doping layer 104 using the second mask layer as a mask.

[0078] Etching the doped layer 104 using the second mask layer as a mask can remove the doped layer 104 in a partial area, or reduce the lateral width of the doped layer 104 in a partial area, so that the remaining doped layer 104 can meet the process requirements.

[0079] The steps of forming the second mask layer include: forming a second organic material layer 112 on the graphic definition layer 103 and the doping layer 104, a second bottom anti-reflection layer 113 located on the second organic material layer 112, and a second photoresist layer 114 located on the second bottom anti-reflection layer 113, wherein the second photoresist layer 114 has a second opening 115; etching the second bottom anti-reflection layer 113 and the second organic material layer 112 exposed by the second opening 115, and the remaining second organic material layer 112 serves as the second mask layer.

[0080] In this embodiment, in the step of forming the second mask layer, the second photoresist layer 114 and the second bottom anti-reflection layer 113 are both consumed. In other embodiments, after the second mask layer is formed, the second bottom anti-reflection layer may still exist.

[0081] In this embodiment, the second mask layer is used as a mask and a dry etching process is used to etch the doped layer 104. The dry etching process has anisotropic etching characteristics and good etching profile controllability, and the top of the first anti-etching material layer 102 can be used as the etching stop position during the dry etching process.

[0082] The method for forming the semiconductor structure further includes: after etching the doping layer 104 using the second mask layer as a mask, removing the second mask layer.

[0083] The step of removing the second mask layer refers to the previous step of removing the first mask layer 105 , which will not be described in detail here.

[0084] refer to Fig.16 and Fig.17 After forming the doping layer 104, the pattern definition layer 103 is removed.

[0085] Removing the pattern definition layer 103 is a preparation for subsequently etching the first anti-etching material layer 102 using the doping layer 104 as a mask.

[0086] In this embodiment, a wet etching process is used to remove the pattern definition layer 103. The wet etching process has a high etching rate, simple operation and low process cost.

[0087] The method for forming the semiconductor structure also includes: after etching the doping layer 104 using the second mask layer as a mask, before removing the graphic definition layer 103, it also includes: forming a second sidewall layer 111 on the exposed sidewalls of the graphic definition layer 103 and the sidewalls of the doping layer 104, and the etching resistance of the second sidewall layer 111 is greater than the etching resistance of the graphic definition layer 103.

[0088] In the step of removing the graphic definition layer 103, the second side wall layer 111 and the doping layer 104 are retained, and the second side wall layer 111 and the doping layer 104 serve as etching masks for the subsequent etching of the first anti-etching material layer 102. By forming the second side wall layer 111, the mask formed by the second side wall layer 111 and the doping layer 104 meets the process requirements, so that the first anti-etching layer that meets the process requirements can be formed subsequently.

[0089] The material of the second spacer layer 111 includes: TiN, TiO or SiN. In this embodiment, the material of the second spacer layer 111 is SiN.

[0090] The steps of forming the second sidewall layer 111 include: forming a second sidewall material layer (not shown in the figure) on the graphic definition layer 103 and the doping layer 104, and on the first anti-etching material layer 102 exposed by the graphic definition layer 103 and the doping layer 104; removing the second sidewall material layer on the top surface of the graphic definition layer 103 and the doping layer 104, and the surface of the first anti-etching material layer 102, and the remaining second sidewall material layer located on the exposed sidewalls of the graphic definition layer 103 and the sidewalls of the doping layer 104 serves as the second sidewall layer 111.

[0091] refer to Fig.18 After removing the pattern definition layer 103 , the first anti-etching material layer 102 is etched with the top of the etch stop material layer as the etch stop position and the doping layer 104 as a mask to form a first anti-etching layer 116 .

[0092] The first anti-etching layer 116 serves as an etching mask for subsequently etching the etch stop material layer.

[0093] In this embodiment, the first anti-etching material layer 102 is etched by an anisotropic dry etching process using the doping layer 104 as a mask to form a first anti-etching layer 116. The dry etching process has an anisotropic etching characteristic and good etching profile controllability, so that the first anti-etching layer 116 is not prone to have a bottom convex corner, which is conducive to making the morphology of the first anti-etching layer 116 meet the process requirements; and in the process of etching the first anti-etching material layer 102 by the dry etching process, the top of the etching stop material layer can be used as the etching stop position.

[0094] It should be noted that, in the step of etching the first anti-etching material layer 102 using the doping layer 104 as a mask, the first anti-etching material layer 102 is etched using the doping layer 104 and the second spacer layer 111 as masks to form the first anti-etching layer 116 .

[0095] refer to Fig.19 and Fig. 20 , taking the top of the substrate 100 as an etching stop position, and taking the first anti-etching layer 116 as a mask to etch the etching stop material layer, to form an etching stop structure 117 .

[0096] The doping layer 104 is formed by doping ions. Due to the ion implantation angle, the doping layer 104 may have a bottom convex angle. Considering the bottom convex angle, the embodiment of the present invention forms an etch stop material layer between the substrate and the first anti-etching material layer 102. Therefore, in the process of forming the first anti-etching layer 116, the top of the etch stop material layer is used as the etching stop position, so that the bottom convex angle in the doping layer 104 is not easily transferred to the first anti-etching layer 116, and the problem of excessive or insufficient etching caused by the inconsistent etching rate of each region can be avoided, so that the formation quality of the first anti-etching layer 116 is better; similarly, in the process of forming the etching stop structure 117, the top of the substrate is used as the etching stop position, which further reduces the influence of the bottom convex angle phenomenon on the etching stop structure 117, and the problem of excessive or insufficient etching caused by the inconsistent etching rate of each region can be avoided, and finally the formation quality of the etching stop structure 117 is better. In summary, the interconnect openings formed by etching the substrate 100 using the etch stop structure 117 as a mask have good formation quality. The interconnect openings serve as target patterns, and the interconnect structures subsequently formed in the interconnect openings are less likely to have bridging or short circuits, which is beneficial to improving the electrical performance of the semiconductor structure.

[0097] In this embodiment, an anisotropic dry etching process is used to etch the etch stop material layer to form the etch stop structure 117. The anisotropic dry etching process has good etching profile controllability, which is conducive to making the etch stop structure 117 less likely to have a bottom convex corner, so that the morphology of the etch stop structure 117 meets the process requirements, and in the process of etching the etch stop material layer using the anisotropic dry etching process, the top of the substrate 100 can be used as the etching stop position; in addition, by replacing the etching gas, the second anti-etching material layer 1171 and the third anti-etching material layer 1172 can be etched in the same etching equipment, which simplifies the process steps.

[0098] Specifically, the step of etching the etch stop material layer using an anisotropic dry etching process includes: performing one or more etching treatments, the etching treatment being used to etch one of the stacked material layers 101, the etching treatment including: taking the top of the second anti-etching material layer 1011 as the etching stop position, performing a first etching treatment on the third anti-etching material layer 1012 to form a third anti-etching layer 1172; after the first etching treatment, taking the top of the third anti-etching material layer 1012 or the top of the substrate 100 as the etching stop position, performing a second etching treatment on the second anti-etching material layer 1011 to form a second anti-etching layer 1171.

[0099] During the first etching process, the top of the second anti-etching material layer 1011 is used as the etching stop position, so that the bottom convex corners in the first anti-etching layer 116 are not easily transferred to the third anti-etching layer 1172, and the problem of over-etching or under-etching caused by inconsistent etching rates in different regions can be avoided, so that the formation quality of the third anti-etching layer 1172 is better.

[0100] During the second etching process, the top of the third anti-etching material layer 1012 or the top of the substrate 100 is used as the etching stop position, so that the bottom convex corners in the third anti-etching layer 1172 are not easily transferred to the second anti-etching layer 1171, and the problem of over-etching or under-etching caused by inconsistent etching rates in different regions can be avoided, so that the formation quality of the second anti-etching layer 1171 is better.

[0101] The process parameters of the first etching treatment include: the etching gas includes one or more of SiF4, NF3, CHF3 and C2F6.

[0102] It should be noted that the flow rate of the etching gas in the first etching treatment should not be too large. If the flow rate of the etching gas is too large, it is easy to cause the pressure in the chamber to be too high, and the etching gas etches the third anti-etching material layer 1012 exposed by the first anti-etching layer 116 at a faster rate, which is easy to cause the roughness of the side wall of the formed third anti-etching layer 1172 to be too large. In addition, if the flow rate of the etching gas is too large, it is easy to reduce the process controllability and reaction rate uniformity of the etching process, resulting in poor process stability. In this embodiment, the etching gas flow rate of the etching gas in the first etching treatment is less than 1000 sccm.

[0103] It should be noted that the chamber pressure of the first etching process should not be too high. If the chamber pressure of the first etching process is too high, the removal rate of the third anti-etching material layer 1012 exposed by the first anti-etching layer 116 is relatively fast, which is easy to reduce the process controllability and reaction rate uniformity of the first etching process. If the chamber pressure is too high, the decomposition rate of the byproducts generated by etching the third anti-etching material layer 1012 is too slow, which is easy to cause the third anti-etching layer 1172 to have a bottom convex corner. In this embodiment, the chamber pressure of the first etching process is less than 50mTorr.

[0104] The process parameters of the second etching treatment include: the etching gas includes one or more of CF4, C3F8, C4F8, CHF3 and NF3.

[0105] It should be noted that the flow rate of the etching gas of the second etching treatment should not be too large. If the flow rate of the etching gas is too large, it is easy to cause the pressure in the chamber to be too high, and the etching gas etches the second anti-etching layer 1171 to expose the second anti-etching material layer 1011 at a faster rate, which is easy to cause the roughness of the side wall of the formed second anti-etching layer 1171 to be too large. In addition, if the flow rate of the etching gas is too large, it is easy to reduce the process controllability and reaction rate uniformity of the etching treatment, resulting in poor process stability. In this embodiment, the etching gas flow rate of the second etching treatment is less than 1000 sccm.

[0106] It should be noted that the chamber pressure of the second etching treatment should not be too high. If the chamber pressure of the second etching treatment is too high, the removal rate of the second anti-etching material layer 1011 exposed by the third anti-etching layer 1172 is relatively fast, which is easy to reduce the process controllability and reaction rate uniformity of the second etching treatment. If the chamber pressure is too high, the decomposition rate of the byproducts generated by etching the second anti-etching material layer 1011 is too slow, which is easy to cause the second anti-etching layer 1171 to have a bottom convex corner. In this embodiment, the chamber pressure of the second etching treatment is less than 50mTorr.

[0107] refer to Fig.21The method for forming the semiconductor structure further includes: etching the substrate 100 using the etch stop structure 117 to form a target pattern.

[0108] The target pattern provides space for subsequent formation of an interconnection structure.

[0109] Specifically, the step of forming the target pattern includes: etching the dielectric layer to form an interconnect opening 118, and the interconnect opening 118 serves as the target pattern.

[0110] In other embodiments, the method for forming the semiconductor structure may further include: forming a third side wall on the side wall of the etch stop structure; after forming the third side wall, removing the etch stop structure; after removing the etch stop structure, using the third side wall as a mask to etch the substrate to form a target pattern.

[0111] Accordingly, combined with reference Fig.13 , an embodiment of the present invention also provides a semiconductor structure.

[0112] The semiconductor structure includes: a substrate 100; an etch stop material layer, located on the substrate 100; a first anti-etching material layer 102, located on the etch stop material layer; a graphic definition layer 103, located on the first anti-etching material layer 102; a plurality of spaced-apart doping layers 104, penetrating the graphic definition layer 103, the doping layers 104 being obtained by doping ions into a plurality of spaced-apart regions of the graphic definition layer 103, the etching resistance of the doping layers 104 being greater than the etching resistance of the graphic definition layer 103.

[0113] The doping layer 104 is formed by doping ions. Due to the angle of ion implantation, the doping layer 104 may have a bottom convex angle. Considering the problem of the bottom convex angle, an etching stop material layer is formed between the substrate 100 and the first anti-etching material layer 102. Therefore, in the subsequent process of forming the first anti-etching layer, the top of the etching stop material layer is used as the etching stop position, so that the bottom convex angle in the doping layer 104 is not easily transferred to the first anti-etching layer, and the problem of excessive or insufficient etching caused by the inconsistent etching rate of each region can be avoided, so that the formation quality of the first anti-etching layer is better; similarly, in the subsequent process of forming the etching stop structure, the top of the substrate 100 is used as the etching stop position, which further reduces the influence of the bottom convex angle phenomenon on the etching stop structure, and can also avoid the problem of excessive or insufficient etching caused by the inconsistent etching rate of each region, and finally the formation quality of the etching stop structure is better. In summary, the interconnect openings formed by etching the substrate 100 using the etch stop structure as a mask have good formation quality. The interconnect openings serve as target patterns, and the interconnect structures subsequently formed in the interconnect openings are less likely to have bridging or short circuits, which is beneficial to improving the electrical performance of the semiconductor structure.

[0114] The substrate 100 is prepared for subsequent etching to form a target pattern.

[0115] In this embodiment, the substrate 100 includes a dielectric layer. Specifically, the dielectric layer is made of a low-k dielectric material, which is beneficial to reducing the parasitic capacitance between the conductive layers, thereby reducing the RC delay of the subsequent stage.

[0116] In this embodiment, the material of the dielectric layer includes SiCOH.

[0117] The etch stop material layer is prepared for the subsequent formation of an etch stop structure.

[0118] The etch stop material layer includes a plurality of stacked etch stop sub-film layers, and an etch selectivity ratio exists between adjacent etch stop sub-film layers.

[0119] In the subsequent etching process of the etch stop material layer, the multiple etch stop sub-film layers are etched, and there is an etching selectivity ratio between adjacent etch stop sub-film layers, which can avoid the problem of over-etching or under-etching caused by inconsistent etching rates in different regions, and is beneficial to improving the formation quality of the etch stop structure.

[0120] Specifically, the plurality of etch stop sub-film layers constitute one or more stacked material layers 101, and the stacked material layer 101 includes a second anti-etching material layer 1011 and a third anti-etching material layer 1012 ( Fig. 9Only one stacked material layer 101 is shown in the figure. The stacked material layer 101 includes a second anti-etching material layer 1011 and a third anti-etching material layer 1012, that is, the etch stop material layer includes two etch stop sub-film layers, and the stacked material layer 101 does not need to be formed through too many process flows, which is conducive to improving the process compatibility of forming the etch stop material layer. In other embodiments, the number of etch stop sub-film layers in the one stacked material layer can also be three, four or five.

[0121] Specifically, the material of the second anti-etching material layer 1011 includes Si, Ge, SiO or SiN. In this embodiment, the material of the second anti-etching material layer 1011 includes SiO.

[0122] Specifically, the material of the third anti-etching material layer 1012 includes: Si, Ge, SiO or SiN. In this embodiment, the material of the third anti-etching material layer 1012 includes Si.

[0123] The first anti-etching material layer 102 is prepared for the subsequent formation of a first anti-etching layer.

[0124] Specifically, the material of the first anti-etching material layer 102 includes SiON, SiBCN, SiCN, and SiN. In this embodiment, the material of the first anti-etching material layer 102 is SiON.

[0125] The pattern definition layer 103 is used to provide a process platform for the subsequent formation of a doping layer.

[0126] In this embodiment, the material of the pattern definition layer 103 is amorphous silicon. Amorphous silicon is a commonly used material in the process, and the formation process is simple, which is conducive to reducing the process cost of the semiconductor structure. In other embodiments, the material of the pattern definition layer can also be silicon oxide.

[0127] The doping layer 104 is used as an etching mask for subsequent etching of the first anti-etching material layer 102 .

[0128] In this embodiment, the doping layer 104 is doped with one or more of B, P, C and N.

[0129] The semiconductor structure described in this embodiment can be formed by the formation method described in the above embodiment, or by other formation methods. For the specific description of the semiconductor structure described in this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0130] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, an etch stop material layer located on the substrate, a first anti-etching material layer located on the etch stop material layer, and a pattern definition layer located on the first anti-etching material layer, wherein the first anti-etching material layer is in contact with the etch stop material layer, the etch stop material layer comprises a plurality of stacked etch stop sub-film layers, adjacent etch stop sub-film layers have an etching selectivity ratio, the etch stop sub-film layer comprises a second anti-etching material layer and a third anti-etching material layer located on the second anti-etching material layer, the material of the second anti-etching material layer comprises SiO, and the material of the third anti-etching material layer comprises Si; doping ions into a plurality of spaced-apart regions of the pattern definition layer, wherein the pattern definition layer doped with ions serves as a doping layer, and the etching resistance of the doping layer is greater than that of the pattern definition layer; After forming the doping layer, removing the pattern definition layer; After removing the pattern definition layer, taking the top of the etch stop material layer as the etch stop position and taking the doping layer as a mask, etching the first anti-etching material layer to form a first anti-etching layer; The top of the substrate is used as an etching stop position, and the first anti-etching layer is used as a mask to etch the etching stop material layer to form an etching stop structure.

2. The method for forming a semiconductor structure according to claim 1, wherein: The plurality of etch stopper sub-film layers constitute one or more stacked material layers, and the stacked material layers include a second anti-etching material layer and a third anti-etching material layer located on the second anti-etching material layer.

3. The method for forming a semiconductor structure according to claim 2, wherein: The etch stop material layer is etched by an anisotropic dry etching process to form the etch stop structure.

4. The method for forming a semiconductor structure according to claim 3, wherein: The step of etching the etching stop material layer by using an anisotropic dry etching process comprises: Performing one or more etching processes, wherein the etching process is used to etch one of the stacked material layers, and the etching process includes: taking the top of the second anti-etching material layer as an etching stop position, performing a first etching process on the third anti-etching material layer to form a third anti-etching layer; After the first etching process, the second anti-etching material layer is subjected to a second etching process with the top of the third anti-etching material layer or the top of the substrate as an etching stop position to form a second anti-etching layer.

5. The method for forming a semiconductor structure according to claim 4, wherein: The process parameters of the first etching treatment include: the etching gas includes one or more of SiF4, NF3, CHF3 and C2F6, the etching gas flow rate is less than 1000 sccm, and the chamber pressure is less than 50 mTorr; The process parameters of the second etching treatment include: the etching gas includes one or more of CF4, C3F8, C4F8, CHF3 and NF3, the etching gas flow rate is less than 1000 sccm, and the chamber pressure is less than 50 mTorr.

6. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming the doping layer includes: forming a separate first mask layer on the pattern definition layer; using the first mask layer as a mask, injecting ions into the pattern definition layer exposed by the first mask layer to form the doping layer; The method for forming a semiconductor structure comprises: after forming the doping layer, removing the first mask layer.

7. The method for forming a semiconductor structure according to claim 6, wherein: The step of removing the first mask layer includes: forming a sacrificial material layer on the first mask layer and the doping layer between the first mask layer, the sacrificial material layer and the first mask layer having the same material, and the top surface of the sacrificial material layer being higher than or flush with the top surface of the first mask layer; and removing the sacrificial material layer and the first mask layer using a maskless dry etching process.

8. The method for forming a semiconductor structure according to claim 6, wherein: The method for forming a semiconductor structure further comprises: after forming the first mask layer, before injecting ions into the pattern definition layer between the first mask layers, forming a first spacer layer on the sidewall of the first mask layer, wherein the etching resistance of the first spacer layer is greater than the etching resistance of the first mask layer; In the step of implanting ions into the pattern definition layer between the first mask layers, ions are doped into the pattern definition layer exposed by the first mask layer and the first spacer layer.

9. The method for forming a semiconductor structure according to claim 1, wherein: The process parameters for doping ions in the multiple spaced-apart regions of the graphic definition layer include: the implanted ions include one or more of B, P, C and N, the ion implantation energy is less than 30 KeV, and the angle between the ion implantation angle and the normal line of the substrate surface is less than 30 degrees.

10. The method for forming a semiconductor structure according to claim 1, wherein: After forming the doping layer and before removing the pattern definition layer, the method further includes: forming a second mask layer on the doping layer and the pattern definition layer; Taking the top of the first anti-etching material layer as an etching stop position and taking the second mask layer as a mask to etch the doping layer; The method for forming the semiconductor structure further includes: after etching the doping layer using the second mask layer as a mask, removing the second mask layer.

11. The method for forming a semiconductor structure according to claim 10, wherein: After etching the doped layer with the second mask layer as a mask and before removing the pattern definition layer, the method further comprises: forming a second spacer layer on the exposed sidewalls of the pattern definition layer and the doped layer, wherein the etching resistance of the second spacer layer is greater than that of the pattern definition layer; In the step of etching the first anti-etching material layer using the doping layer as a mask, the first anti-etching material layer is etched using the doping layer and the second sidewall layer as masks.

12. The method for forming a semiconductor structure according to claim 1, wherein: The pattern definition layer is removed by a wet etching process.

13. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming a semiconductor structure further includes: etching the substrate using the etch stop structure as a mask to form a target pattern; or, The method for forming the semiconductor structure also includes: forming a third sidewall on the sidewall of the etch stop structure; after forming the third sidewall, removing the etch stop structure; after removing the etch stop structure, using the third sidewall as a mask to etch the substrate to form a target pattern.

14. The method for forming a semiconductor structure according to claim 13, wherein: The substrate includes a dielectric layer; The step of etching the substrate to form a target pattern includes: etching the dielectric layer to form an interconnect opening, wherein the interconnect opening serves as the target pattern.

15. A semiconductor structure, characterized in that: include: substrate; an etch stop material layer, located on the substrate; A first etch-resistant material layer is located on the etch-stop material layer, the first etch-resistant material layer is in contact with the etch-stop material layer, the etch-stop material layer includes a plurality of stacked etch-stop sub-film layers, and there is an etching selectivity ratio between adjacent etch-stop sub-film layers, the etch-stop sub-film layer includes a second etch-resistant material layer and a third etch-resistant material layer located on the second etch-resistant material layer, the material of the second etch-resistant material layer includes SiO, and the material of the third etch-resistant material layer includes Si; A pattern definition layer, located on the first anti-etching material layer; A plurality of spaced doping layers penetrate the pattern definition layer, wherein the doping layers are obtained by doping ions into a plurality of spaced regions of the pattern definition layer, and the etching resistance of the doping layers is greater than that of the pattern definition layer.

16. The semiconductor structure according to claim 15, wherein: The plurality of etch stopper sub-film layers constitute one or more stacked material layers, and the stacked material layers include a second anti-etching material layer and a third anti-etching material layer located on the second anti-etching material layer.

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