Semiconductor structure and method for forming the same

Abstract

An embodiment of the present invention provides a semiconductor structure, comprising: a first wire structure, contacting a first interconnect structure; a first tube core, formed on the first wire structure; a second wire structure, contacting a second interconnect structure, the second interconnect structure connected to the first interconnect structure; a second tube core, formed on the second wire structure. The purpose of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the yield of the semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor structures and methods of forming the same. Background Art

[0002] In a package structure with multiple electronic components, the circuit structure must simultaneously include the wire circuits of each electronic component. For example, in a fan-out chip-on-substrate (FOCoS) structure, an application-specific integrated circuit (ASIC) chip and a high-bandwidth memory (HBM) are simultaneously bonded to a structure that includes the fan-out circuits of the two. Due to the complexity of the circuits and the large size of the circuit manufacturing, the yield rate will be lower. Summary of the invention

[0003] In view of the problems existing in the related art, an object of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the yield of the semiconductor structure.

[0004] To achieve the above objectives, an embodiment of the present invention provides a semiconductor structure, including: a first wire structure, contacting a first interconnect structure; a first tube core, formed on the first wire structure; a second wire structure, contacting a second interconnect structure, the second interconnect structure connected to the first interconnect structure; and a second tube core, formed on the second wire structure.

[0005] In some embodiments, it also includes: a first dielectric layer, located on the upper and lower sides of the first conductor structure; a second dielectric layer, located on the upper and lower sides of the second conductor structure, the first conductor structure and the second conductor structure extend to the side walls of the first dielectric layer and the side walls of the second dielectric layer respectively, and the first interconnection structure and the second interconnection structure are in contact with the first dielectric layer and the second dielectric layer respectively.

[0006] In some embodiments, it also includes: a first dielectric layer, located on the upper and lower sides of the first conductor structure; a second dielectric layer, located on the upper and lower sides of the second conductor structure, the first conductor structure and the second conductor structure are respectively recessed relative to the sidewalls of the first dielectric layer and the sidewalls of the second dielectric layer, and the first interconnection structure and the second interconnection structure are respectively in contact with the first dielectric layer and the second dielectric layer.

[0007] In some embodiments, it also includes: a first dielectric layer, located on the upper and lower sides of the first wire structure; a second dielectric layer, located on the upper and lower sides of the second wire structure, the first wire structure and the second wire structure protrude relative to the sidewalls of the first dielectric layer and the sidewalls of the second dielectric layer, respectively, the sidewalls of the first dielectric layer and the second dielectric layer are respectively concave inwardly into an arc shape in a direction away from the first interconnection structure and the second interconnection structure, and the first interconnection structure and the second interconnection structure are in contact with the first dielectric layer and the second dielectric layer, respectively.

[0008] In some embodiments, the first interconnect structure and the second interconnect structure respectively cover the arc-shaped sidewalls of the first dielectric layer and the arc-shaped sidewalls of the second dielectric layer, and the first dielectric layer and the second dielectric layer respectively have sharp corners at the corresponding arc-shaped sidewalls.

[0009] In some embodiments, the first interconnect structure covers a sharp corner of the first dielectric layer, and the second interconnect structure covers a sharp corner of the second dielectric layer.

[0010] In some embodiments, an end of the first conductive line structure contacting the first interconnect structure is configured as a pointed end, and an end of the second conductive line structure contacting the second interconnect structure is configured as a pointed end.

[0011] In some embodiments, the method further includes: a first oxide layer covering a portion of the first conductive line structure and being adjacent to a tip of the first conductive line structure; and a second oxide layer covering a portion of the second conductive line structure and being adjacent to a tip of the second conductive line structure.

[0012] In some embodiments, the method further includes: a bridge structure located between the first conductive line structure and the second conductive line structure and electrically connected to the first interconnect structure and the second interconnect structure.

[0013] In some embodiments, the first wire structure and the second wire structure both have a first metal layer and a second metal layer stacked one above the other, the first interconnect structure and the second interconnect structure respectively cover ends of the first wire structure and the second wire structure, the first interconnect structure and the second interconnect structure are made of the same material as the first metal layer, the thickness of the first interconnect structure on the first metal layer is greater than the thickness of the first interconnect structure on the second metal layer, and the thickness of the second interconnect structure on the first metal layer is greater than the thickness of the second interconnect structure on the second metal layer.

[0014] An embodiment of the present application provides a method for forming a semiconductor structure, comprising: forming a first tube core on a first wire structure to form a first tube core packaging structure; forming a second tube core on a second wire structure to form a second tube core packaging structure; forming a first interconnection structure on a side wall of the first wire structure; forming a second interconnection structure on a side wall of the second wire structure; and docking the first interconnection structure to the second interconnection structure.

[0015] In some embodiments, the first interconnect structure and the second interconnect structure are formed using a chemical plating process.

[0016] In some embodiments, the first interconnect structure is butted to the second interconnect structure using an electroless plating process.

[0017] In some embodiments, a first dielectric layer is formed on the upper and lower sides of a first conductor structure. When preparing the first conductor structure, a cutting process is used to form a monolithic first conductor structure. When performing a chemical plating process, the first conductor structure extends to the side wall of the first dielectric layer, and the first interconnect structure contacts the first dielectric layer.

[0018] In some embodiments, a first dielectric layer is formed on the upper and lower sides of a first conductor structure. When preparing the first conductor structure, a cutting process is used to form a monolithic first conductor structure. A wet etching process is performed to make the first conductor structure recessed relative to the sidewall of the first dielectric layer, and the first interconnect structure contacts the first dielectric layer.

[0019] In some embodiments, the first dielectric layer is formed on the upper and lower sides of the first conductive line structure, and the first dielectric layer at the sidewall of the first die package structure is isotropically etched so that the sidewall of the first dielectric layer is concave into an arc shape.

[0020] In some embodiments, the first interconnect structure covers a sharp corner formed by the curved sidewall of the first dielectric layer and the first conductive line structure.

[0021] In some embodiments, an end of the first conductive line structure contacting the first interconnect structure is formed as a pointed end.

[0022] In some embodiments, forming a first tube core packaging structure includes: forming an oxide layer on the first wire structure; forming a mask layer on the oxide layer, the mask layer not covering the tip, and the mask layer covering a portion of the first wire structure adjacent to the tip; removing a portion of the oxide layer not covered by the mask layer; and removing the mask layer.

[0023] In some embodiments, forming the first conductive line structure includes: forming a second metal layer and a first metal layer located on the second metal layer, the first metal layer and the second metal layer being conformal.

[0024] In some embodiments, the first interconnect structure and the first metal layer are made of the same material, and a thickness of the first interconnect structure on the first metal layer is greater than a thickness of the first interconnect structure on the second metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0026] Figures 1 to 7 A cross-sectional view showing the formation process of the semiconductor structure of the present application.

[0027] Figures 8 to 22B Various embodiments of the semiconductor structure of the present application are shown.

[0028] Figure 23 to Figure 28 The cross-sectional views are shown showing the formation process of different embodiments of the semiconductor structure of the present application. DETAILED DESCRIPTION

[0029] In order to better understand the spirit of the embodiments of the present application, some preferred embodiments of the present application are further described below.

[0030] The embodiments of the present application will be described in detail below. In the full text of the present application specification, the same or similar components and components with the same or similar functions are represented by similar reference numerals. The embodiments of the accompanying drawings described herein are illustrative, graphical, and are used to provide a basic understanding of the present application. The embodiments of the present application should not be interpreted as limiting the present application.

[0031] As used herein, the terms "substantially," "substantially," "essentially," and "about" are used to describe and illustrate small variations. When used in conjunction with an event or circumstance, the terms may refer to instances where the event or circumstance occurred exactly as well as instances where the event or circumstance occurred very approximately. For example, when used in conjunction with a numerical value, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, two values ​​may be considered “substantially” the same if the difference between them is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%).

[0032] In this specification, unless otherwise specified or limited, relative terms such as "central", "longitudinal", "lateral", "front", "rear", "right", "left", "inner", "outer", "lower", "higher", "horizontal", "vertical", "above", "below", "above", "below", "top", "bottom" and their derivative terms (such as "horizontally", "downwardly", "upwardly", etc.) should be interpreted as referring to the directions described in the discussion or depicted in the drawings. These relative terms are only used for convenience of description and do not require that the present application be constructed or operated in a specific direction.

[0033] In addition, sometimes amounts, ratios and other numerical values ​​are presented in range format herein. It should be understood that such range format is for convenience and brevity, and should be flexibly understood to include not only the numerical values ​​explicitly specified as range limits, but also all individual numerical values ​​or sub-ranges encompassed within the range, as if each numerical value and sub-range were explicitly specified.

[0034] Furthermore, for ease of description, “first”, “second”, “third”, etc. may be used herein to distinguish different components in one figure or a series of figures. “First”, “second”, “third”, etc. are not intended to describe the corresponding components.

[0035] The semiconductor structure and the method for forming the same of the present application will be described in detail below with reference to the accompanying drawings.

[0036] See also Figure 1 , a first conductive line structure 10 is provided, and a first dielectric layer 12 is disposed on the first conductive line structure 10 .

[0037] See also Figure 2 , providing a first mask layer 20.

[0038] See also Figure 3 The first mask layer 20 covers the first conductive line structure 10 exposed on the first dielectric layer 12. A first plasma etching process is performed to etch the first dielectric layer 12 not covered by the first mask layer 20 to expose the first conductive line structure 10.

[0039] See also Figure 4 , providing a second conductor structure 40 and a second dielectric layer 42 located on the second conductor structure 40. The second dielectric layer 42 and the second conductor structure 40 are processed by the same processing technology as the first dielectric layer 12 and the first conductor structure 10. A first interconnect structure 44 and a second interconnect structure 46 are formed on the exposed first conductor structure 10 and the second conductor structure 40, respectively. In some embodiments, the first interconnect structure 44 and the second interconnect structure 46 are formed using a chemical plating process. In some embodiments, the first interconnect structure 44 is butted to the second interconnect structure 46 using a chemical plating process.

[0040] See also Figure 5 , remove the first mask layer 20.

[0041] See also Figure 6 , the first electronic component 60 and the second electronic component 62 are flip chip bonded (FCB) to the first wire structure 10 and the second wire structure 40 respectively.

[0042] See also Figure 7 In some embodiments, the first conductive line structure 10 , the second conductive line structure 40 , the first chip 60 , and the second chip 62 are encapsulated using a packaging material 70 .

[0043] See also Figure 8 In some embodiments, the packaging material 70 encapsulates the first chip 60 and the second chip 62 to form a first solder ball 80 electrically connected to the first conductive line structure 10 and the second conductive line structure 40 .

[0044] See also Fig. 9 In some embodiments, a filling material 90 is disposed between the first dielectric layer 12 and the second dielectric layer 42, and the filling material 90 surrounds the first interconnect structure 44 and the second interconnect structure 46. The packaging material 70 encapsulates the first conductive line structure 10, the second conductive line structure 40, the first chip 60 and the second chip 62.

[0045] See also Fig.10 In some embodiments, a filling material 90 is disposed between the first dielectric layer 12 and the second dielectric layer 42, and the filling material 90 surrounds the first interconnect structure 44 and the second interconnect structure 46. The packaging material 70 encapsulates the first conductive line structure 10, the second conductive line structure 40, the first chip 60 and the second chip 62. A first solder ball 80 electrically connected to the first conductive line structure 10 and the second conductive line structure 40 is formed.

[0046] See also Fig.11A , a partial cross-sectional view of the first conductive line structure 10 and the first dielectric layer 12 is shown. In an embodiment, the first conductive line structure 10 includes a first metal layer 101 and a second metal layer 102 stacked one above the other. If the first conductive line structure 10 and the first dielectric layer 12 are cut along the dotted line AA using a cutting process (e.g., a laser cutting process), the sidewalls of the first conductive line structure 10 and the first dielectric layer 12 are flush after cutting.

[0047] See also Fig. 11B , the first metal layer 101 extends upward to the sidewall of the first dielectric layer 12 .

[0048] See also Fig. 11C When the electroless plating process is performed to form the first interconnect structure 44 , the first interconnect structure 44 also contacts the sidewall of the first dielectric layer 12 .

[0049] See also Fig. 12A In some embodiments, Fig.11A After the step of etching, the first metal layer 101 and the second metal layer 102 are etched to make the first metal layer 101 and the second metal layer 102 recessed relative to the first dielectric layer 12. In some embodiments, a wet etching process is performed to make the first metal layer 101 and the second metal layer 102 recessed relative to the first dielectric layer 12.

[0050] See also Fig. 12B, the first dielectric layer 12 is etched to make the first metal layer 101 and the second metal layer 102 protrude outward relative to the first dielectric layer 12. In some embodiments, a wet etching process is performed to make the first metal layer 101 and the second metal layer 102 protrude outward relative to the first dielectric layer 12.

[0051] See also Fig. 12C When the electroless plating process is performed to form the first interconnect structure 44 , the first interconnect structure 44 contacts the sidewall of the first dielectric layer 12 .

[0052] See also Fig.13 In some embodiments, Fig. 12A A chemical plating process is directly performed on the basis of the first dielectric layer 12 to form a first interconnect structure 44 , where the first interconnect structure 44 contacts the sidewall of the first dielectric layer 12 .

[0053] See also Fig.14A In some embodiments, Fig.11A After the step of etching, the first dielectric layer 12 is directly etched to be recessed inwardly relative to the first conductive line structure 10 .

[0054] See also Fig. 14B , chemical plating is performed directly on the protruding first conductive line structure 10 to form a first interconnect structure 44 , and the first interconnect structure 44 contacts the first dielectric layer 12 .

[0055] See also Fig.15A , shows a three-dimensional view of a first conductive line structure 10 located on a first dielectric layer 12, wherein an end portion 140 of the first conductive line structure 10 has a tip 103. In some embodiments, the tip 103 can prevent the metal material from growing toward both sides as much as possible.

[0056] See also Fig. 15B , a first oxide layer 140 is used to cover a portion of the first conductive line structure 10 .

[0057] See also Fig. 15C , the second mask layer 142 covers part of the first oxide layer 140 .

[0058] See also Fig.15D , the first oxide layer 140 is etched using the second mask layer 142 as a mask.

[0059] See also Fig.15E The remaining first oxide layer 140 does not cover the tip 103 and is adjacent to the tip 103. The first oxide layer 140 can prevent the first circuit structure 10 from being exposed too much and growing around.

[0060] See also Fig.16, a stereoscopic view of a plurality of first conductor structures 10 and a plurality of second conductor structures 40 respectively located in and on a first dielectric layer 12 and a second dielectric layer 42 is shown, wherein the first dielectric layer 12 and the second dielectric layer above the first conductor structure 10 and the second conductor structure 40 located at the bottom layer are displayed semi-transparently to more clearly show the internal structure. In some embodiments, the distance H between the upper and lower first conductor structures 10 or the adjacent second conductor structures 40 is greater than 60 μm to avoid bridging problems. In some embodiments, the distance W between adjacent first conductor structures 10 or adjacent second conductor structures 40 of the same layer is greater than 60 μm to avoid bridging problems. In some embodiments, the distance D between a first conductor structure 10 and a corresponding second conductor structure 40 is less than 30 μm.

[0061] See also Fig.17 , in some embodiments, further comprising: a bridge structure 170, located between the first conductive line structure 10 and the second conductive line structure 40, and electrically connected to the first interconnect structure 10 and the second interconnect structure 40. In some embodiments, the line layer in the bridge structure 170 is electrically connected to the first interconnect structure 44 and the second interconnect structure 46 on the left and right sides, respectively.

[0062] See also Fig.18 In some embodiments, the interconnection concept of the present application can be applied between chips, and the third wire structure 181 of the third chip 180 is interconnected with the fourth wire structure 184 of the fourth chip 182. In some embodiments, Figures 1 to 10 As shown, the interconnection concept of the present application is applied between substrates.

[0063] See also Fig.19 In some embodiments, the interconnection concept of the present application can be applied between fan-out structures, and the fifth conductive line structure 191 of the first fan-out structure 191 is interconnected with the sixth conductive line structure 191 of the second fan-out structure 191.

[0064] See also Fig. 20A In some embodiments, a first conductive line structure 10 encapsulated by a first dielectric layer 12 is provided.

[0065] See also Fig. 20B , the first dielectric layer 12 is directly isotropically etched to expose the first conductive line structure 10 .

[0066] See also Fig. 20C , an electroless plating process is performed to form a first interconnect structure 44 and a second interconnect structure 46. The sidewalls of the first dielectric layer 12 and the second dielectric layer 42 are respectively concave inwardly in a direction away from the first interconnect structure 44 and the second interconnect structure 46 into an arc shape.

[0067] See also Fig.20D , Fig.20Dyes Fig. 20C : An enlarged view of the first interconnect structure 44 and the second interconnect structure 46 in FIG. The first interconnect structure 44 and the second interconnect structure 46 respectively cover a portion of the arc-shaped sidewall of the first dielectric layer 12 and a portion of the arc-shaped sidewall of the second dielectric layer 42, and the first dielectric layer 12 and the second dielectric layer 42 respectively have sharp corners at the corresponding arc-shaped sidewalls. The first interconnect structure 44 covers the sharp corner of the first dielectric layer 12, and the second interconnect structure 46 covers the sharp corner of the second dielectric layer 42. The first interconnect structure 44 and the second interconnect structure 46 are made of the same material as the first metal layer 101 (for example, both include copper), and the thickness H1 of the first interconnect structure 44 on the first metal layer 101 is greater than the thickness H2 of the first interconnect structure 44 on the second metal layer 102 (for example, including titanium), and the thickness H1 of the second interconnect structure 46 on the first metal layer 101 is greater than the thickness H2 of the second interconnect structure on the second metal layer 102. A width D1 of the first interconnect structure 44 extending on the first metal layer 101 is greater than a width D2 of the first interconnect structure 44 extending on the second metal layer 102 .

[0068] See also Fig.21A An end dielectric layer 210 is additionally provided and is located at an end of the first conductive line structure 10 .

[0069] See also Fig.21B , cutting the entire structure to expose the end dielectric layer 210 .

[0070] See also Fig. 21C , the end dielectric layer 210 is etched away, and the first dielectric layer 12 is used as an etching mask.

[0071] See also Fig.21D , an electroless plating process is performed to form a first interconnect structure 44 and a second interconnect structure 46 .

[0072] See also Fig.21E , shows an enlarged view of the first interconnect structure 44 and the second interconnect structure 46, wherein the thickness H3 of the first interconnect structure 44 on the first conductive line structure 10 is greater than the thickness H4 of the first interconnect structure 44 on the first dielectric layer 12. In addition, the portion of the first interconnect structure 44 extending on the first conductive line structure 10 laterally contacts the sidewall of the first dielectric layer 12. The portion of the first interconnect structure 44 extending on the first dielectric layer 12 does not laterally contact the sidewall of the first dielectric layer 12.

[0073] See also Fig.22A ,exist Fig.21A After the steps, no Fig.21B The cutting step is performed to directly etch to expose the end dielectric layer 210. In some embodiments, the etching rate of the end dielectric layer 210 is lower than that of the first dielectric layer 12.

[0074] See also Fig. 22B After the end dielectric layer 210 is etched, an electroless plating process is performed to form the first interconnect structure 44 and the second interconnect structure 46 .

[0075] See also Figure 23 to Figure 28 , showing a method for forming a semiconductor structure (chip-first process) according to different embodiments of the present application.

[0076] See also Fig.23 , providing a first circuit structure 10, a second circuit structure 40, and a first chip 60 and a second chip 62 electrically connected to the first circuit structure 10 and the second circuit structure 40 respectively.

[0077] See also Fig.24 , cutting to form separated first structures 240 and second structures 242 , so as to form separated first dielectric layers 12 and second dielectric layers 42 .

[0078] See also Fig.25 , the first dielectric layer 12 and the second dielectric layer 42 are etched to expose the first wiring structure 10 and the second wiring structure 40. In an embodiment, the etching is performed using a plasma etching process or a wet etching process.

[0079] See also Fig.26 , adjust the positions of the first structure 240 and the second structure 242 so that the exposed first circuit structure 10 and the second circuit structure 40 face each other.

[0080] See also Fig. 27 , an electroless plating process is performed to form the first interconnect structure 44 and the second interconnect structure 46. In some embodiments, the electroless plating process is chemical plating or electroplating.

[0081] See also Fig.28 The entire structure is encapsulated using a molding compound 280 to form a semiconductor structure 282 .

[0082] The embodiment of the present application utilizes an electroless plating process to perform circuit docking, so that small substrates (low cost) can be spliced ​​into a large substrate (high value). The dielectric layer of existing semiconductor structures generally covers the circuit structure, but the present application exposes the circuit structure to achieve interconnection and docking between two semiconductor structures.

[0083] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A semiconductor structure, characterized in that: include: a first conductive line structure contacting the first interconnect structure; A first tube die is formed on the first conductive line structure; a second conductive line structure contacting a second interconnect structure, wherein the second interconnect structure is connected to the first interconnect structure; a second tube die formed on the second conductive line structure; A first dielectric layer, located at the upper and lower sides of the first conductive line structure; A second dielectric layer is located at the upper and lower sides of the second conductor structure, The first conductive line structure and the second conductive line structure protrude relative to the sidewalls of the first dielectric layer and the second dielectric layer, respectively. The sidewalls of the first dielectric layer and the second dielectric layer are respectively concave inwardly into an arc shape in a direction away from the first interconnect structure and the second interconnect structure. The first interconnect structure and the second interconnect structure are in contact with the first dielectric layer and the second dielectric layer, respectively.

2. The semiconductor structure according to claim 1, characterized in that: The first interconnect structure and the second interconnect structure respectively cover the arc-shaped sidewalls of the first dielectric layer and the arc-shaped sidewalls of the second dielectric layer, and the first dielectric layer and the second dielectric layer respectively have sharp corners at the corresponding arc-shaped sidewalls.

3. The semiconductor structure according to claim 2, characterized in that: The first interconnect structure covers the sharp corner of the first dielectric layer, and the second interconnect structure covers the sharp corner of the second dielectric layer.

4. The semiconductor structure according to claim 1, characterized in that An end of the first conductor structure contacting the first interconnect structure is configured as a pointed end, and an end of the second conductor structure contacting the second interconnect structure is configured as a pointed end.

5. The semiconductor structure according to claim 1, characterized in that: Also includes: a first oxide layer covering a portion of the first conductive line structure and adjacent to a tip of the first conductive line structure; The second oxide layer covers a portion of the second conductive line structure and is adjacent to a tip of the second conductive line structure.

6. The semiconductor structure according to claim 1, characterized in that Also includes: A bridge structure is located between the first conductive line structure and the second conductive line structure and is electrically connected to the first interconnect structure and the second interconnect structure.

7. A semiconductor structure, characterized in that: include: a first conductive line structure contacting the first interconnect structure; A first tube die is formed on the first conductive line structure; a second conductive line structure contacting a second interconnect structure, wherein the second interconnect structure is connected to the first interconnect structure; a second tube die formed on the second conductive line structure; The first conductive line structure and the second conductive line structure each have a first metal layer and a second metal layer stacked one above the other. The first interconnect structure and the second interconnect structure respectively cover ends of the first conductive line structure and the second conductive line structure. The first interconnect structure and the second interconnect structure are made of the same material as the first metal layer. The thickness of the first interconnect structure on the first metal layer is greater than the thickness of the first interconnect structure on the second metal layer. The thickness of the second interconnect structure on the first metal layer is greater than the thickness of the second interconnect structure on the second metal layer.

8. The semiconductor structure according to claim 7, characterized in that: Also includes: A first dielectric layer, located at the upper and lower sides of the first conductive line structure; A second dielectric layer is located at the upper and lower sides of the second conductor structure, The first conductive line structure and the second conductive line structure extend onto sidewalls of the first dielectric layer and the second dielectric layer, respectively. The first interconnect structure and the second interconnect structure contact the first dielectric layer and the second dielectric layer, respectively.

9. The semiconductor structure according to claim 7, characterized in that: Also includes: A first dielectric layer, located at the upper and lower sides of the first conductive line structure; A second dielectric layer is located at the upper and lower sides of the second conductor structure, The first conductive line structure and the second conductive line structure are recessed relative to the sidewalls of the first dielectric layer and the second dielectric layer, respectively, and the first interconnect structure and the second interconnect structure are in contact with the first dielectric layer and the second dielectric layer, respectively.

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