An enhanced high-voltage HEMT device with a multi-finger buried gate structure and a method for preparing the same

Abstract

The present invention relates to an enhanced high-voltage HEMT device with a multi-finger buried gate structure and a preparation method thereof, comprising a stress release layer, a high-resistance buffer layer, a channel layer, an insertion layer and a barrier layer stacked in sequence; a source electrode and a drain electrode are located at both ends of the barrier layer and are in contact with the insertion layer; a gate electrode is located on the barrier layer; a gate dielectric layer is located between the gate electrode and the barrier layer; a multi-finger buried gate structure including a finger buried gate unit extends along the surface of the barrier layer to a certain depth in the barrier layer, and in the direction from the source electrode to the drain electrode, a plurality of PN junctions arranged in sequence are formed between the multi-finger buried gate structure and the barrier layer. The invention adopts the introduction of a multi-finger buried gate structure formed by an ion implantation process, which greatly improves the withstand voltage characteristics of the device, reduces the leakage current of the gate electrode, increases the upper limit of the saturated drain current, and increases the output current while obtaining an enhanced device.

Description

Technical Field

[0001] The present invention relates to the technical field of HEMT devices, and in particular to an enhanced high-voltage HEMT device with a multi-finger buried gate structure and a preparation method thereof. Background Art

[0002] A two-dimensional electron gas (2DEG) with high mobility electron density is formed at the AlGaN / GaN interface due to spontaneous polarization and piezoelectric polarization. However, the high-density 2DEG will cause the HEMT device to be in the on state when the device is in the zero bias state, becoming a normally-on device. Although normally-on AlGaN / GaN is used in low-voltage and high-frequency applications, for power switching applications, normally-off characteristics are often required to ensure safe operation and simple gate drive configuration, thereby ensuring widespread application in power electronic devices. At the same time, the AlGaN / GaN HEMT device structure has a high withstand voltage characteristic in theory, but the actual breakdown is only a few hundred volts, which is still a long way from the maximum breakdown limit of GaN.

[0003] At present, the methods for realizing normally-off characteristics, that is, enhancement-mode HEMT power devices, include recessed gate structure, fluorine ion implantation technology, P-GaN gate technology, and cascade structure. In these structures, there are more or less inevitable defects. (1) The recessed gate can only reduce the polarization charge density in the area under the gate, the precise etching of the barrier layer is difficult to control in the process, the threshold voltage is closely related to the thickness of the AlGaN barrier layer, it is difficult to accurately control the threshold voltage of the device, and the process repeatability is poor. (2) Fluorine ion implantation has important advantages in terms of technical controllability, ease of operation, and reduction of lattice damage, but it will inevitably produce a small amount of fluorine ions in the channel, resulting in a decrease in carrier mobility in the channel. (3) The cascade structure is a circuit structure design that combines the entire face of the enhancement-mode MOSFET and the high-voltage depletion-mode GaN HEMT device, but this method has problems such as high cost, resistance series parasitic effects, and limited operating temperature. (4) P-GaN gate technology can effectively avoid many of the above-mentioned problems by inserting a P-GaN layer between the gate and the AlGaN barrier layer and increasing the height of the barrier layer to obtain an enhanced device. However, the current P-GaN gate technology still has problems such as small gate swing and limited gate drive capability, and the P-GaN cap layer needs to be selectively removed by etching. During this process, the AlGaN barrier layer below will be damaged by plasma impact, resulting in an increase in surface trap density and a decrease in 2DEG concentration and mobility in the channel, thereby increasing the on-resistance of the device. Summary of the invention

[0004] In view of the technical problems existing in the prior art, the primary purpose of the present invention is to provide an enhanced high-voltage HEMT device with a multi-finger buried gate structure and a preparation method thereof. The device forms a multi-finger buried gate structure including multiple finger buried gate units along the surface of the barrier layer to a certain depth through an ion implantation process, so that the thickness of the AlGaN barrier layer in the gate area can be thinned, and the 2DEG concentration generated by the polarization effect is reduced. At the same time, due to the introduction of a p-type AlGaN buried gate on the AlGaN barrier layer, the conduction band of AlGaN in the channel is raised to above the Fermi level, resulting in 2DEG depletion to obtain a high threshold voltage. Since conventional P-GaN HEMTs require a thinner AlGaN thickness to ensure that they can be in the off state under normal circumstances, the AlGaN thickness in the non-gate area is also thinner, and the resulting 2DEG concentration is low, which limits the saturated drain current. The HEMT device of the multi-finger buried gate structure of the present invention is a device in which n-type AlGaN is converted into p-type AlGaN in the gate region by ion implantation, so that the thickness of n-type AlGaN in the gate region is controllable, thereby allowing a larger AlGaN thickness in the non-gate region, raising the upper limit of the saturated drain current, and increasing the output current while obtaining an enhanced device. A gate dielectric layer is arranged on the surface of the multi-finger buried gate structure, which serves as a protective layer while obtaining an enhanced device, preventing damage and decomposition of the ion implantation region during high-temperature annealing, reducing defects and impurities near the gate region, thereby reducing the influence of gate leakage current on the device when the device is operating normally.

[0005] In addition, the p-type AlGaN buried gate with a multi-finger structure obtained by ion implantation in the present invention will form multiple PN junctions in the horizontal direction with the unintentionally doped n-AlGaN in the region below the gate, and the PN junction can withstand a higher reverse bias under the same peak electric field. When the gate is in the off state and the drain is positively biased, the PN junction is in a reverse biased state, and the electric field generated by its external bias in the space charge region is consistent with the built-in electric field of the PN junction. Therefore, the electric field in the space charge region is enhanced, and its depletion region extends to both sides, increasing the width of the depletion region and improving the barrier height. Since both the external voltage and the contact potential difference fall in the depletion layer, the wider depletion region can withstand more voltage, greatly improving the withstand voltage characteristics of the device, while reducing the leakage current of the gate.

[0006] From the process point of view, the device proposed in the present invention directly performs ion implantation on the proposed gate-under-gate region in the AlGaN barrier layer to obtain a P-AlGaN buried gate. Compared with the process of first growing a thick p-type GaN layer on the barrier layer and then etching the p-type GaN layer to leave only the GaN layer in the gate region to form a GaN cap layer in the conventional P-GaN HEMT power device manufacturing process, the present invention simplifies the manufacturing process of the device by using an ion implantation process that can be precisely doped and is highly compatible with metal oxide semiconductor technology, while avoiding the traditional ICP etching process that easily generates a large number of defects and impurities, causing interface state problems on the AlGaN surface, and defects and impurities are also prone to form leakage paths, resulting in premature breakdown of the gate voltage.

[0007] In order to achieve the above object, the present invention adopts at least the following technical solutions:

[0008] One aspect of the present invention provides an enhanced high-voltage HEMT device with a multi-finger buried gate structure, comprising a stress release layer, a high-resistance buffer layer, a channel layer, an insertion layer and a barrier layer stacked in sequence; wherein:

[0009] A source electrode and a drain electrode are located at two ends of the barrier layer and contact the insertion layer;

[0010] a gate, located on the barrier layer;

[0011] a gate dielectric layer, located between the gate and the barrier layer;

[0012] The multi-finger buried gate structure including the buried gate unit extends along the surface of the barrier layer to a certain depth in the barrier layer, and forms a plurality of sequentially arranged PN junctions between the multi-finger buried gate structure and the barrier layer in the direction from the source to the drain.

[0013] Furthermore, the multi-interpolated finger buried gate structure comprises at least three interpolated finger buried gate units formed by an ion implantation process, and the interpolated finger buried gate units are sequentially arranged at intervals in a direction from the source to the drain.

[0014] Furthermore, the width of the multi-finger buried gate structure in the direction from the source to the drain is equal to the width of the gate.

[0015] Furthermore, the thickness of the multi-finger buried gate structure is smaller than that of the barrier layer, the barrier layer is an n-type AlGaN layer, the Al component of which is 0.1 to 0.3 and the thickness is 30 to 50 nm; the doping concentration of the multi-finger buried gate structure is greater than or equal to 10 8 cm -3 , thickness is 10 to 30 nm.

[0016] Furthermore, the gate dielectric layer is made of HfO2, Al2O3, TiO2 or SiO2, and has a thickness of 5 to 10 nm.

[0017] Furthermore, the channel layer is a GaN channel layer with a thickness of 50-70 nm; the insertion layer is an AlN insertion layer with a thickness of 1-2 nm.

[0018] Furthermore, the thickness of the AlGaN barrier layer is selected to be 30 nm, and the Al composition thereof is selected to be 0.24.

[0019] Furthermore, the stress release layer is an AlN stress release layer; and the high resistance buffer layer is a GaN high resistance layer.

[0020] Furthermore, it also includes a passivation layer arranged on the surface of the barrier layer between the source / drain and the gate.

[0021] Another aspect of the present invention provides an enhanced high-voltage HEMT device with a multi-finger buried gate structure, comprising the following steps:

[0022] A stress release layer, a high resistance buffer layer, a channel layer, an insertion layer and a barrier layer are sequentially grown on the substrate;

[0023] An ion implantation process is used to form a multi-finger buried gate structure of a certain depth in a predetermined area on the surface of the barrier layer, wherein the multi-finger buried gate structure comprises a plurality of interleaved finger buried gate units arranged at intervals, and the conductivity type of the interleaved finger buried gate units is opposite to that of the barrier layer;

[0024] Depositing a gate dielectric layer on the surface of the multi-finger buried gate structure, followed by high temperature annealing;

[0025] Etching the barrier layer to form source and drain regions, and depositing source and drain metals;

[0026] forming a gate region on the gate dielectric layer and depositing a gate metal;

[0027] Depositing a passivation layer to cover the region between the gate and the source, and to cover the region between the gate and the drain;

[0028] The inserted finger buried gate units are sequentially arranged at intervals in a direction from the source to the drain. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic structural diagram of an enhancement-mode high-voltage HEMT device according to an embodiment of the present invention.

[0030] Figure 2 It is a comparison diagram of the process steps of the enhancement-mode high-voltage HEMT device according to the embodiment of the present invention and the conventional p-GaN cap layer device.

[0031] Figure 3 It is a schematic diagram of the working state of the PN junction in the multi-finger buried gate structure region in the enhanced high-voltage HEMT device according to an embodiment of the present invention.

[0032] Figure 4 It is a DC characteristic diagram of the enhancement mode high voltage HEMT device according to an embodiment of the present invention.

[0033] Figure 5 3 is a transfer characteristic diagram of an enhanced high-voltage HEMT device according to an embodiment of the present invention.

[0034] Figure 6 4 is a breakdown voltage diagram of an enhanced high-voltage HEMT device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0035] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings of the present invention. The described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, other embodiments obtained by ordinary technicians in this field without creative work are all within the scope of protection of the present invention. The experimental methods described in the following embodiments are all conventional methods unless otherwise specified; the reagents and materials, unless otherwise specified, can be obtained from public commercial channels.

[0036] Spatially relative terms such as "below," "beneath," "below," "above," "upper," etc. are used in this specification to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to different orientations than those depicted in the figures.

[0037] In addition, the use of terms such as "first", "second", etc. to describe various elements, layers, regions, sections, etc. is not intended to be limiting. The use of "having", "containing", "including", "comprising", etc. is open-ended, indicating the presence of the stated elements or features, but does not exclude additional elements or features. Unless the context clearly states otherwise.

[0038] like Figure 1As shown, an embodiment of the present invention provides an enhanced high-voltage HEMT device with a multi-finger buried gate structure, comprising a stress release layer 2, a high-resistance buffer layer 3, a channel layer 4, an insertion layer 5 and a barrier layer 6 stacked in sequence on a substrate 1. The substrate 1 may include sapphire, Si or SiC. In this embodiment, a sapphire substrate with low cost and high crystal quality is preferred. The stress release layer 2 is made of AlN material. Preferably, a 15nm thick AlN stress release layer is grown on the surface of the substrate by a magnetron sputtering process. The high-resistance buffer layer 3 is preferably a GaN high-resistance buffer layer with a thickness of 2 to 5um. In this example, the thickness of the GaN high-resistance buffer layer is selected to be 3um. The GaN high-resistance buffer layer is grown on the AlN stress release layer by an MOCVD process, which effectively inhibits the diffusion of oxygen from the substrate to the GaN layer. The obtained high-resistance GaN is of high quality, which alleviates the leakage problem of the buffer layer, prevents the premature breakdown of the device, and reduces the background carrier concentration.

[0039] The direction along which the material grows is the positive direction. Figure 1 In the example shown. Continue to use the MOCVD growth process to sequentially grow the channel layer 4, the insertion layer 5 and the barrier layer 6 on the surface of the GaN buffer layer. The channel layer 4 is preferably a GaN channel layer, and the thickness of the channel layer is 70nm. The insertion layer 5 is preferably an AlN insertion layer, and its thickness is preferably 1nm. The barrier layer 6 is preferably an n-type AlGaN barrier layer. Since the thickness and Al component of the AlGaN barrier layer are two important parameters of the heterojunction band diagram, in order to achieve normally-off behavior under zero bias equilibrium conditions, the thickness of the AlGaN barrier layer is preferably 30nm, and the Al component is preferably 0.24. Due to their own spontaneous polarization and piezoelectric polarization, the AlGaN barrier layer 6 and the GaN channel layer 4 form a high electron mobility and high concentration 2DEG on the AlGaN / GaN surface close to the GaN channel layer side. The AlN insertion layer 5 can help form a deeper and narrower triangular potential well on the AlGaN / GaN surface, further improving the channel electron density, while suppressing the leakage of 2DEG into the AlGaN barrier layer, reducing the leakage current and slowing down the current collapse phenomenon.

[0040] The multi-finger buried gate structure 7 extends to a certain depth in the barrier layer along a predetermined surface area of ​​the barrier layer. Specifically, the multi-finger buried gate structure 7 includes a plurality of interleaved finger buried gate units. Preferably, the total width of the multi-finger buried gate structure 7 is 1 μm; an ion implantation process is used to form three interleaved p-type AlGaN interleaved finger buried gate units with a width (i.e., the direction from the source to the drain or the drain to the source) of 0.2 μm and a thickness of 15 nm in a predetermined area on the surface of the barrier layer 6, and the interval between the interleaved finger buried gate units is 0.2 μm. Unless otherwise specified in this specification, the width refers to the direction from the source to the drain or the drain to the source. The arrangement of the multi-finger buried gate structure in the vertical direction (i.e., the direction perpendicular to the substrate) has the advantages of thinning the barrier layer under the gate, increasing the conduction band height of the AlGaN barrier layer, depleting the 2DEG concentration under the gate, avoiding the regrowth of the P-GaN cap layer, and reducing the damage caused by ICP etching. In the horizontal direction, three p-type AlGaN buried gates and n-type AlGaN barrier layers form multiple PN junction structures. When a drain bias is applied, the PN junction structure is similar to a diode in a reverse bias state. The depletion region increases and can withstand more voltage drops, thereby improving the device's withstand voltage characteristics and greatly improving the critical breakdown voltage. The critical voltage value reaches about 1948V. Compared with the conventional P-GaN cap layer HEMT device with a breakdown voltage of several hundred volts, the arrangement of the multi-finger buried gate structure greatly improves the device's withstand voltage characteristics.

[0041] The gate dielectric layer 8 is arranged on the surface of the multi-finger buried gate structure 7. In this embodiment, SiO2 is selected for the gate dielectric layer 8. The gate dielectric layer 8 serves as a protective layer for the subsequent annealing process. The provision of the dielectric layer can inhibit the surface decomposition of the high temperature annealing device and reduce the leakage current of the gate.

[0042] The gate 11 is arranged on the surface of the gate dielectric layer 8, and the gate is selected from Ti / Al / Mo / Au. The drain 9 and the source 12 are arranged at both ends of the barrier layer 6, and are in contact with the surface of the insertion layer 5. The drain 9 and the source 12 are selected from Ti / Al / Ni / Au alloy or Ti / Al / Ti / TiN alloy. The passivation layer 10 is arranged on the surface of the barrier layer 6, and is arranged between the gate 11 and the source 12 and the drain 9. In this embodiment, the passivation layer is selected from Si3N4. The P-type AlGaN multi-finger buried gate structure, the gate dielectric layer and the metal gate form a MIS-HEMT groove gate structure.

[0043] In order to more clearly understand the device of the present invention, the preparation method of the device is introduced below in combination with the above-mentioned enhancement mode high voltage HEMT device structure.

[0044] First, a 15nm thick stress release layer is grown on a sapphire substrate using a magnetron sputtering process. Then, a 3um thick GaN high-resistance buffer layer, a 70nm GaN channel layer, a 1nm AlN insertion layer, and a 30nm thick AlGaN barrier layer are grown on the stress release layer using an MOCVD growth process, where the Al component in the AlGaN barrier layer is 0.24.

[0045] Next, a mask pattern is formed in a predetermined area on the surface of the AlGaN barrier layer, and an ion implantation process is used to form a multi-finger buried gate structure in the predetermined area. The multi-finger buried gate structure includes three p-type finger buried gate units arranged at intervals of 0.2 μm, and the doping concentration of the finger buried gate unit is greater than or equal to 10 8 cm -3 , thickness is 15nm and width is 0.2um.

[0046] The mask pattern is removed, a photoresist layer is spin-coated, a predetermined photoresist pattern of the gate dielectric layer is formed, a SiO2 layer is deposited, the photoresist pattern is removed, and a SiO2 gate dielectric layer is formed. A high-temperature annealing process is then performed, preferably, in an N2 atmosphere, annealing is performed at a temperature of 1230°C for 30 minutes to activate the doped ions of the p-type buried-gate unit. At this time, the SiO2 gate dielectric layer serves as a protective layer for the ion implantation region, inhibiting the decomposition of the surface of the ion implantation region during the high-temperature annealing process, reducing defects and impurities near the gate region, thereby reducing the influence of the gate leakage current on the device when the device is operating normally.

[0047] Next, a mask layer is deposited to form a mask pattern, and the two ends of the barrier layer are etched using the mask pattern as a mask to form source and drain regions, and a metal layer is deposited to form the source and drain. The source and drain metal layers are made of Ti / Al / Ni / Au alloy or Ti / Al / Ti / TiN alloy.

[0048] The mask layer is continuously deposited to form a mask pattern, the gate dielectric layer is exposed to form a gate region, and a metal layer is deposited to form a gate. The gate metal layer is Ti / Al / Mo / Au.

[0049] Finally, a Si3N4 passivation layer is deposited to fill the area between the gate and the source, and to fill the area between the gate and the drain.

[0050] Figure 3 This is a schematic diagram of the PN junction working state in the multi-finger buried gate structure region of this embodiment. In this working state, the source is grounded, the gate is zero biased and in the off state, and the p-type AlGaN multi-finger buried gate and the n-type AlGaN barrier layer form multiple PN junctions under the condition of positive bias of the drain. The PN junction can be regarded as a diode. When a positive bias is applied from the outside, the three PN junctions are in a reverse bias state, and the depletion region becomes wider, which greatly improves the withstand voltage of the device and reduces the gate leakage current.

[0051] Figure 4 The device DC characteristic diagram of this embodiment is shown, and it can be seen that when the gate voltage is 6V, the saturated output current reaches nearly 600mA / mm. Figure 5 From the device transfer characteristic diagram, it can be seen that when the drain voltage is 10V, the threshold voltage is about 3V. Figure 6 From the device breakdown voltage characteristic curve, it can be seen that when the gate voltage is set to -1V, the channel is in the off state, the drain voltage is continuously increased, and the critical breakdown voltage value of the device reaches 1948V.

[0052] The above embodiments are preferred implementation modes of the present invention, but the implementation modes of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications that do not deviate from the spirit and principles of the present invention should be equivalent replacement methods and are included in the protection scope of the present invention.

Claims

1. An enhanced high-voltage HEMT device with a multi-finger buried gate structure, It is characterized in that It includes a stress release layer, a high resistance buffer layer, a channel layer, an insertion layer and a barrier layer stacked in sequence; wherein, A source electrode and a drain electrode are located at two ends of the barrier layer and contact the insertion layer; a gate, located on the barrier layer; a gate dielectric layer, located between the gate and the barrier layer; A multi-finger buried gate structure comprising at least three p-type interdigitated buried gate units, extending along the surface of the barrier layer to a certain depth in the barrier layer, the interdigitated buried gate units are sequentially arranged at intervals in the direction from the source to the drain, and the width of the multi-finger buried gate structure in the direction from the source to the drain is equal to the width of the gate, and the multi-finger buried gate structure and the barrier layer form sequentially arranged PN junctions; The invention also includes a passivation layer arranged on the surface of the barrier layer between the source / drain and the gate.

2. The enhancement mode high voltage HEMT device according to claim 1, It is characterized in that The multi-finger buried gate structure is formed by an ion implantation process.

3. The enhancement mode high voltage HEMT device according to claim 2, It is characterized in that The thickness of the multi-finger buried gate structure is smaller than that of the barrier layer. The barrier layer is an n-type AlGaN layer, the Al component of which is 0.1-0.3 and the thickness is 30-50nm. The doping concentration of the multi-finger buried gate structure is greater than or equal to 10 8 cm -3 , thickness is 10~30nm.

4. The enhancement mode high voltage HEMT device according to claim 1, 2 or 3, It is characterized in that The gate dielectric layer is made of HfO 2 、Al 2 O 3 、TiO 2 or SiO 2 , and its thickness is 5~10nm.

5. The enhancement mode high voltage HEMT device according to claim 1, 2 or 3, It is characterized in that The channel layer is a GaN channel layer with a thickness of 50-70 nm; the insertion layer is an AlN insertion layer with a thickness of 1-2 nm.

6. The enhancement mode high voltage HEMT device according to claim 5, It is characterized in that The thickness of the AlGaN barrier layer is selected to be 30 nm, and its Al composition is selected to be 0.

24.

7. The enhancement mode high voltage HEMT device according to claim 5, It is characterized in that The stress release layer is an AlN stress release layer; and the high resistance buffer layer is a GaN high resistance layer.

8. A method for preparing an enhanced high-voltage HEMT device with a multi-finger buried gate structure. It is characterized in that The following steps are involved: A stress release layer, a high resistance buffer layer, a channel layer, an insertion layer and a barrier layer are sequentially grown on the substrate; An ion implantation process is used to form a multi-finger buried gate structure of a certain depth in a predetermined area on the surface of the barrier layer, wherein the multi-finger buried gate structure comprises at least three p-type interdigitated buried gate units arranged at intervals in the direction from the source to the drain, and the width of the multi-finger buried gate structure in the direction from the source to the drain is equal to the width of the gate, and a PN junction arranged in sequence is formed between the multi-finger buried gate structure and the barrier layer; Depositing a gate dielectric layer on the surface of the multi-finger buried gate structure, followed by high temperature annealing; Etching the barrier layer to form source and drain regions, and depositing source and drain metals; forming a gate region on the gate dielectric layer and depositing a gate metal; A passivation layer is deposited to cover the region between the gate and the source, and to cover the region between the gate and the drain.

Images