Semiconductor structure and method for forming the same

Abstract

The present application discloses a semiconductor structure and a method for forming the same, the method comprising: providing a substrate, the substrate comprising a first region and a second region; forming a first gate dielectric material layer on the surface of the first region; forming an epitaxial layer on the surface of the second region, so that the absolute value of the height difference between the top of the epitaxial layer and the top of the first gate dielectric material layer is less than a first target threshold; and forming a second gate dielectric material layer on the surface of the epitaxial layer. The semiconductor structure and the method for forming the same disclosed in the present application improve the performance of the semiconductor structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In the semiconductor manufacturing process of 28nm and below, high voltage (HV) semiconductor devices may include low voltage (LV) devices as core devices and medium voltage (MV) devices that provide source drive. The higher the threshold voltage of the device, the greater the thickness of the gate dielectric layer. Therefore, the thickness of the gate dielectric layer of the medium voltage device is greater than the thickness of the gate dielectric layer of the low voltage device. In other words, when the channel heights of the medium voltage device and the low voltage device are the same, the top of the gate dielectric layer of the medium voltage device is higher than the top of the gate dielectric layer of the low voltage device. The height difference between the two increases the difficulty of subsequent processes.

[0003] Therefore, it is necessary to improve the existing process to enhance the performance of the semiconductor structure. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a semiconductor structure and a method for forming the same, so as to eliminate the height difference between the tops of the gate dielectric layers of semiconductor devices with different threshold voltages, thereby reducing the difficulty of subsequent processes.

[0005] One aspect of the present application provides a method for forming a semiconductor structure, which includes: providing a substrate, the substrate including a first region and a second region; forming a first gate dielectric material layer on the surface of the first region; selectively epitaxially growing (Epitaxial Growth) a substrate material on the surface of the second region to form an epitaxial layer, so that the absolute value of the height difference between the top of the epitaxial layer and the top of the first gate dielectric material layer is less than a first target threshold; and forming a second gate dielectric material layer on the surface of the epitaxial layer.

[0006] Optionally, the first target threshold is to

[0007] Optionally, the first target threshold is to

[0008] Optionally, the top of the epitaxial layer is flush with the top of the first gate dielectric material layer.

[0009] Optionally, an absolute value of a height difference between a top of the second gate dielectric material layer and a top of the first gate dielectric material layer is smaller than a second target threshold.

[0010] Optionally, the second target threshold is to

[0011] Optionally, the second target threshold is to

[0012] Optionally, the top of the second gate dielectric material layer is flush with the top of the first gate dielectric material layer. Optionally, the process of forming the second gate dielectric material layer on the surface of the epitaxial layer includes: performing oxidation treatment on the surface of the epitaxial layer.

[0013] Optionally, the process method for oxidizing the surface of the epitaxial layer includes: an in-situ water vapor generation process.

[0014] Optionally, the method also includes: forming a first gate material layer on the surface of the first gate dielectric material layer and the surface of the second gate dielectric material layer; etching the first gate material layer to form a first gate and a second gate; etching the first gate dielectric material layer and the second gate dielectric material layer respectively to form a first gate dielectric layer and a second gate dielectric layer; and forming a first source and a first drain in the first region, forming a second source and a second drain in the second region, the first source and the first drain are respectively located on both sides of the first gate dielectric layer, and the second source and the second drain are respectively located on both sides of the second gate dielectric layer.

[0015] Optionally, the method further includes: replacing the first gate and the second gate with a third gate and a fourth gate.

[0016] Optionally, replacing the first gate and the second gate by the third gate and the fourth gate includes: forming an interlayer dielectric layer, the top of the interlayer dielectric layer is higher than the top of the first gate and the top of the second gate; flattening the interlayer dielectric layer so that the top of the interlayer dielectric layer, the top of the first gate and the top of the second gate are flush; removing the first gate and the second gate to expose the top of the first gate dielectric layer, the top of the second gate dielectric layer and the sidewalls of the interlayer dielectric layer; forming a second gate material layer on the top of the first gate dielectric layer, the top of the second gate dielectric layer, the sidewalls and the top of the interlayer dielectric layer; and flattening the second gate material layer to form a third gate and a fourth gate, and making the top of the third gate and the top of the fourth gate flush with the top of the interlayer dielectric layer.

[0017] Optionally, the first gate and the second gate are made of silicon, and the third gate and the fourth gate are made of metal.

[0018] Another aspect of the present application provides a semiconductor structure, comprising: a substrate, the substrate comprising a first region and a second region, the top of the second region being higher than the top of the first region; a first gate dielectric layer, located on the surface of the first region; and a second gate dielectric layer, located on the surface of the second region, the absolute value of the height difference between the top of the second gate dielectric layer and the top of the first gate dielectric layer being less than a second target threshold.

[0019] Optionally, the second target threshold is to

[0020] Optionally, the second target threshold is to

[0021] Optionally, a top of the second gate dielectric material layer is flush with a top of the first gate dielectric material layer.

[0022] Optionally, the semiconductor structure also includes: a third gate, located on the surface of the first gate dielectric layer; a fourth gate, located on the surface of the second gate dielectric layer; a first source and a first drain, located in the first region and respectively located on both sides of the first gate dielectric layer; a second source and a second drain, located in the second region and respectively located on both sides of the second gate dielectric layer.

[0023] The technical solution of this application has the following beneficial effects:

[0024] If the top of the first gate dielectric layer is higher than the top of the second gate dielectric layer, the top of the first gate formed on the first gate dielectric layer is also higher than the top of the second gate formed on the second gate dielectric layer. As a result, in the process of planarizing the subsequently deposited interlayer dielectric layer in order to simultaneously expose the first gate and the second gate, if the planarization process is stopped when the first gate is exposed, the surface of the second gate may not be exposed, that is, there is still an interlayer dielectric layer remaining, so that the subsequent etching of the gate cannot be carried out normally; but if the planarization process is not stopped until the second gate is exposed, a part of the first gate may have been removed at this time, resulting in excessive consumption of the first gate, so that the thickness of the remaining first gate is insufficient to reach the target value, and there is even a risk of exposing the first gate dielectric, which not only causes a waste of materials, process time and resources, but more importantly, an overly thin first gate layer is very likely to cause leakage or breakdown during the subsequent device operation. In addition, the larger the gate size, the more serious the dishing problem caused by the planarization of the interlayer dielectric layer, which may cause the remaining first gate to be insufficiently thick in the dipping area, and then cause the subsequently formed metal gate to be insufficiently thick, ultimately causing leakage or breakdown, affecting the operating performance and reliability of the device, etc.

[0025] By means of the technical means of "forming an epitaxial layer on the surface of the second region, the absolute value of the height difference between the top of the epitaxial layer and the top of the first gate dielectric material layer is less than the first target threshold; and forming a second gate dielectric material layer on the surface of the epitaxial layer", the first gate dielectric layer and the second gate dielectric layer formed subsequently have substantially the same top height, and the first gate and the second gate formed on the first gate dielectric layer and the second gate dielectric layer also have substantially the same top height. Therefore, in the subsequent planarization process, the technical problems of the residual interlayer dielectric layer or the insufficient thickness of the first gate are avoided, which not only expands the window of the subsequent process, but also further improves the electrical performance and reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The following drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals represent similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of the present disclosure. Other embodiments may also accomplish the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Among them:

[0027] Figure 1A A schematic diagram of a cross-sectional structure of a semiconductor structure;

[0028] Figure 1B A schematic diagram of a cross-sectional structure of a semiconductor structure;

[0029] Figure 2 is a flow chart of a method for forming a semiconductor structure according to an embodiment of the present application;

[0030] FIG. 3A to FIG. 3L Schematic cross-sectional view of a semiconductor structure forming process according to an embodiment of the present application. DETAILED DESCRIPTION

[0031] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content in the present application. Various local modifications to the disclosed embodiments are obvious to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure is not limited to the embodiments shown, but to the widest scope consistent with the claims.

[0032] The technical solution of the present application is described in detail below with reference to the embodiments and drawings.

[0033] like Figure 1A and Figure 1B As shown, a semiconductor structure includes: a substrate 10, the substrate 10 includes a well region 20 and a first region 30, a second region 40 and a trench isolation structure (for example, including a liner oxide 52 and a dielectric filler 51) located in the well region 20, wherein the trench isolation structure is located between the first region 30 and the second region 40; a first gate dielectric layer 33 located on the surface of the first region 30, and a first source 31 and a first drain 32 located in the first region 30 and on both sides of the first gate dielectric layer 33; a second gate dielectric layer 43 located on the surface of the second region 40, and a second source 41 and a second drain 42 located in the second region 40 and on both sides of the second gate dielectric layer 43; a first gate 34 located on the surface of the first gate dielectric layer 33; a second gate 44 located on the surface of the second gate dielectric layer 43; and an inter-layer dielectric layer 70 (ILD, Inter-Layer Dielectric) located on the surface of the substrate 10, the surface and sidewalls of the first gate 34, and the surface and sidewalls of the second gate 44. It should be noted that the structure shown in the figure is only an exemplary structure. In other embodiments, the positions of the first source 31 and the first drain 32 can be interchanged, and the positions of the second source 41 and the second drain 42 can be interchanged.

[0034] The first region may be a medium voltage device region, and the first source 31, the first drain 32, the first gate dielectric layer 33 and the first gate 34 correspond to the medium voltage device, wherein the length of the first gate dielectric layer 33 is about 10-15 μm, and the thickness of the first gate dielectric layer 33 is about The second region may be a low voltage device region, and the second source 41, the second drain 42, the second gate dielectric layer 43 and the second gate 44 correspond to the low voltage device, wherein the length of the second gate dielectric layer 43 is about 1 to 5 μm, and the thickness of the second gate dielectric layer 43 is about As can be seen from the figure, when the channel heights of the medium voltage device and the low voltage device are the same, the top of the first gate dielectric layer 33 is higher than the top of the second gate dielectric layer 43 by The height difference between the first gate dielectric layer 33 and the second gate dielectric layer 43 increases the difficulty of subsequent processes.

[0035] Specifically, since the top of the first gate dielectric layer 33 is higher than the top of the second gate dielectric layer 43, when the channel heights of the medium voltage device and the low voltage device are the same, the top of the first gate 34 formed on the first gate dielectric layer 33 is also higher than the top of the second gate 44 formed on the second gate dielectric layer 43. Therefore, in the process of performing a planarization process on the subsequently deposited interlayer dielectric layer 70 to simultaneously expose the first gate 34 and the second gate 44, if the planarization process is stopped when the first gate 34 is exposed, the surface of the second gate 44 may not be fully exposed, that is, there is still an interlayer dielectric layer remaining, so that the subsequent etching of the gate cannot be performed normally; but if the planarization process is not stopped until the second gate 44 is exposed, a part of the first gate 34 may have been removed at this time, resulting in excessive consumption of the first gate 34, so that the thickness of the remaining first gate 34 is insufficient to reach the target value, and there is even a risk of exposing the first gate dielectric 33, which not only causes a waste of materials, process time and resources, but more importantly, an overly thin first gate layer 34 is very likely to cause leakage or breakdown during the subsequent device operation. In addition, as the gate size increases, the dishing problem caused by planarizing the interlayer dielectric layer 70 and the first gate 34 becomes more serious, which may result in insufficient thickness of the remaining first gate 34, thereby affecting the device's operating performance and reliability.

[0036] In order to solve the above problems, the present application provides a semiconductor structure and a method for forming the same, such as Figure 2 As shown, the method for forming the semiconductor structure includes the following steps:

[0037] Step S101: providing a substrate, wherein the substrate comprises a first region and a second region;

[0038] Step S102: forming a first gate dielectric material layer on a portion of the surface of the first region;

[0039] Step S103: selectively epitaxially growing a substrate material on the surface of the second region to form an epitaxial layer, so that an absolute value of a height difference between a top of the epitaxial layer and a top of the first gate dielectric material layer is less than a first target threshold;

[0040] Step S104: forming a second gate dielectric material layer on the surface of the epitaxial layer;

[0041] Step S105: forming a first gate material layer on the surface of the first gate dielectric layer and the surface of the second gate dielectric layer;

[0042] Step S106: etching the first gate material layer to form a first gate and a second gate, and respectively etching the first gate dielectric material layer and the second gate dielectric material layer to form a first gate dielectric layer and a second gate dielectric layer;

[0043] Step S107: forming a first source and a first drain in the first region and forming a second source and a second drain in the second region, wherein the first source and the first drain are respectively located on both sides of the first gate dielectric layer, and the second source and the second drain are respectively located on both sides of the second gate dielectric layer;

[0044] Step S108: forming an interlayer dielectric layer, wherein the top of the interlayer dielectric layer is higher than the top of the first gate and the top of the second gate;

[0045] Step S109: performing a planarization process on the interlayer dielectric layer so that the top of the interlayer dielectric layer, the top of the first gate and the top of the second gate are flush;

[0046] Step S110: removing the first gate and the second gate to expose the top of the first gate dielectric layer, the top of the second gate dielectric layer and the sidewall of the interlayer dielectric layer;

[0047] Step S111: forming a second gate material layer on the top of the first gate dielectric layer, the top of the second gate dielectric layer, and the sidewall and top of the interlayer dielectric layer;

[0048] Step S112: performing a planarization process on the second gate material layer to form a third gate and a fourth gate, and making the top of the third gate and the top of the fourth gate flush with the top of the interlayer dielectric layer.

[0049] Combine the following FIG. 3A to FIG. 3L The above steps are described in detail. It should be noted that methods that perform the above and following steps in other sequences also fall within the protection scope of the present disclosure.

[0050] like Figure 3A As shown, a substrate 100 is provided, and the substrate 100 includes a first region 300 and a second region 400 .

[0051] The material of the substrate 100 may be silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon on insulator (SOI), germanium on insulator (GOI), or other semiconductor materials, such as III-V compounds such as gallium arsenide (GaAs). The material of the substrate 100 may be polycrystalline silicon. The substrate 100 may also be a silicon on insulator structure or an epitaxial layer structure on silicon.

[0052] The substrate 100 may include a well region 200, which may be formed by injecting ions into the substrate 100 and play a role in protecting the circuit. The well region 200 may be a P-type well region or an N-type well region. The P-type well region may be formed by performing P-type doping in the substrate 200, and the impurity ions used for P-type doping may be one or more of various ions such as boron ions, indium ions, and gallium ions; the N-type well region may be formed by performing N-type doping in the substrate 100, and the impurity ions used for N-type may be one or more of various ions such as phosphorus ions, arsenic ions, and antimony ions. In this embodiment, the well region 200 is a low-concentration N-type deep well.

[0053] The substrate 100 may further include a first region 300 and a second region 400, and the first region 300 and the second region 400 may be located in the well region 200. The first region 300 may be a medium voltage device region, and the second region 400 may be a low voltage device region. The first region 300 may be formed by doping in the well region 200. The doping type of the first region 300 may be the same as or opposite to the doping type of the well region 200. The doping concentration of the first region 300 may be higher than the doping concentration of the well region 200. The second region 400 may be formed by doping in the well region 200. The doping type of the second region 400 may be the same as or opposite to the doping type of the well region 200. The doping concentration of the second region 400 may be higher than the doping concentration of the well region 200.

[0054] The substrate 100 may further include a trench isolation structure, which may include a liner oxide 520 and a filler 510. Both the liner oxide 520 and the filler 520 may be oxides, for example, silicon oxide. The liner oxide 520 may be formed by an atomic layer deposition (ALD) process, an oxidation treatment process, an in-situ steam generation (ISSG) process, etc.; the filler 520 may be formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin coating (SOC) process, a sputtering process, etc. The trench isolation structure may be located between the first region 300 and the second region 400.

[0055] like Figure 3B As shown, a first gate dielectric material layer 330 is formed on the surface of the substrate 100 in the first region 300 .

[0056] The first gate dielectric material layer 330 may include silicon oxide, silicon oxynitride (SiON) or other high dielectric constant (i.e., K value ≥ 3.9) materials, such as hafnium dioxide (HfO2), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), titanium oxide (TiO2), etc. The first gate dielectric material layer 330 may be formed on the surface of the first region 300 by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, an oxidation treatment process, an in-situ steam generation (ISSG) process, etc. The process steps and methods for forming the first gate dielectric material layer 330 on the surface of the substrate 100 in the first region 300 may include: first, forming the first gate dielectric material layer 330 on a portion of the surface of the substrate 100 (e.g., the surface of the first region 300, the surface of the second region 400, and the surface of the trench isolation structure), and then removing (e.g., by dry etching or wet etching) the first gate dielectric material layer 330 located on the surface of the second region 400 and the surface of the trench isolation structure. In this embodiment, the first region 300 may correspond to the medium voltage device region, and the thickness of the first gate dielectric material layer 330 may be to Those skilled in the art should understand that the thickness of the first gate dielectric material layer 330 is not limited to the numerical range disclosed herein, and other thicknesses of the first gate dielectric material layer 330 are also possible.

[0057] like Figure 3C As shown, the substrate material is selectively epitaxially grown on the surface of the second region 400 to form an epitaxial layer 401 , so that the absolute value of the height difference between the top of the epitaxial layer 401 and the top of the first gate dielectric material layer 330 is less than the first target threshold.

[0058] In this embodiment, the absolute value of the height difference between the top of the epitaxial layer 401 and the top of the first gate dielectric material layer 330 is less than or equal to In this embodiment, the top of the epitaxial layer 401 is equal to or lower than the top of the first gate dielectric material layer 330. In some embodiments, the top of the epitaxial layer 401 is higher than the top of the first gate dielectric material layer 330. In other embodiments, the range of the first target threshold value can be to Preferably, to More preferably, to For example, the first target threshold may be or wait.

[0059] The substrate material (eg, silicon) can be selectively epitaxially grown on the surface of the second region 400 to increase the top height of the second region 400 to form an epitaxial layer 401. In this embodiment, the height of the epitaxial layer 401 is to For example, In other embodiments, the height of the epitaxial layer 401 may be to The substrate material is formed by selective epitaxial growth, without adding additional photolithography processes and masks, thus saving time and process costs. In some embodiments, the top of the epitaxial layer 401 is lower than the top of the first gate dielectric material layer 330. In some embodiments, the top of the epitaxial layer 401 is substantially flush with the top of the first gate dielectric material layer 330. In some embodiments, the epitaxial layer 401 can also be formed on the surface of the second region 400 by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD) and other processes.

[0060] like Figure 3D As shown, a second gate dielectric material layer 430 is formed on the surface of the epitaxial layer 401 .

[0061] The material of the second gate dielectric material layer 430 may include silicon oxide, hafnium dioxide or other high-K materials. The process method for forming the second gate dielectric material layer 430 on the surface of the epitaxial layer 401 includes: oxidizing the surface of the epitaxial layer 401. The surface of the second region may be oxidized by an in-situ steam generation (ISSG) process to form the second gate dielectric material layer 430 (for example, silicon oxide). The ISSG process is a process for growing an oxide layer in a high-temperature water vapor atmosphere. The speed of growing the oxide layer is relatively fast, and the thickness and uniformity of the oxide layer growth can be precisely controlled. In the present embodiment, the second region 400 may correspond to a low-voltage device region, and the thickness of the second gate dielectric material layer 430 may be to For example Those skilled in the art should understand that the thickness of the second gate dielectric material layer 430 is not limited to the numerical range disclosed herein, and other thicknesses of the second gate dielectric material layer 430 are also possible.

[0062] The height difference between the top of the second gate dielectric material layer 430 and the top of the first gate dielectric material layer 330 may be less than the second target threshold. The range of the second target threshold may be to Preferably, to More preferably, to For example, the first target threshold may be or In this embodiment, the top of the second gate dielectric material layer 430 is substantially flush with the top of the first gate dielectric material layer 330. In other embodiments, the top of the second gate dielectric material layer 430 may also be higher or lower than the top of the first gate dielectric material layer 330, depending on the positional relationship between the top of the epitaxial layer 401 and the top of the first gate dielectric material layer 330.

[0063] like Figure 3E As shown, a first gate material layer 800 is formed on the surface of the first gate dielectric material layer 330 and the surface of the second gate dielectric material layer 430 .

[0064] The first gate material layer 800 may be silicon, for example, polycrystalline silicon (Poly-Si), amorphous silicon (a-Si), or single crystal silicon (c-Si). For example, a polycrystalline silicon layer may be deposited on the surface of the first gate dielectric material layer 330 and the surface of the second gate dielectric material layer 430 by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. In some embodiments, the first gate material layer 800 also covers the surface of the trench isolation structure.

[0065] like Figure 3F As shown, the first gate material layer 800 is etched to form a first gate 340 and a second gate 440 , and the first gate dielectric material layer 330 and the second gate dielectric material layer 430 are etched to form a first gate dielectric layer 331 and a second gate dielectric layer 431 .

[0066] For example, the first gate 340 and the second gate 440 may be formed by dry etching or wet etching. For example, the first gate 340 and the second gate 440 may be dummy gates.

[0067] The first gate dielectric layer 331 and the second gate dielectric layer 431 may be formed by dry etching or wet etching.

[0068] like Figure 3G As shown, a first source 310 and a first drain 320 are formed in the first region 300, and a second source 410 and a second drain 420 are formed in the second region 400. The first source 310 and the first drain 320 are respectively located on both sides of the first gate dielectric layer 330, and the second source 410 and the second drain 420 are respectively located on both sides of the second gate dielectric layer 430.

[0069] The first source 310 and the first drain 320 may be formed by injecting impurity ions into the first region 300. The second source 410 and the second drain 420 may be formed by injecting impurity ions into the second region 400. It should be noted that the first source 310, the first drain 320, the second source 410 and the second drain 420 shown in the figure are only exemplary structures. In other embodiments, the positions of the first source 310 and the first drain 320 may be interchanged, and the positions of the second source 410 and the second drain 420 may be interchanged.

[0070] like Figure 3H As shown, an interlayer dielectric layer 700 is formed, and the top of the interlayer dielectric layer 700 is higher than the top of the first gate 340 and the top of the second gate 440 .

[0071] The material of the interlayer dielectric layer 700 may include silicon nitride or silicon oxide. The interlayer dielectric layer 700 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), spin coating (SOC) and other processes. In some embodiments, the interlayer dielectric layer 700 may also cover the surface of the trench isolation structure, a portion of the surface of the first region 300, the sidewall of the first gate dielectric layer 331, the sidewall of the second gate dielectric layer 431, and the top of the epitaxial layer 401.

[0072] like Fig. 3I As shown, the interlayer dielectric layer 700 is planarized so that the top of the interlayer dielectric layer 700 , the top of the first gate 340 , and the top of the second gate 440 are flush.

[0073] In this embodiment, the planarization process is chemical-mechanical polishing (CMP).

[0074] like Figure 3J As shown, the first gate 340 and the second gate 440 are removed to expose the top of the first gate dielectric layer 331 , the top of the second gate dielectric layer 431 and the sidewall of the interlayer dielectric layer 700 .

[0075] For example, the first gate 340 and the second gate 440 may be removed by dry etching or wet etching. In some embodiments, only the second gate 440 may be removed, while the first gate 340 is retained.

[0076] like Figure 3K As shown, a second gate material layer 900 is formed on the top of the first gate dielectric layer 331 , on the top of the second gate dielectric layer 431 , and on the sidewall and top of the interlayer dielectric layer 700 .

[0077] The second gate material layer 900 may include metal, such as tantalum or tungsten. For example, the second gate material layer 900 may be formed by physical vapor deposition, chemical vapor deposition, atomic layer deposition, or the like.

[0078] In the embodiment where the first gate 340 is retained, the second gate material layer 900 is formed on the surface of the first gate 340 , the surface of the second gate dielectric layer 431 , and the sidewall and top of the interlayer dielectric layer 700 .

[0079] like Figure 3L As shown, the second gate material layer 900 is planarized to form a third gate 341 and a fourth gate 441 , and the top of the third gate 341 and the top of the fourth gate 441 are flush with the top of the interlayer dielectric layer 700 .

[0080] In this embodiment, the planarization process is chemical mechanical polishing.

[0081] In the embodiment where the first gate 340 is retained, the second gate material layer 900 is planarized to expose the first gate 340 and form the fourth gate 441 , and to make the top of the first gate 340 and the top of the fourth gate 441 flush with the top of the interlayer dielectric layer 700 .

[0082] In the embodiment of the present application, by making the top of the second gate dielectric material layer 430 substantially flush with the top of the first gate dielectric material layer 330, the first gate dielectric layer 331 and the second gate dielectric layer 431 formed subsequently can have substantially the same top height, and thus the first gate 340 and the second gate 440 formed subsequently on the first gate dielectric layer 331 and the second gate dielectric layer 431 also have substantially the same top height. Therefore, in the planarization process, the interlayer dielectric layer 700 is avoided from remaining. In addition, the first gate 340 will not be removed in large quantities in the planarization process in order to take into account the second gate 440 with a lower top height, thereby causing insufficient remaining gate thickness when the recess effect occurs, and even exposing the first gate dielectric layer 331. In addition, the third gate 341 and the fourth gate 441 formed subsequently will not lack sufficient remaining thickness in the planarization process due to the influence of the recess effect. Therefore, the semiconductor structure and the formation method thereof of the present application can effectively improve the performance of semiconductor devices.

[0083] An embodiment of the present application also provides a semiconductor structure, which includes: a substrate 100, the substrate 100 includes a first region 300 and a second region 400, the top of the second region 400 is higher than the top of the first region 300; a first gate dielectric layer 331, located on the surface of the first region 300; and a second gate dielectric layer 431, located on the surface of the second region 400, the height difference between the top of the second gate dielectric layer 431 and the top of the first gate dielectric layer 331 is less than a second target threshold.

[0084] The semiconductor structure may also include: a third gate 341, the third gate 341 is located on the surface of the first gate dielectric layer 331; a fourth gate 441, the fourth gate 441 is located on the surface of the second gate dielectric layer 431; a first source 310 and a first drain 320, which are located in the first region 300 and are respectively located on both sides of the first gate dielectric layer 331; a second source 410 and a second drain 420, which are located in the second region 400 and are respectively located on both sides of the second gate dielectric layer 431.

[0085] In summary, after reading this detailed disclosure, it will be apparent to those skilled in the art that the foregoing detailed disclosure may be presented only by way of example and may not be limiting. Although not explicitly stated herein, it will be appreciated by those skilled in the art that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are intended to be proposed by this disclosure and are within the spirit and scope of the exemplary embodiments of this disclosure.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate, the substrate comprising a first region and a second region; forming a first gate dielectric material layer on the surface of the first region; A substrate material is selectively epitaxially grown on the surface of the second region to form an epitaxial layer, so that an absolute value of a height difference between a top of the epitaxial layer and a top of the first gate dielectric material layer is less than a first target threshold value, wherein the first target threshold value is to as well as A second gate dielectric material layer is formed on the surface of the epitaxial layer, wherein the absolute value of the height difference between the top of the second gate dielectric material layer and the top of the first gate dielectric material layer is less than a second target threshold value, and the second target threshold value is to 2. The method according to claim 1, characterized in that The first target threshold is to 3. The method according to claim 2, characterized in that The top of the epitaxial layer is flush with the top of the first gate dielectric material layer.

4. The method according to claim 1, characterized in that: The second target threshold is to 5. The method according to claim 4, characterized in that The top of the second gate dielectric material layer is flush with the top of the first gate dielectric material layer.

6. The method according to claim 1, characterized in that The process of forming a second gate dielectric material layer on the surface of the epitaxial layer comprises: The surface of the epitaxial layer is subjected to oxidation treatment.

7. The method according to claim 6, characterized in that The process method for oxidizing the surface of the epitaxial layer includes: an in-situ water vapor generation process.

8. The method according to claim 1, characterized in that: Also includes: forming a first gate material layer on the surface of the first gate dielectric material layer and the surface of the second gate dielectric material layer; Etching the first gate material layer to form a first gate and a second gate; Etching the first gate dielectric material layer and the second gate dielectric material layer respectively to form a first gate dielectric layer and a second gate dielectric layer; as well as A first source and a first drain are formed in the first region, and a second source and a second drain are formed in the second region, the first source and the first drain are respectively located on both sides of the first gate dielectric layer, and the second source and the second drain are respectively located on both sides of the second gate dielectric layer.

9. The method according to claim 8, characterized in that Also includes: The first gate and the second gate are replaced by a third gate and a fourth gate.

10. The method according to claim 9, characterized in that Replacing the first gate and the second gate with a third gate and a fourth gate includes: forming an interlayer dielectric layer, wherein a top of the interlayer dielectric layer is higher than a top of the first gate and a top of the second gate; performing a planarization process on the interlayer dielectric layer so that the top of the interlayer dielectric layer, the top of the first gate and the top of the second gate are flush; Removing the first gate and the second gate to expose the top of the first gate dielectric layer, the top of the second gate dielectric layer and the sidewall of the interlayer dielectric layer; forming a second gate material layer on the top of the first gate dielectric layer, the top of the second gate dielectric layer, and the sidewall and top of the interlayer dielectric layer; and The second gate material layer is planarized to form a third gate and a fourth gate, and the top of the third gate and the top of the fourth gate are flush with the top of the interlayer dielectric layer.

11. The method according to claim 9, characterized in that The first gate and the second gate are made of silicon, and the third gate and the fourth gate are made of metal.

12. A semiconductor structure, characterized in that: Formed by the method of any one of claims 1 to 11, comprising: A substrate, the substrate comprising a first region and a second region, wherein a top of the second region is higher than a top of the first region; A first gate dielectric layer, located on the surface of the first region; and A second gate dielectric layer is located on the surface of the second region, and an absolute value of a height difference between a top of the second gate dielectric layer and a top of the first gate dielectric layer is less than a second target threshold value. The second target threshold value is to 13. The semiconductor structure according to claim 12, characterized in that: The second target threshold is to 14. The semiconductor structure according to claim 13, characterized in that: The top of the second gate dielectric layer is flush with the top of the first gate dielectric layer.

15. The semiconductor structure according to claim 12, characterized in that: Also includes: A third gate, located on a surface of the first gate dielectric layer; a fourth gate, located on a surface of the second gate dielectric layer; A first source electrode and a first drain electrode are located in the first region and are respectively located on two sides of the first gate dielectric layer; as well as The second source and the second drain are located in the second region and are respectively located on two sides of the second gate dielectric layer.

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