Semiconductor device and method for manufacturing the same

Abstract

The invention discloses a semiconductor device and a method for preparing the same. The semiconductor device formed by the preparation method of the embodiment of the invention can not only avoid gate metal migration and improve device yield, but also ensure that the side walls of the gate structure are flat and free of deformation, thereby improving the reliability of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] In the prior art, as the gate size becomes smaller and smaller, the distance between the source and drain regions of the metal oxide semiconductor field effect transistor (MOSFET) becomes shorter and shorter, and the device is prone to short channel effect (Short Channel Effect) and hot carrier effect (Hot Carrier Effect), which in turn causes the device to fail to operate. In order to improve the above problems, the source / drain design of the existing micron-level and below-level MOSFET devices will adopt a lightly doped drain (LDD) structure, that is, a low-doped region with a shallow depth and the same doping type as the source / drain region is formed under the gate structure adjacent to the source / drain region to reduce the electric field in the channel region and thus avoid the occurrence of short channel effect and hot carrier effect. In the existing mainstream technology, before forming the LDD structure, atomic layer deposition (ALD) is used to form an insulating layer on the surface of the metal / polysilicon gate. Atomic layer deposition is a thin film deposition method based on an ordered, self-saturated surface reaction. The self-limited growth of the thin film is achieved through alternating saturated surface reactions, and the material is plated layer by layer on the substrate surface in the form of a single atomic film. Compared with physical vapor deposition (PVD) and chemical vapor deposition (CVD), ALD deposition has a slower reaction rate, better film uniformity and film coverage, and is more suitable for graphics with particularly high film uniformity requirements. Although the film uniformity of ALD deposition will be better, there is still a big gap with the ideal requirements, especially the difference in growth rate on the surface of different substrate materials, which has always been a bottleneck restricting the development of ALD technology. In the atomic layer deposition process of the gate insulation layer, due to the difference in growth rate on the surface of the conductive layer and the passivation layer of the gate structure, there is a difference in the thickness of the insulating layer film, resulting in an abnormal sidewall profile of the gate structure. The thickness of the top of the gate structure is greater than the thickness at the bottom to form a "T"-shaped structure. In the subsequent LDD structure formation process, the "T"-shaped structure has a wider top thickness, which blocks ion implantation and causes an abnormal LDD structure at the bottom. In addition, with the continuous improvement of the integration of semiconductor devices, the thickness of the gate insulation layer continues to decrease, which makes the gate prone to metal migration and device displacement, thereby causing a loss in the yield of semiconductor devices. How to solve this problem in the process has also become a major challenge. Summary of the invention

[0003] The object of the present invention is to provide a method for preparing a semiconductor device, which can avoid the migration of gate metal materials, ensure the uniformity of the gate insulation layer, and improve the product yield.

[0004] According to an embodiment of the present invention, a method for preparing a semiconductor device includes: providing a semiconductor substrate, sequentially forming a gate dielectric layer, a first conductive layer and a support layer with a through hole on the semiconductor substrate; forming a barrier layer and a second conductive layer in the through hole of the support layer, wherein the barrier layer is formed between the support layer and the second conductive layer and covers the inner wall surface of the through hole; removing the support layer and a portion of the first conductive layer below the support layer to form a primary gate pattern and expose the gate dielectric layer; forming the gate sidewall protection layer together with the side wall of the primary gate pattern; forming a gate insulating layer on the top of the primary gate pattern, the surface of the gate sidewall protection layer and the exposed surface of the gate dielectric layer; removing a portion of the insulating layer and a portion of the gate dielectric layer, the insulating layer formed on the top of the primary gate pattern and the surface of the gate sidewall protection layer is retained, and the primary gate pattern, the gate sidewall protection layer and the gate dielectric layer covered by the insulating layer on the surface of the gate sidewall protection layer are retained.

[0005] According to some embodiments of the present invention, in the step of forming the barrier layer and the second conductive layer in the through hole, wherein the barrier layer is formed between the supporting layer and the second conductive layer and covers the inner wall surface of the through hole, the following steps are included: depositing the barrier layer on the surface of the supporting layer and in the through hole; depositing the second conductive layer on the surface of the barrier layer; removing part of the second conductive layer and the barrier layer, and retaining the second conductive layer and the barrier layer located in the through hole.

[0006] According to some embodiments of the present invention, the step of forming a gate sidewall protection layer includes the following steps: performing plasma treatment on the primary gate pattern to form a first protection layer on the sidewall of the first conductive layer and a second protection layer on the sidewall of the barrier layer.

[0007] Optionally, the step of performing plasma treatment on the sidewalls of the preliminary gate pattern includes: performing nitrogen and oxygen mixed plasma treatment on the sidewalls of the preliminary gate pattern.

[0008] The invention also provides a semiconductor device.

[0009] According to an embodiment of the present invention, a semiconductor device includes: a semiconductor substrate, on which a gate dielectric layer is formed; the gate structure is formed on the gate dielectric layer, and the gate structure includes a first conductive layer, a barrier layer, a gate sidewall protection layer, a second conductive layer and an insulating layer arranged in sequence, the barrier layer wraps the bottom surface and the side surface of the second conductive layer, and the insulating layer is formed on the surface of the gate sidewall protection layer and on the top of the second conductive layer and the barrier layer.

[0010] According to some embodiments of the present invention, the gate protection layer includes a first protection layer on the sidewall of the first conductive layer and a second protection layer on the sidewall of the barrier layer.

[0011] Optionally, the thickness of the first protective layer is 5 to 20 angstroms, and the thickness of the second protective layer is 3 to 10 angstroms.

[0012] Optionally, the side surfaces of the first protective layer and the second protective layer are flush.

[0013] According to some embodiments of the present invention, the side surface of the gate dielectric layer is flush with the side surface of the insulating layer on the side wall of the first protection layer and the side surface of the insulating layer on the side wall of the second protection layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A schematic diagram of a process for preparing a semiconductor device according to an embodiment of the present invention;

[0015] Figure 2-Figure 14 FIG. 4 is a process flow chart of a method for preparing a semiconductor structure according to an embodiment of the present invention.

[0016] Reference numerals

[0017] 1000: semiconductor devices;

[0018] 100: semiconductor substrate;

[0019] 200: gate dielectric layer;

[0020] 300: first conductive layer;

[0021] 400: support layer, 401: mask layer, 402: photoresist layer, 403: through hole;

[0022] 500: barrier layer;

[0023] 600: second conductive layer;

[0024] 700: insulation layer;

[0025] 900: gate sidewall protection layer, 901: second protection layer, 902: first protection layer. DETAILED DESCRIPTION

[0026] A semiconductor device and a method for manufacturing the same proposed by the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0027] A method for manufacturing a semiconductor device 1000 according to an embodiment of the present invention will be described below with reference to the accompanying drawings.

[0028] like Figure 1As shown, the method for preparing a semiconductor device 1000 according to an embodiment of the present invention may include the following steps: providing a semiconductor substrate 100, sequentially forming a gate dielectric layer 200, a first conductive layer 300 and a support layer 400 having a through hole 403 on the semiconductor substrate 100; forming a barrier layer 500 and a second conductive layer 600 in the through hole 403 of the support layer 400, wherein the barrier layer 500 is formed between the support layer 400 and the second conductive layer 600 and covers the inner wall surface of the through hole 403; removing the support layer 400 and a portion of the first conductive layer 300 located below the support layer 400; and removing the barrier layer 500 from the support layer 400. , forming a primary gate pattern, exposing the gate dielectric layer 200; forming a gate sidewall protection layer on the surface sidewall of the primary gate pattern; forming an insulating layer 700 on the top of the primary gate pattern, the surface of the gate sidewall protection layer 900 and the exposed surface of the gate dielectric layer 200; removing part of the insulating layer 700 and part of the gate dielectric layer 200, the insulating layer 700 formed on the top of the primary gate pattern and the surface of the gate sidewall protection layer 900 is retained, and the primary gate pattern, the gate sidewall protection layer 900 and the gate dielectric layer 200 covered by the insulating layer 700 on the surface of the gate sidewall protection layer 900 are retained.

[0029] Figure 2-Figure 14 is a process flow chart of an embodiment of a method for preparing a semiconductor device 1000 of the present invention, and the following is a reference to the attached Figure 2-Figure 14 A method for manufacturing a semiconductor device 1000 according to an embodiment of the present invention is described.

[0030] like Figure 7 As shown, a gate dielectric layer 200, a first conductive layer 300 and a support layer 400 with through holes are sequentially formed on a semiconductor substrate 100 from bottom to top. The semiconductor substrate 100 may be made of silicon (Si), germanium (Ge), silicon germanium (GeSi), or silicon carbide (SiC); or silicon on insulator (SOI), germanium on insulator (GOI); or other materials, such as III-V compounds such as gallium arsenide. Devices may also be provided on the semiconductor substrate 100.

[0031] The gate dielectric layer 200 may be made of silicon oxide, germanium oxide or a material with a high dielectric constant, etc., wherein the gate dielectric layer 200 may be formed on the semiconductor substrate 100 by methods such as thermal oxidation or chemical vapor deposition. The first conductive layer 300 is formed on the upper surface of the gate dielectric layer 200, and the first conductive layer 300 may be formed on the gate dielectric layer 200 by processes such as chemical vapor deposition (CVD), and the material thereof may be a conductive material containing silicon.

[0032] As for the method of forming the through hole 403, Figure 2-Figure 7As shown, the step of forming a support layer 400 having a through hole 403 may include the following steps: forming a support layer 400, a mask layer 401 and a photoresist layer 402 on the first conductive layer 300; patterning the photoresist layer 402, and removing the photoresist layer 402 in the area where a primary gate pattern needs to be formed; transferring the pattern of the photoresist layer 402 to the mask layer 401 to form a patterned mask layer 401; using the mask layer 401 as a mask, removing part of the support layer 400; removing the mask layer 401 and the photoresist layer 402 to form a support layer 400 having a through hole 403.

[0033] Specifically, Figure 2-Figure 3 As shown, a support layer 400 covering the upper surface of the first conductive layer 300 is formed above the first conductive layer 300, and a mask layer 401 and a photoresist layer 402 can be formed above the support layer 400, wherein the mask layer 401 may include silicon oxynitride of a dielectric anti-reflection coating (DARC) and an amorphous carbon (aC) layer as a pattern layer. In some specific embodiments, a bottom anti-reflection coating (BARC) and a photoresist layer (PR) can be deposited above the mask layer 401. The photoresist layer 402 is formed on the bottom anti-reflection coating.

[0034] like Figure 4 As shown, the patterned photoresist layer 402, the area where the primary gate pattern needs to be formed is removed, that is, the area where the through hole 403 needs to be formed is removed; Figure 5 As shown, the pattern of the photoresist layer 402 is transferred to the mask layer 401 to form a patterned mask layer 401. Figure 6 As shown, the mask layer 401 is used as a mask to remove the portion of the support layer 400 not blocked by the mask layer 401, and the portion of the support layer 400 blocked by the mask layer 401 is retained. Figure 7 As shown, the remaining mask layer 401 and the remaining photoresist layer 402 are removed to form a through hole 403 in the support layer 400 to expose the first conductive layer 300 .

[0035] like Figure 8-Figure 10 As shown, a barrier layer 500 and a second conductive layer 600 are formed in the through hole 403 of the support layer 400. The barrier layer 500 is formed between the support layer 400 and the second conductive layer 600 and covers the inner wall surface of the through hole 403. In this way, the second conductive layer 600 is partially wrapped by the barrier layer 500, which not only blocks the migration of the metal material of the second conductive layer 600, but also helps to protect the gate and avoid deformation of the gate structure due to high temperature, oxidation, aging and other factors.

[0036] Specific as Figure 8 As shown, a barrier layer 500 is deposited on the surface of the support layer 400 and in the through hole 403. Optionally, the barrier layer 500 may be a titanium-containing material layer such as a titanium nitride layer, etc., and the deposition method may be a chemical vapor deposition process; Fig. 9 As shown, a second conductive layer 600 is deposited on the surface of the barrier layer 500. In this step, the second conductive layer 600 can be deposited on the surface of the barrier layer 500 by chemical vapor deposition or physical vapor deposition, wherein the second conductive layer 600 can be a tungsten-containing material layer such as a metal tungsten layer; Fig.10 As shown, part of the second conductive layer 600 and part of the barrier layer 500 are removed, and the second conductive layer 600 and the barrier layer 500 located in the through hole 403 are retained. Specifically, in this step, the second conductive layer 600 and the barrier layer 500 that exceed the upper surface of the support layer 400 are removed, and the second conductive layer 600 and the barrier layer 500 located in the through hole 403 are retained, and the barrier layer 500 covers the inner wall surface of the through hole 403 and wraps the side and bottom surfaces of the second conductive layer 600.

[0037] like Fig.11 As shown, the support layer 400 and a portion of the first conductive layer 300 located below the support layer 400 are removed to form a primary gate pattern, exposing the gate dielectric layer 200. Optionally, an anisotropic etching method may be used to remove the support layer 400 and a portion of the first conductive layer 300 in this step, whereby the anisotropic etching method may be used to control the etching direction, and the support layer 400 and a portion of the first conductive layer 300 shielded by the support layer 400 may be removed in the up and down directions.

[0038] like Fig.12 As shown, a gate sidewall protection layer 900 is formed on the sidewall of the primary gate pattern. Fig.13 As shown, an insulating layer 700 is formed on the top of the primary gate pattern, the surface of the gate sidewall protection layer 900 and the surface of the exposed gate dielectric layer 200, as shown in FIG. Fig.14 As shown, part of the insulating layer 700 and part of the gate dielectric layer 200 are removed, the insulating layer 700 formed on the top of the primary gate pattern and the surface of the gate sidewall protection layer 900 is retained, and the primary gate pattern, the gate sidewall protection layer 900 and the gate dielectric layer 200 covered by the insulating layer 700 on the surface of the gate sidewall protection layer 900 are retained.

[0039] In some embodiments of the present invention, Fig.12As shown, the step of forming the gate sidewall protection layer 900 may include the following steps: plasma treatment is performed on the primary gate pattern to form a first protection layer 902 on the side wall of the first conductive layer 300, and a second protection layer 901 is formed on the side wall of the barrier layer 500, and the first protection layer 902 and the second protection layer 901 together constitute the gate sidewall protection layer 900. The protective layer 900 is formed on the side of the primary gate structure by plasma treatment, which is not only conducive to the protection of the side wall, but also can further improve the problem of uniformity of the gate sidewall insulation layer in the subsequent deposition of the insulation layer 700, ensure that the insulation layer on the surface of the first protection layer 902 and the insulation layer on the surface of the second protection layer 901 are flush, avoid forming a "T" structure, and ensure that the device structure is normal. Further, the step of plasma treatment of the side wall of the primary gate pattern is an in-situ plasma treatment, that is, plasma treatment is directly performed in the process chamber where the primary gate pattern is formed. It can avoid long-term exposure of the primary gate pattern formed subsequently, and prevent the side wall of the primary gate pattern from being oxidized and causing deformation of the gate structure.

[0040] Optionally, the step of performing plasma treatment on the sidewall of the primary gate pattern is: performing nitrogen and oxygen mixed plasma treatment on the sidewall of the primary gate pattern. The proportion of nitrogen is greater than the proportion of oxygen, that is, in a certain volume of mixed gas, the content of nitrogen is greater than the content of oxygen. For example, the barrier layer 500 can be made of a material containing titanium, the first conductive layer 300 can be a conductive layer containing silicon, and the plasma can be a mixture of nitrogen and oxygen. Thus, through the plasma reaction, a second protective layer 901 containing nitrogen, oxygen, and titanium elements can be formed on the sidewall of the barrier layer 500, and a first protective layer 902 containing nitrogen, oxygen, and silicon elements can be formed on the sidewall of the first conductive layer 300, wherein the first protective layer 902 and the second protective layer 901 both contain a large amount of nitrogen and oxygen elements. When the insulating layer 700 is subsequently deposited, since the material elements of the first protective layer 902 and the second protective layer 901 are similar, the insulating layer 700 deposited on the surface of the first protective layer 902 and the second protective layer 901 can be ensured to have good uniformity.

[0041] Furthermore, in the plasma treatment step, the plasma treatment time is 20s to 60s, the flow rate of nitrogen is 200sccm to 800sccm, and the flow rate of oxygen is 50sccm to 400sccm, and the temperature of plasma treatment is 20 to 80°C.

[0042] The semiconductor device 1000 according to an embodiment of the present invention is described below with reference to the accompanying drawings. The semiconductor device 1000 can be manufactured by the method for manufacturing the semiconductor device of the above embodiment.

[0043] like Fig.14As shown, a semiconductor device 1000 according to an embodiment of the present invention may include a semiconductor substrate 100 and a gate structure.

[0044] Specifically, the gate dielectric layer 200 covers part of the upper surface of the semiconductor substrate 100, wherein the material of the semiconductor substrate 100 may be silicon (Si), germanium (Ge), silicon germanium (GeSi), or silicon carbide (SiC); it may also be silicon on insulator (SOI), germanium on insulator (GOI); or it may also be other materials, such as III-V compounds such as gallium arsenide. Devices may also be arranged on the semiconductor substrate 100. The gate dielectric layer 200 material may be silicon oxide, germanium oxide or a material with a high dielectric constant, wherein the gate dielectric layer 200 may be formed on the semiconductor substrate 100 by methods such as thermal oxidation or chemical vapor deposition.

[0045] The gate structure is formed on the gate dielectric layer 200, and the gate structure includes a first conductive layer 300, a barrier layer 500, a gate sidewall protection layer 900, a second conductive layer 600 and an insulating layer 700 arranged in sequence, and the barrier layer 500 wraps the bottom and side surfaces of the second conductive layer 600. Fig.14 In the cross section of the semiconductor device 1000 shown, the barrier layer 500 can be formed into a U-shaped structure, and the second conductive layer 600 is filled and formed in the barrier layer 500, so that the barrier layer 500 wraps the second conductive layer 600, thereby avoiding the migration of the second conductive layer 600 material and avoiding the oxidation of the side of the second conductive layer 600 to cause abnormal gate structure.

[0046] As for the material of the blocking layer 500, the blocking layer 500 can be formed of a titanium-containing material such as titanium nitride, and the second conductive layer 600 can be a tungsten-containing material layer such as a metal tungsten layer. The blocking layer 500 can prevent tungsten migration, ensure the normal gate structure, further avoid device displacement, and ensure device reliability.

[0047] The insulating layer 700 is formed on the surface of the gate sidewall protection layer 900 and the top of the second conductive layer 600 and the barrier layer 500. Specifically, the gate sidewall protection layer 900 includes a second protection layer 901 formed on the sidewall of the barrier layer 500 after plasma treatment and a first protection layer 902 formed on the sidewall of the first conductive layer 300. The first protection layer 902 covers the side of the first conductive layer 300, and the second protection layer 901 covers the side of the barrier layer 500. The plasma treatment of the barrier layer 500 and the first conductive layer 300 can be carried out using a mixture of nitrogen and oxygen. The first conductive layer 300 can be made of a conductive material containing silicon. In this way, the plasma reaction of the sidewall of the first conductive layer 300 can form a first protection layer 902 containing nitrogen, oxygen and silicon. The barrier layer 500 can be formed of titanium nitride, a titanium-containing material. The plasma reaction of the sidewall of the barrier layer 500 can form a second protection layer 901 containing nitrogen, oxygen and titanium.

[0048] Furthermore, the sides of the first protective layer 902 and the second protective layer 901 are flush, and the sides of the gate dielectric layer 200 can be flush with the sides of the insulating layer 700 on the side walls of the first protective layer 902 and the sides of the insulating layer 700 on the side walls of the second protective layer 901. As a result, the sides of the gate structure form a flat structure without any unevenness, which can greatly improve the reliability of the semiconductor device.

[0049] Furthermore, the thickness of the first protective layer 902 is 5 to 20 angstroms, and the thickness of the second protective layer 901 is 3 to 10 angstroms. If the thickness of the first protective layer 902 and the second protective layer 901 is too thin, the purpose of preventing the oxidation of the device sidewalls cannot be achieved, and the uniformity of the insulating layer subsequently deposited on the sidewall protective layer cannot be guaranteed. If the thickness of the first protective layer 902 and the second protective layer 901 is too thick, the remaining thickness of the first conductive layer 300 and the barrier layer 500 will be too small, affecting the resistance of the gate and further affecting the performance of the device.

[0050] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: Providing a semiconductor substrate, and sequentially forming a gate dielectric layer, a first conductive layer, and a support layer having a through hole on the semiconductor substrate; forming a barrier layer and a second conductive layer in the through hole of the support layer, wherein the barrier layer is formed between the support layer and the second conductive layer and covers the inner wall surface of the through hole, and the material of the second conductive layer is metal; removing the support layer and a portion of the first conductive layer below the support layer to form a preliminary gate pattern and expose the gate dielectric layer; forming a gate sidewall protection layer on the sidewall of the primary gate pattern; forming an insulating layer on the top of the primary gate pattern, the surface of the gate sidewall protection layer and the exposed surface of the gate dielectric layer; Part of the insulating layer and part of the gate dielectric layer are removed, and the insulating layer formed on the top of the primary gate pattern and on the surface of the gate sidewall protection layer is retained, and the primary gate pattern, the gate sidewall protection layer and the gate dielectric layer covered by the insulating layer on the surface of the gate sidewall protection layer are retained.

2. The method for preparing a semiconductor device according to claim 1, wherein: The step of forming the barrier layer and the second conductive layer in the through hole, wherein the barrier layer is formed between the support layer and the second conductive layer and covers the inner wall surface of the through hole, comprises the following steps: Depositing a barrier layer on the surface of the support layer and in the through hole; Depositing a second conductive layer on the surface of the barrier layer; Part of the second conductive layer and the barrier layer is removed, and the second conductive layer and the barrier layer located in the through hole are retained.

3. The method for preparing a semiconductor device according to claim 1, characterized in that: The step of forming the gate sidewall protection layer includes the following steps: performing plasma treatment on the preliminary gate pattern to form a first protection layer on the sidewall of the first conductive layer and a second protection layer on the sidewall of the barrier layer.

4. The method for preparing a semiconductor device according to claim 3, characterized in that: The step of performing plasma treatment on the sidewalls of the preliminary gate pattern comprises: performing nitrogen and oxygen mixed plasma treatment on the sidewalls of the preliminary gate pattern.

5. The method for preparing a semiconductor device according to claim 4, characterized in that: The step of performing plasma treatment on the sidewall of the preliminary gate pattern is an in-situ plasma treatment.

6. A gate structure for preparing an LDD structure of a semiconductor device, characterized in that: The semiconductor device comprises: a semiconductor substrate, on which a gate dielectric layer is formed; The gate structure is formed on the gate dielectric layer, and the gate structure includes a first conductive layer, a barrier layer, a second conductive layer, and an insulating layer arranged in sequence, and the barrier layer wraps the bottom and side surfaces of the second conductive layer; the gate structure also includes a gate sidewall protection layer, and the gate sidewall protection layer is formed on the side walls of the barrier layer and the first conductive layer; the insulating layer is formed on the surface of the gate sidewall protection layer and on the top of the second conductive layer and the barrier layer, and the material of the second conductive layer is metal.

7. The gate structure according to claim 6, characterized in that: The gate sidewall protection layer comprises a first protection layer on the sidewall of the first conductive layer and a second protection layer on the sidewall of the barrier layer.

8. The gate structure according to claim 7, characterized in that: The thickness of the first protective layer is 5 to 20 angstroms, and the thickness of the second protective layer is 3 to 10 angstroms.

9. The gate structure according to claim 7, characterized in that: The side surfaces of the first protective layer and the second protective layer are flush.

10. The gate structure according to claim 7, characterized in that: The side surface of the gate dielectric layer is flush with the side surface of the insulating layer on the side wall of the first protection layer and the side surface of the insulating layer on the side wall of the second protection layer.

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