Semiconductor device and method for manufacturing the same

Abstract

The present application discloses a semiconductor device and a method for manufacturing the same. A method for manufacturing a semiconductor device includes: forming a contact hole in a substrate; filling the contact hole with a plug material; forming a contact plug by etching the plug material; forming a trench by etching the substrate to align it with the sidewall of the contact plug, the trench exposing the sidewall of the contact plug; forming a gate insulating layer on the exposed sidewall of the contact plug and the surface of the trench; and forming a gate electrode on the gate insulating layer, the gate electrode partially filling the trench.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2020-0102401, filed on August 14, 2020, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a word line and a bit line and a method of manufacturing the same. Background Art

[0004] As the integration of semiconductor devices becomes higher and higher, the area occupied by word lines and bit line contact plugs is shrinking. Therefore, although various techniques have been proposed to prevent short circuit defects occurring between word lines and bit line contact plugs, further improvements are still needed. One such technique uses an oxide film formed between word lines and bit line contact plugs. Summary of the invention

[0005] Embodiments of the present disclosure provide a semiconductor device having a bit line contact plug and a gate insulating layer and a method for manufacturing the semiconductor device.

[0006] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device includes: forming a contact hole in a substrate; filling the contact hole with a plug material; forming a contact plug by etching the plug material; forming a trench by etching the substrate so as to align it with the sidewall of the contact plug, the trench exposing the sidewall of the contact plug; forming a gate insulating layer on the exposed sidewall of the contact plug and the surface of the trench; and forming a gate electrode on the gate insulating layer, the gate electrode partially filling the trench.

[0007] This technology can reduce the process difficulty by forming a bit line contact plug earlier than a word line, thereby forming a stable structure.

[0008] This technology can form a gate oxide film on the sidewall of the bit line contact plug, thereby preventing a short circuit defect between the bit line contact plug and the gate electrode.

[0009] These and other features and advantages of the present disclosure will become apparent to those of ordinary skill in the art from the following drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A , Figure 1B , Figure 1C and Figure 1D is a view showing a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G , Figure 2H , Fig.2I , Figure 2J and FIG. 2K are views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G , Figure 3H , Fig. 3I , Figure 3J and Figure 3K are along Figures 2A to 2K A cross-sectional view taken along line AA′ and line BB′.

[0013] Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E is a view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 5 is a top view showing a semiconductor device according to an embodiment of the present disclosure.

[0015] Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E , Fig. 6F , Figure 6G , Figure 6H and Fig.6I is a cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure.

[0016] Figure 7 is a cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure.

[0017] Figure 8 is a cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure.

[0018] Fig. 9A and Fig. 9B is a top view showing a semiconductor device according to an embodiment of the present disclosure.

[0019] Fig. 10A , Fig. 10B , Fig. 10C and Fig. 10D is a view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] The embodiments of the present disclosure may be described herein using cross-sectional views, plan views and block diagrams of examples, and may be modified according to, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments of the present disclosure are not limited to the specific types shown and described herein, but may include changes or modifications caused by manufacturing processes. For example, the regions or zones shown in the accompanying drawings may be schematically illustrated, and only their illustrated shapes are provided as examples, without intending to limit the categories or scope of the present disclosure. For the purpose of illustration, the elements shown in the accompanying drawings may be enlarged according to their thickness and spacing. Well-known components or elements that are not related to the subject matter of the present disclosure may be omitted from the description. Throughout the specification and the accompanying drawings, the same or substantially the same reference numerals are used to represent the same or substantially the same elements.

[0021] Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. For ease of explanation, the description mainly focuses on dynamic random access memory (DRAM), but the present disclosure is not limited thereto and may be applicable to other memories or semiconductor devices.

[0022] Figure 1A , Figure 1B , Figure 1C and Figure 1D is a view showing a semiconductor device 100 according to an embodiment of the present disclosure. Figure 1A is a top view of the semiconductor device 100 . Figure 1B Shown along Figure 1A A cross-sectional view taken along line AA′ and line BB′. Figure 1C yes Figure 1A Magnified view of part C. Figure 1D 1 is a perspective view showing a plug spacer SP of the semiconductor device 100 .

[0023] refer to Figure 1A and Figure 1B , an element isolation layer 103 may be formed on the substrate 101 . The element isolation layer 103 may be located in the isolation trench 102 . The active region 104 may be defined by the element isolation layer 103 .

[0024] The substrate 101 may include a material suitable for semiconductor processing. The substrate 101 may include a semiconductor substrate. The substrate 101 may be formed of a silicon-containing material. The substrate 101 may include, for example, silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a multilayer structure thereof. The substrate 101 may include other semiconductor materials, such as germanium. The substrate 101 may include a compound semiconductor substrate, for example, a III to V group semiconductor substrate, such as GaAs. The substrate 101 may include a silicon on insulator (SOI) substrate.

[0025] The element isolation layer 103 may be a shallow trench isolation (STI) region formed by trench etching. The element isolation layer 103 may be formed by filling a shallow trench (e.g., isolation trench 102) with an insulating material. The element isolation layer 103 may include, for example, silicon oxide, silicon nitride, or a combination thereof. Chemical vapor deposition (CVD) or other deposition processes may be used to fill the isolation trench 102 with an insulating material. In addition, a planarization process such as chemical mechanical polishing (CMP) may be used.

[0026] A source / drain region SD may be formed in the active region 104. A doping process may be performed to form the source / drain region SD. The doping process may include, for example, implantation or plasma doping (PLAD). The source / drain region SD may be doped with conductive impurities. For example, the conductive impurities may include phosphorus (P), arsenic (As), antimony (Sb), or boron (B). The bottom surface of the source / drain region SD may be located at a predetermined depth from the top surface of the active region 104. The source / drain region SD may correspond to the source region and the drain region. The source / drain region SD may have the same depth. The source / drain region SD may each be a region where a bit line contact plug or a storage node contact plug is connected.

[0027] The interlayer insulating layer 105 may be formed on the substrate 101 and may be in contact with the substrate 101. The interlayer insulating layer 105 may include an insulating material. The interlayer insulating layer 105 may include, for example, silicon oxide, silicon nitride, a low-k material, or a combination thereof. The interlayer insulating layer 105 may include tetraethyl orthosilicate (TEOS). The interlayer insulating layer 105 may include one or more layers. The interlayer insulating layer 105 may include one or more layers formed of different materials. According to one embodiment, the interlayer insulating layer 105 may include two layers. According to an embodiment, the interlayer insulating layer 105 may include a layer formed of silicon oxide and a layer formed of silicon nitride.

[0028] A trench T may be formed in the substrate 101. The trench T may be referred to as a "gate trench". The trench T may include a first trench T1 and a second trench T2 parallel to the first trench T1. The first trench T1 and the second trench T2 may be spaced apart from each other and extend in one direction. The trench T may have a linear shape intersecting the active region 104 and the element isolation layer 103. The sidewall of the trench T may be adjacent to the source / drain region SD. The bottom surface of the trench T may be at a level lower than the bottom surface of the source / drain region SD. The bottom surface of the trench T may be at a level higher than the bottom surface of the element isolation layer 103. The trench T may include an upper region provided by etching the interlayer insulating layer 105 and a lower region provided by etching the substrate 101. The lower region of the trench T may have a greater depth than the upper region of the trench T.

[0029] The contact plug 106 may be formed between the trenches T. The contact plug 106 may be formed between the first trench T and the second trench T2. The contact plug 106 may penetrate the interlayer insulating layer 105. The contact plug 106 may be formed in the substrate 101. The contact plug 106 may pass through the interlayer insulating layer 105 and extend inside the substrate 101. The contact plug 106 may be referred to as a "buried plug". The contact plug 106 may include a lower portion extending to the inside of the substrate 101 and an upper portion penetrating the interlayer insulating layer 105. The depth of the lower portion of the contact plug 106 may be greater than the depth of the upper portion. That is, the depth of the portion of the contact plug 106 extending to the inside of the substrate 101 may be greater than the depth of the portion penetrating the interlayer insulating layer 105. The contact plug 106 may be buried in the substrate 101.

[0030] The shape of the top view of the contact plug 106 may be an ellipse that is broken between the surfaces facing each other. The shape of the top view of the contact plug 106 may be a circle that is broken between the surfaces facing each other. The top view of the contact plug 106 may have a rectangular shape. The trench T may be self-aligned with the side surface of the contact plug 106. The trench T may include a first trench T located on one side surface of the contact plug 106. The trench T may include a second trench T located on the opposite side surface of the contact plug 106. Both sidewalls of the contact plug 106 may contact the first trench T and the second trench T2. The bottom surface of the trench T may be located at a position deeper than the bottom surface of the contact plug 106. The cross section of the contact plug 106 may have the same width at its top and bottom. The width of the cross section of the contact plug 106 at the top may be greater than the width at the bottom. The cross section of the contact plug 106 may have a vertical shape. The cross section of the contact plug 106 may have an inclined shape.

[0031] The contact plug 106 may include a semiconductor material. The contact plug 106 may include a material containing silicon. The contact plug 106 may include, for example, polysilicon. The polysilicon may be doped with impurities. According to one embodiment, the contact plug 106 may be formed by selective epitaxial growth (SEG). For example, the contact plug 106 may include SEG silicon phosphide (SiP). The contact plug 106 may be formed without a void by selective epitaxial growth (SEG).

[0032] The plug spacer SP may be formed to surround the outer wall of the contact plug 106. The plug spacer SP may not overlap the trench T. The top view of the plug spacer SP may have a discontinuous annular shape. The cross section of the plug spacer SP may have an inclined shape. The plug spacer SP may discontinuously surround the lower outer wall of the contact plug 106. The plug spacer SP may be located between the trenches T. The plug spacer SP may include an insulating material. The plug spacer SP may include a nitrogen-containing material. The plug spacer SP may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. According to one embodiment, the plug spacer SP may be formed of silicon nitride. The plug spacer SP may be formed, for example, by chemical vapor deposition (CVD) or atomic layer deposition (ALD). The plug spacer SP may be formed by using dichlorosilane (SiH 2 Cl 2 ) and ammonia (NH 3 ) as the reactive gas for selective growth by atomic layer deposition (ALD) or low pressure chemical vapor deposition (LPCVD) process.

[0033] A gate structure BG may be formed in the trench T. The gate structure BG may include a gate insulating layer 107, a gate electrode 108, and a gate capping layer 109. The gate structure BG may extend in the form of a line. The gate structure BG may be referred to as a "buried gate structure."

[0034] The gate insulating layer 107 may be formed on the surface and sidewalls of the trench T and may contact the surface and sidewalls of the trench T. The gate insulating layer 107 may cover the surface and sidewalls of the trench T. The gate insulating layer 107 may extend vertically and continuously from the bottom surface of the trench T to the sidewalls of the contact plug 106. The gate insulating layer 107 may be formed by depositing an oxide film or a nitride film. The gate insulating layer 107 may be formed by a deposition method such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The gate insulating layer 107 may also be formed by oxidation. The gate insulating layer 107 may be formed by thermal oxidation. According to an embodiment, the gate insulating layer 107 may be formed by oxidizing the bottom surface and sidewalls of the trench T.

[0035] The gate insulating layer 107 may include a first oxide 107A, a second oxide 107B, and a third oxide 107C. The first oxide 107A may include an oxide of a sidewall of the contact plug 106. The first oxide 107A may be formed by oxidizing the exposed sidewall of the contact plug 106. The second oxide 107B may include an oxide of an exposed surface of the substrate 101. The second oxide 107B may be formed by oxidizing the exposed surface of the substrate 101. The exposed surface of the substrate 101 may be formed by the trench T. The third oxide 107C may include an oxide of an exposed surface of the interlayer insulating layer 105. The third oxide 107C may be formed by oxidizing the exposed surface of the interlayer insulating layer 105. The exposed surface of the interlayer insulating layer 105 may be formed by the trench T. The second oxide 107B may extend from the first oxide 107A. The second oxide 107B may extend from the third oxide 107C.

[0036] The gate insulating layer 107 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, high-k material, or a combination thereof. The high-k material may include a material having a dielectric constant greater than that of silicon oxide. The high-k material may include at least one metal element. The high-k material may include a hafnium-containing material. The hafnium-containing material may include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. According to one embodiment, the high-k material may include lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof. For the high-k material, other known high-k materials may be optionally used. The first oxide 107A, the second oxide 107B, and the third oxide 107C may include the same material. The first oxide 107A, the second oxide 107B, and the third oxide 107C may include, for example, silicon oxide.

[0037] The gate electrode 108 may be formed on the gate insulating layer 107 and may contact the gate insulating layer 107. The gate electrode 108 may partially fill the trench T. In order to form the gate electrode 108, a recess process may be performed. Therefore, the gate electrode 108 may be referred to as a "buried gate electrode" or a "buried word line". The top surface of the gate electrode 108 may be at a level lower than the bottom surface of the contact plug 106. The top surface of the gate electrode 108 may be at the same level as the bottom surface of the contact plug 106.

[0038] The gate electrode 108 may include a metal, a metal nitride, or a combination thereof. For example, the gate electrode 108 may be formed of titanium nitride (TiN), tungsten (W), or titanium nitride / tungsten (TiN / W). Titanium nitride / tungsten (TiN / W) may have a structure obtained by conformally forming titanium nitride and then partially filling the trench T with tungsten. The gate electrode 108 may include titanium nitride. The gate electrode 108 may include a tungsten-containing material that contains tungsten as a main element.

[0039] The gate capping layer 109 may be formed on the gate electrode 108 and may contact the gate electrode 108. The gate capping layer 109 may fill the remaining portion of the trench T. The gate capping layer 109 may be adjacent to the contact plug 106, and the two are separated by the gate insulating layer 107 therebetween. That is, the gate insulating layer 107 may extend to be located between the gate capping layer 109 and the contact plug 106 to electrically isolate the two. The top surface of the gate capping layer 109 may be at the same level as the top surface of the interlayer insulating layer 105. The gate capping layer 109 includes an insulating material. The gate capping layer 109 may include, for example, silicon nitride. According to one embodiment, the gate capping layer 109 may include, for example, silicon oxide. According to an embodiment, the gate capping layer 109 may have a multi-layer nitride-oxide-nitride (NON) structure.

[0040] refer to Figure 1C , the contact plug 106 may include a first side surface S1 and a second side surface S2 located opposite to the first side surface S1. A top view of the contact plug 106 may include a third side surface S3 and a fourth side surface S4 located opposite to the third side surface S3. The first side surface S1 and the second side surface S2 may intersect with the third side surface S3 and the fourth side surface S4.

[0041] The first side surface S1 may be parallel to the second side surface S2. The first side surface S1 and the second side surface S2 may have a straight line shape. The first side surface S1 and the second side surface S2 may have a straight line profile. The first side surface S1 and the second side surface S2 may not directly contact the plug spacer SP. The first side surface S1 and the second side surface S2 may directly contact the gate insulating layer 107.

[0042] The third side surface S3 and the fourth side surface S4 may face each other. The third side surface S3 and the fourth side surface S4 may have a curved or arc-shaped shape. The third side surface S3 and the fourth side surface S4 may have a curved or arc-shaped profile. The third side surface S3 and the fourth side surface S4 may directly contact the plug spacer SP. The third side surface S3 and the fourth side surface S4 may not directly contact the gate insulating layer 107.

[0043] The top view of the contact plug 106 may have various shapes, including, for example, a circular, oval, or rectangular shape. The width WX of the contact plug 106 in the X direction may be the same as the width WY in the Y direction. The width WX of the contact plug 106 in the X direction may be smaller than the width WY in the Y direction. The width WX of the contact plug 106 in the X direction may be larger than the width WY in the Y direction.

[0044] refer to Figure 1D The plug spacer SP may include a pair of sidewalls facing each other. The plug spacer SP may have a curved or arcuate shape. The plug spacer SP may include parallel cross sections.

[0045] The top view of the cross section of the plug spacer SP in the D1 direction may have a discontinuous annular shape. The top view of the cross section of the plug spacer SP in the D1 direction may have a curved or arcuate shape facing each other. The interval between a pair of side walls of the plug spacer SP facing each other may decrease from an upper level to a lower level. The cross section of the plug spacer SP in the D2 direction may have an inclined shape. The cross section of the plug spacer SP in the D2 direction may have a straight line shape.

[0046] According to the above embodiment, the process difficulty of forming the contact plug 106 can be reduced by forming the contact plug 106 earlier than the gate structure BG. Therefore, a stable structure can be formed. In addition, the short circuit defect between the contact plug 106 and the gate electrode 108 can be alleviated by forming the gate insulating layer 107 on the sidewall of the contact plug 106.

[0047] Figures 2A to 2K and FIG. 3A to FIG. 3K is a view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figures 2A to 2K It is a top view of a semiconductor device. FIG. 3A to FIG. 3K is along Figures 2A to 2K A cross-sectional view taken along lines AA′ and BB′.

[0048] refer to Figure 2A and Figure 3A , prepare substrate 11. Substrate 11 may include a material suitable for semiconductor processing. Substrate 11 may include a semiconductor substrate. Substrate 11 may be formed of a silicon-containing material. Substrate 11 may include, for example, silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a multilayer structure thereof. Substrate 11 may include other semiconductor materials, such as germanium. Substrate 11 may include a compound semiconductor substrate, such as a Group III to V semiconductor substrate, such as GaAs. In one embodiment, substrate 11 may include a silicon-on-insulator (SOI) substrate.

[0049] An element isolation layer 13 and an active region 14 may be formed in the substrate 11. The active region 14 may be defined by the element isolation layer 13. The element isolation layer 13 may be a shallow trench isolation (STI) region formed by trench etching. The element isolation layer 13 may be formed by filling a shallow trench (e.g., the isolation trench 12) with an insulating material. The element isolation layer 13 may include, for example, silicon oxide, silicon nitride, or a combination thereof. Chemical vapor deposition (CVD) or other deposition processes may be used to fill the isolation trench 12 with an insulating material. In addition, a planarization process such as chemical mechanical polishing (CMP) may be used.

[0050] A source / drain region SD may be formed in the active region 14. A doping process may be performed to form the source / drain region SD. The doping process may include, for example, implantation or plasma doping (PLAD). The source / drain region SD may be doped with conductive impurities. For example, the conductive impurities may include phosphorus (P), arsenic (As), antimony (Sb), or boron (B). The bottom surface of each source / drain region SD may be located at a predetermined depth from the top surface of the active region 14. The source / drain region SD may correspond to the source region and the drain region. The source / drain region SD may have the same depth. The source / drain region SD may each be a region in which a bit line contact plug or a storage node contact plug is connected.

[0051] The interlayer insulating layer 15 may be formed on the substrate 11 and may be in contact with the substrate 11. The interlayer insulating layer 15 may include an insulating material. The interlayer insulating layer 15 may include, for example, silicon oxide, silicon nitride, a low-k material, or a combination thereof. In one embodiment, the interlayer insulating layer 15 may include tetraethyl orthosilicate (TEOS). The interlayer insulating layer 15 may include one or more layers. The interlayer insulating layer 15 may include one or more layers formed of different materials. According to one embodiment, the interlayer insulating layer 15 may include two layers. According to an embodiment, the interlayer insulating layer 15 may include a layer formed of silicon oxide and a layer formed of silicon nitride.

[0052] refer to Figure 2B and Figure 3B , a contact hole mask 16 may be formed on the interlayer insulating layer 15 and may contact the interlayer insulating layer 15. The contact hole mask 16 may include a photoresist pattern.

[0053] The contact hole 17 may be formed by etching the interlayer insulating layer 15 using the contact hole mask 16 as an etching mask. From a top view, the shape of the contact hole 17 may be circular or elliptical. The contact hole 17 may be formed to penetrate the interlayer insulating layer 15. A step of recessing the exposed surface of the substrate 11 may be included. The contact hole 17 may be formed in the substrate 11. When etching the interlayer insulating layer 15 using the contact hole mask 16 as an etching mask, a portion of the substrate 11 may be etched together with the interlayer insulating layer 105. Therefore, a portion of the substrate 11 may be exposed through the contact hole 17. The bottom surface of the contact hole 17 may be located at a level lower than the top surface of the substrate 11. The bottom surface of the contact hole 17 may be located at a level higher than the bottom surface of the source / drain region SD.

[0054] refer to Figure 2C and Figure 3C , a preliminary spacer layer 18A′ may be formed to cover the interlayer insulating layer 15 and the contact hole 17. The preliminary spacer layer 18A′ may include an insulating material. The preliminary spacer layer 18A′ may include a nitrogen-containing material. The preliminary spacer layer 18A′ may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. According to one embodiment, the preliminary spacer layer 18A′ may be formed of silicon nitride.

[0055] The pre-spacer layer 18A′ may be formed, for example, by chemical vapor deposition (CVD) or atomic layer deposition (ALD). The pre-spacer layer 18A′ may be formed by using dichlorosilane (SiH 2 Cl 2 ) and ammonia (NH 3 ) as the reactive gas for selective growth by atomic layer deposition (ALD) or low pressure chemical vapor deposition (LPCVD) process.

[0056] refer to Figure 2D and Figure 3D , the pre-spacer 18A may be formed by etching the pre-spacer layer 18A′. As the pre-spacer 18A is formed, a portion of the substrate 11 may be exposed. As the pre-spacer 18A is formed, the bottom surface of the contact hole 17 may be exposed. The surface of the substrate 11 exposed in the contact hole 17 may be further enlarged by the pre-spacer 18A. The surface of the substrate 11 exposed inside the contact hole 17 may be further recessed by the pre-spacer 18A. The surface of the substrate 11 exposed inside the contact hole 17 may be further etched by the pre-spacer 18A. Therefore, a recessed contact hole 17R may be formed.

[0057] The recessed contact hole 17R may penetrate the interlayer insulating layer 15. A bottom surface of the recessed contact hole 17R may be formed in the substrate 11. The recessed contact hole 17R may penetrate the interlayer insulating layer 105 and be formed in the substrate 11.

[0058] As the pre-spacer 18A is formed, the top surface of the interlayer insulating layer 15 may be exposed. The pre-spacer 18A may cover the sidewall of the recessed contact hole 17R. The shape of the pre-spacer 18A may be around the sidewall of the recessed contact hole 17R. From a top view, the pre-spacer 18A may have an annular shape. The perimeter of the pre-spacer 18A may narrow from the top to the bottom of the pre-spacer 18A. The cross section of the pre-spacer 18A may have an inclined shape.

[0059] refer to Figure 2E and Figure 3E , a plug material 19A may be formed in the contact hole 17R. The plug material 19A may fill the contact hole 17R. In order to form the plug material 19A, a plug material layer 19A′ may be formed to cover the interlayer insulating layer 15. This may include a process of planarizing the plug material layer 19A′ to expose the top surface of the interlayer insulating layer 15. Thus, the top surface of the plug material 19A may be exposed. The top surface of the plug material 19A may be at the same level as the top surface of the interlayer insulating layer 15. The plug material 19A may penetrate the interlayer insulating layer 15 and contact a portion of the substrate 11.

[0060] The plug material 19A may include a semiconductor material. The plug material 19A may include a conductive material. The plug material 19A may include a silicon-containing material. The plug material 19A may include, for example, polysilicon. The polysilicon may be doped with impurities. According to one embodiment, the plug material 19A may be formed by selective epitaxial growth (SEG). For example, the plug material 19A may include SEG silicon phosphide (SiP). In this way, a void-free plug material 19A may be formed by SEG.

[0061] refer to Figure 2F and Figure 3F , the trench hard mask layer 20A may be formed on the interlayer insulating layer 15 and the plug material 19A and may be in direct contact with the interlayer insulating layer 15 and the plug material 19A. The trench hard mask layer 20A may be formed to define at least one or more openings in the interlayer insulating layer 15. The trench hard mask layer 20A may have a multilayer structure. The trench hard mask layer 20A may include one or more layers. The height of the trench hard mask layer 20A may be greater than the height of the interlayer insulating layer 15. The trench hard mask layer 20A may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. According to one embodiment, the trench hard mask layer 20A may be formed of silicon nitride.

[0062] The trench hard mask layer 20A may be formed, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In order to improve the deposition effect, the trench hard mask layer 20A may use plasma. For example, the trench hard mask layer 20A may be formed by plasma enhanced CVD (PECVD) or plasma enhanced ALD (PEALD).

[0063] refer to Figure 2G and Figure 3G , the trench mask pattern 20M may be formed on the trench hard mask layer 20A and may contact the trench hard mask layer 20A. The trench mask pattern 20M may be formed by a known photolithography process. The trench mask pattern 20M may include a hard mask pattern patterned by a photoresist pattern. The trench mask pattern 20M may include a line type mask.

[0064] The trench hard mask layer 20A may be etched using the trench mask pattern 20M as an etching mask. A trench hard mask 20 may be formed by etching the trench hard mask layer 20A. A portion of the interlayer insulating layer 15 and a portion of the substrate 11 may be etched using the trench hard mask 20 as an etching mask. A trench 21 may be formed by etching a portion of the interlayer insulating layer 15 and a portion of the substrate 11. The trench 21 may be referred to as a "gate trench". The trench 21 may have a linear shape intersecting the active region 14 and the element isolation layer 13. A plurality of trenches 21 spaced apart from each other may be formed.

[0065] The trench 21 may be self-aligned with the side surface of the contact plug 19B. The trench 21 may be self-aligned with the exposed sidewall of the contact plug 19B. The sidewall of the contact plug 19B may abut the trench 21. As the trench 21 is formed, a portion of the sidewall of the contact plug 19B may be exposed.

[0066] The bottom surface of the trench 21 may be at a level lower than the bottom surface of the contact plug 19B. The bottom surface of the trench 21 may be at a level higher than the bottom surface of the element isolation layer 13. The sidewall of the trench 21 may abut the source / drain region SD. The bottom surface of the source / drain region SD may be higher than the bottom surface of the trench 21. The trench 21 may include an upper region provided by etching the interlayer insulating layer 15 and a lower region provided by etching the substrate 11, and the depth of the lower region may be greater than the depth of the upper region. The trench 21 may have a depth sufficient to increase the average cross-sectional area of ​​the subsequent gate electrode. Therefore, the resistance of the gate electrode may be reduced. Although not shown, a portion of the element isolation layer 13 may be recessed so that the top of the active region 14 below the trench 21 protrudes. For example, the element isolation layer 13 below the trench 21 may be recessed optionally. Therefore, a fin region may be formed below the trench 21. The fin region may be part of the channel region.

[0067] As the trench 21 is formed, a portion (R) of the plug material 19A may be removed. The trench 21 may etch both sidewalls of the plug material 19A. As the plug material 19A is etched, a contact plug 19B may be formed. That is, the contact plug 19B may be formed simultaneously with the formation of the trench 21. The contact plug 19B may be formed between the trenches 21. The contact plug 19B may penetrate the interlayer insulating layer 15. The contact plug 19B may be formed in the substrate 11. The contact plug 19B may pass through the interlayer insulating layer 15 and extend to the inside of the substrate 11. The contact plug 19B may be referred to as a "buried plug". The contact plug 19B may include a lower portion extending to the inside of the substrate 11 and an upper portion penetrating the interlayer insulating layer 15. The depth of the lower portion of the contact plug 19B may be greater than the depth of its upper portion. That is, the depth of the portion of the contact plug 19B extending to the inside of the substrate 11 may be greater than the depth of the portion penetrating the interlayer insulating layer 15. The contact plug 19B may be buried in the substrate 11 .

[0068] From a top view, the shape of the contact plug 19B may be an ellipse or a circle that is disconnected between two opposing surfaces. The width WT of the top portion of the contact plug 19B may be the same as the width WB of the bottom portion. The cross section of the contact plug 19B may have a vertical shape. The cross section of the contact plug 19B may have an inclined shape. The exposed sidewall of the contact plug 19B may include a straight profile. The unexposed sidewall of the contact plug 19B may include a curved or arcuate profile.

[0069] As the trench 21 is formed, a portion (R) of the pre-spacer 18A may be removed. The trench 21 may etch a portion of the pre-spacer 18A. As the pre-spacer 18A is etched, the plug spacer 18 may be formed. As the pre-spacer 18A is cut, the plug spacer 18 may be formed. The plug spacer 18 may cover the unexposed sidewall of the contact plug 19B. The plug spacer 18 may surround a portion of the outer wall of the contact plug 19B. The plug spacer 18 may not overlap with the trench 21. The top view of the plug spacer 18 may have a discontinuous annular shape. The shape of the top view of the plug spacer 18 may be a curved or arc-shaped shape facing each other. The cross section of the plug spacer 18 may have an inclined shape. The plug spacer 18 may discontinuously surround the lower outer wall of the contact plug 19B. The plug spacer 18 may be located between the trenches 21.

[0070] refer to Figure 2H and Figure 3H , the pre-gate insulating layer 22A may be formed on the bottom surface and sidewalls of the trench 21 and in direct contact with the bottom surface and sidewalls of the trench 21. The pre-gate insulating layer 22A may be formed on the exposed sidewalls of the contact plug 19B and in direct contact with the exposed sidewalls of the contact plug 19B. The pre-gate insulating layer 22A may be formed on the surface of the trench 21 and in direct contact with the surface of the trench 21. Before forming the pre-gate insulating layer 22A, etching damage to the surface of the trench 21 may be repaired. For example, a sacrificial oxide may be formed by thermal oxidation and then removed.

[0071] The pre-gate insulating layer 22A may be formed by depositing an oxide film or a nitride film. The pre-gate insulating layer 22A may be formed on the bottom surface and sidewalls of the trench 21 and may be in direct contact with the bottom surface and sidewalls of the trench 21. The pre-gate insulating layer 22A may be formed on the sidewalls of the interlayer insulating layer 15 exposed by the trench 21 and may be in direct contact with the sidewalls of the interlayer insulating layer 15 exposed by the trench 21. The pre-gate insulating layer 22A may be formed on the sidewalls of the contact plug 19B exposed by the trench 21 and may be in direct contact with the sidewalls of the contact plug 19B exposed by the trench 21. The pre-gate insulating layer 22A may be formed on the top surface and sidewalls of the trench hard mask 20 exposed by the trench 21 and may be in direct contact with the top surface and sidewalls of the trench hard mask 20 exposed by the trench 21. Thus, the pre-gate insulating layer 22A may cover the trench 21, the interlayer insulating layer 15, the contact plug 19B, and the trench hard mask 20. The pre-gate insulating layer 22A may be formed by a deposition method such as, for example, chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0072] According to one embodiment, the pre-gate insulating layer 22A may be formed by oxidation. For example, the pre-gate insulating layer 22A may be formed by thermal oxidation. According to one embodiment, the pre-gate insulating layer 22A may be formed by oxidizing the sidewalls of the contact plug 19B and the surface of the trench 21. The pre-gate insulating layer 22A may be formed by oxidizing the substrate 11 exposed by the trench 21. The pre-gate insulating layer 22A may be formed by oxidizing the sidewalls of the contact plug 19B exposed by the trench 21. The pre-gate insulating layer 22A may be formed by oxidizing the sidewalls of the interlayer insulating layer 15 exposed by the trench 21. The pre-gate insulating layer 22A may be formed by oxidizing the top surface and sidewalls of the trench hard mask 20 exposed by the trench 21. The thickness of the oxide film formed on the top surface and sidewalls of the trench hard mask 20 exposed by the trench 21 may be smaller than the thickness of the oxide film formed on the sidewalls of the interlayer insulating layer 15. An oxide film may not be formed on the top surface and sidewalls of the trench hard mask 20 exposed by the trench 21. Therefore, the pre-gate insulating layer 22A may cover the trench 21, the sidewalls of the interlayer insulating layer 15, and the sidewalls of the contact plug 19B.

[0073] The pre-gate insulating layer 22A may include, for example, silicon oxide, silicon nitride, silicon oxynitride, high-k material, or a combination thereof. The high-k material may include a material having a dielectric constant greater than that of silicon oxide. The high-k material may include at least one metal element. The high-k material may include a hafnium-containing material. The hafnium-containing material may include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. According to one embodiment, the high-k material may include lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof. For the high-k material, other known high-k materials may be optionally used.

[0074] refer to Fig.2I and Fig. 3I , the gate electrode 23 may be formed on the pre-gate insulating layer 22A and may be in direct contact with the pre-gate insulating layer 22A. In order to form the gate electrode 23, a conductive layer (not shown) may be formed to fill the trench 21, and then a recess process may be performed. For the recess process, an etch-back process may be performed, or a chemical mechanical polishing (CMP) process and an etch-back process may be performed sequentially. The gate electrode 23 may partially fill the trench 21. Therefore, the gate electrode 23 may be referred to as a 'buried gate electrode' or a 'buried word line'. The top surface of the gate electrode 23 may be at a level lower than the bottom surface of the contact plug 19B. The top surface of the gate electrode 23 may be at the same level as the bottom surface of the contact plug 19B.

[0075] The gate electrode 23 may include a metal, a metal nitride, or a combination thereof. For example, the gate electrode 23 may be formed of titanium nitride (TiN), tungsten (W), or titanium nitride / tungsten (TiN / W). Titanium nitride / tungsten (TiN / W) may have a structure obtained by conformally forming titanium nitride and then partially filling the trench 21 with tungsten. For the gate electrode 23, titanium nitride may be used alone, which may be referred to as a gate electrode 23 of a "TiN-only" structure. The gate electrode 23 may include a tungsten-containing material containing tungsten as a main element.

[0076] Subsequently, a doping process may be optionally performed. The doping process may include, for example, implantation or plasma doping (PLAD).

[0077] refer to Figure 2J and Figure 3J The pre-gate capping layer 24A may be formed on the gate electrode 23 and may be in direct contact with the gate electrode 23. The remaining portion of the trench 21 may be filled with the pre-gate capping layer 24A. The pre-gate capping layer 24A may cover the pre-gate insulating layer 22A.

[0078] The pre-gate cover layer 24A includes an insulating material. The pre-gate cover layer 24A may include, for example, silicon nitride. According to one embodiment, the pre-gate cover layer 24A may include, for example, silicon oxide. The pre-gate cover layer 24A may have a multi-layer structure. The pre-gate cover layer 24A may include one or more layers. The pre-gate cover layer 24A may have a multi-layer nitride-oxide-nitride (NON) structure.

[0079] refer to Figure 2K and Figure 3K , a gate capping layer 24 may be formed in the trench 21. The top surface of the gate capping layer 24 may be at the same level as the top surface of the interlayer insulating layer 15. To this end, mechanical polishing (CMP) may be performed when forming the gate capping layer 24. The gate capping layer 24 may be formed via an etching process using a separate mask. In this process, the trench hard mask 20, the pre-gate insulating layer 22A and the pre-gate capping layer 24A located on the top surface of the contact plug 19B and the interlayer insulating layer 15 may be removed. Therefore, the top surface of the interlayer insulating layer 15 may be exposed. As a portion of the pre-gate insulating layer 22A is removed, a gate insulating layer 22 may be formed inside the trench 21.

[0080] The gate insulating layer 22 may be formed on and in contact with the surface of the trench 21, the sidewall of the contact plug 19B, and the sidewall of the interlayer insulating layer 15. The gate insulating layer 22 may include a first oxide, which is an oxide of the sidewall of the contact plug 19B. The gate insulating layer 22 may include a second oxide, which is an oxide of the surface of the substrate 11 exposed by the trench 21. The gate insulating layer 22 may include a third oxide, which is an oxide of the sidewall of the contact plug 19B exposed by the trench 21. The first oxide, the second oxide, and the third oxide may be continuous. The first oxide, the second oxide, and the third oxide may include the same material. The first oxide, the second oxide, and the third oxide may include, for example, silicon oxide. The gate insulating layer 22 may extend to be located between the gate capping layer 24 and the contact plug 19B.

[0081] The gate insulating layer 22, the gate electrode 23 and the gate capping layer 24 may form a gate structure 25. The gate structure 25 may be formed in the trench 21. The gate structure 25 may extend in a linear shape. The contact plug 19B may be located between the gate structures 25. The gate structure 25 may be referred to as a 'buried gate structure'.

[0082] According to the above embodiment, the process difficulty in forming the contact plug 19B can be reduced by forming the contact plug 19B earlier than the gate electrode 23. Further, the short circuit defect between the contact plug 19B and the gate electrode 23 can be alleviated by forming the gate insulating layer 22 on the sidewall of the contact plug 19B.

[0083] FIG. 4A to FIG. 4E is a view showing a semiconductor device according to an embodiment of the present disclosure. 4A to 4D is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 4E is a perspective view showing the plug spacer 18 ′.

[0084] First, you can FIG. 2A to FIG. 2F and FIG. 3A to FIG. 3F The method shown forms a pre-spacer 18A and a plug material 19A in the contact hole 17. 4A to 4D In the drawings, the same reference numerals are used to denote FIG. 3A to FIG. 3F Detailed description of repeated elements may be omitted.

[0085] refer to 4A to 4D , the semiconductor device 200 may be similar to Figure 1B A semiconductor device 100 is provided.

[0086] refer to Figure 4A, a trench hard mask 30 may be formed on the substrate 11 and may contact the substrate 11. A trench mask pattern 30M may be formed on the trench hard mask 30 and may contact the trench hard mask 30. The trench mask pattern 30M may be formed by a known photolithography process. The trench mask pattern 30M may include a hard mask pattern patterned by a photoresist pattern.

[0087] The trench hard mask layer (not shown) may be etched using the trench mask pattern 30M as an etch mask. The trench hard mask 30 may be formed by etching the trench hard mask layer (not shown).

[0088] The trench hard mask 30 may have a multilayer structure. The trench hard mask 30 may include one or more layers. The height of the trench hard mask 30 may be greater than the height of the interlayer insulating layer 15. The trench hard mask 30 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. According to one embodiment, the trench hard mask 30 may be formed of silicon nitride. Figure 3G The same method as given for the trench hard mask 20 is used to form the trench hard mask 30 .

[0089] The trench 31 may be formed using the trench hard mask 30 as an etching mask. The trench 31 may be referred to as a “gate trench.” The plug material 19A and the interlayer insulating layer 15 and a portion of the substrate 11 may be etched using the trench hard mask 30 as an etching mask. Thus, the trench 31 may be formed.

[0090] As trench 31 is formed, a portion of substrate 11 may be exposed. Figure 4A The top view can be Figure 2G The same. The groove 31 may have a linear shape intersecting the active region 14 and the element isolation layer 13. The bottom surface of the groove 31 may be at a level higher than the bottom surface of the element isolation layer 13. The groove 31 may have a depth smaller than the element isolation layer 13. The sidewall of the groove 31 may be adjacent to the source / drain region SD. The bottom surface of the source / drain region SD may be higher than the bottom surface of the groove 31. The groove 31 may include an upper region provided by etching the interlayer insulating layer 15 and a lower region provided by etching the substrate 11, and the lower region may have a depth greater than the upper region. The groove 31 may have a depth sufficient to increase the average cross-sectional area of ​​the subsequent gate electrode. Therefore, the resistance of the gate can be reduced. A fin region may be formed below the groove 31.

[0091] As the trench 31 is formed, a portion (R') of the plug material 19A may be removed. As the trench 31 is formed, both sidewalls of the plug material 19A may be etched. The contact plug 19B' may be formed by etching the plug material 19A. That is, the contact plug 19B' may be formed simultaneously with the formation of the trench 31.

[0092] A contact plug 19B′ may be formed between the trenches 31. The contact plug 19B′ may penetrate the interlayer insulating layer 15. The contact plug 19B′ may be formed in the substrate 11. The contact plug 19B′ may pass through the interlayer insulating layer 15 and extend to the inside of the substrate 11. The contact plug 19B′ may be referred to as a 'buried plug'. The contact plug 19B′ may include a lower portion extending to the inside of the substrate 11 and an upper portion penetrating the interlayer insulating layer 15. The lower portion of the contact plug 19B′ may have a greater depth than the upper portion thereof. That is, the depth of the portion of the contact plug 19B′ extending to the inside of the substrate 11 may be greater than the depth of the portion penetrating the interlayer insulating layer 15. The contact plug 19B′ may be buried in the substrate 11.

[0093] The sidewall of the contact plug 19B′ may abut the trench 31. The trench 31 may be self-aligned with the sidewall of the contact plug 19B′. The trench 31 may be self-aligned with the exposed sidewall of the contact plug 19B′. From a top view, the shape of the contact plug 19B′ may be an ellipse or a circle that is disconnected between two opposing surfaces. The width WT′ of the top portion of the contact plug 19B′ may be greater than the width WB′ of the bottom portion. The cross-section of the contact plug 19B′ may have an inclined shape. The exposed sidewall of the contact plug 19B′ may include a straight profile. The unexposed sidewall of the contact plug 19B′ may include an arcuate profile.

[0094] As the trench 31 is formed, a portion (R′) of the pre-spacer 18A may be removed. As the pre-spacer 18A is etched, a plug spacer 18′ may be formed. As the pre-spacer 18A is cut, a plug spacer 18′ may be formed. The plug spacer 18′ may cover the unexposed sidewalls of the contact plug 19B′. The shape of the plug spacer 18′ may include an outer wall surrounding the contact plug 19B′. The plug spacer 18′ may not overlap the trench 31.

[0095] The top view of the plug spacer 18' may have a discontinuous annular shape. The shape of the top view of the plug spacer 18' may be a curved or arcuate shape facing each other. The top view of the lower cross section of the plug spacer 18' may have an annular shape. The circumference of the plug spacer 18' may decrease from the top to the bottom. The cross section of the plug spacer 18' may have an inclined shape. The plug spacer 18' may change from a discontinuous annular shape to a continuous annular shape from the top to the bottom. The plug spacer 18' may be located between the grooves 31. The plug spacer 18' may not overlap with the groove 31.

[0096] The plug spacer 18′ located on the lower outer wall of the contact plug 19B′ may be referred to as a bottom spacer RS. The plug spacer 18′ may include a bottom spacer RS. The bottom spacer RS ​​may be located on the lower outer wall of the contact plug 19B′. The bottom spacer RS ​​may be formed in a region narrower than the width WT′ of the top portion of the contact plug 19B′ and wider than the width WB′ of the bottom portion. The bottom spacer RS ​​may be formed between the contact plug 19B′ and the trench 31. The bottom spacer RS ​​may be formed between the bottom edge of the contact plug 19B′ and the trench 31. The bottom spacer RS ​​may be connected to the plug spacer 18′. The bottom spacer RS ​​may have a shape surrounding the lower outer wall of the contact plug 19B′. From a top view, the bottom spacer RS ​​may have a ring shape.

[0097] refer to Figure 4B , the pre-gate insulating layer 32A may be formed on the bottom surface and the sidewalls of the trench 31 and may be in direct contact with the bottom surface and the sidewalls of the trench 31 . Figure 4B The top view can be Figure 2H The pre-gate insulating layer 32A may be formed on the exposed sidewalls of the contact plug 19B′ and may be in direct contact with the exposed sidewalls of the contact plug 19B′. The pre-gate insulating layer 32A may be formed on the surface of the trench 31 and may be in direct contact with the surface of the trench 31. Before forming the pre-gate insulating layer 32A, etching damage to the surface of the trench 31 may be repaired. For example, a sacrificial oxide may be formed by thermal oxidation, and then it may be removed.

[0098] The pre-gate insulating layer 32A may be formed by depositing an oxide film. The pre-gate insulating layer 32A may be formed on the bottom surface and sidewalls of the trench 31 and may be in direct contact with the bottom surface and sidewalls of the trench 31. The pre-gate insulating layer 32A may be formed on the sidewalls of the interlayer insulating layer 15 exposed by the trench 31 and may be in direct contact with the sidewalls of the interlayer insulating layer 15 exposed by the trench 31. The pre-gate insulating layer 32A may be formed on the sidewalls of the contact plug 19B′ exposed by the trench 31 and may be in direct contact with the sidewalls of the contact plug 19B′ exposed by the trench 31. The pre-gate insulating layer 32A may be formed on the sidewalls of the bottom spacer RS ​​exposed by the trench 31 and may be in direct contact with the sidewalls of the bottom spacer RS ​​exposed by the trench 31. The pre-gate insulating layer 32A may be formed on and may be in direct contact with the top surface and sidewalls of the trench hard mask 30 exposed by the trench 31. Therefore, the pre-gate insulating layer 32A may cover the trench 31, the interlayer insulating layer 15, the bottom spacer RS, the contact plug 19B′, and the trench hard mask 30. The pre-gate insulating layer 32A may be formed by a deposition method such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0099] According to one embodiment, the pre-gate insulating layer 32A may be formed by oxidation. The pre-gate insulating layer 32A may be formed by thermal oxidation. According to an embodiment, the pre-gate insulating layer 32A may be formed by oxidizing the bottom surface and sidewalls of the trench 31. According to an embodiment, the pre-gate insulating layer 32A may be formed by oxidizing the bottom surface and sidewalls of the trench 31. The pre-gate insulating layer 32A may be formed by oxidizing the exposed sidewalls of the contact plug 19B′. The pre-gate insulating layer 32A may be formed by oxidizing the sidewalls of the interlayer insulating layer 15 exposed by the trench 31. The pre-gate insulating layer 32A may be formed by oxidizing the contact plug 19B′ exposed by the trench 31. The pre-gate insulating layer 32A may be formed by oxidizing the sidewalls of the bottom spacer RS ​​exposed by the trench 31. The thickness of the oxide film formed on the top surface and sidewalls of the trench hard mask 30 exposed by the trench 31 may be less than the thickness of the oxide film formed on the sidewalls of the interlayer insulating layer 15. An oxide film may not be formed on the sidewalls and top surface of the trench hard mask 30 exposed by the trench 31. Therefore, the pre-gate insulating layer 32A may cover the sidewalls of the trench 31, the interlayer insulating layer 15, and the contact plug 19B'.

[0100] The pre-gate insulating layer 32A may include, for example, silicon oxide, silicon nitride, silicon oxynitride, high-k material, or a combination thereof. The high-k material may include a material having a dielectric constant greater than that of silicon oxide. The high-k material may include a hafnium-containing material. The hafnium-containing material may include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. According to one embodiment, the high-k material may include lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof. For the high-k material, other known high-k materials may be optionally used.

[0101] refer to Figure 4C , the gate electrode 33 may be formed on the pre-gate insulating layer 32A and may be in direct contact with the pre-gate insulating layer 32A. Figure 4C The top view can be Figure 2J The same. In order to form the gate electrode 33, a conductive layer (not shown) may be formed to fill the trench 31, and then a recess process may be performed. For the recess process, an etch-back process may be performed, or a chemical mechanical polishing (CMP) process and an etch-back process may be performed sequentially. The gate electrode 33 may have a recessed shape, which means that it only partially fills the trench 31. The top surface of the gate electrode 33 may be at a lower level than the bottom surface of the contact plug 19B′.

[0102] The gate electrode 33 may include a metal, a metal nitride, or a combination thereof. For example, the gate electrode 33 may be formed of titanium nitride (TiN), tungsten (W), or titanium nitride / tungsten (TiN / W). Titanium nitride / tungsten (TiN / W) may have a structure obtained by conformally forming titanium nitride and then partially filling the trench 31 with tungsten. For the gate electrode 33, titanium nitride may be used alone, which may be referred to as a gate electrode 33 of a "TiN-only" structure. The gate electrode 33 may include a tungsten-containing material that contains tungsten as a main element.

[0103] Subsequently, a doping process may be optionally performed. The doping process may include, for example, implantation or plasma doping (PLAD).

[0104] The pre-gate capping layer 34A may be formed on the gate electrode 33 and may be in direct contact with the gate electrode 33. The remaining portion of the trench 31 above the gate electrode 33 may be filled with the pre-gate capping layer 34A. The pre-gate capping layer 34A may cover the pre-gate insulating layer 32A and the gate electrode 33. The pre-gate capping layer 34A includes an insulating material. The pre-gate capping layer 34A may include, for example, silicon nitride. According to one embodiment, the pre-gate capping layer 34A may include, for example, silicon oxide. The pre-gate capping layer 34A may have a multilayer structure. The pre-gate capping layer 34A may include one or more layers. The pre-gate capping layer 34A may have a multilayer nitride-oxide-nitride (NON) structure.

[0105] refer to Figure 4D , a gate capping layer 34 may be formed in the trench 31 . Figure 4D The top view can be Figure 2K The top surface of the gate capping layer 34 may be at the same level as the top surface of the interlayer insulating layer 15. To this end, chemical mechanical polishing (CMP) may be performed when forming the gate capping layer 34. The gate capping layer 34 may be formed via an etching process using a separate mask. In this process, the trench hard mask 30, the pre-gate insulating layer 32A, and the pre-gate capping layer 34A located on the top surfaces of the interlayer insulating layer 15 and the contact plug 19B′ may be removed. Therefore, the top surface of the interlayer insulating layer 15 may be exposed.

[0106] As a portion of the pre-gate insulating layer 32A is removed, a gate insulating layer 32 may be formed inside the trench 31. The gate insulating layer 32, the gate electrode 33, and the gate capping layer 34 may form a gate structure 35. The gate structure 35 may be formed in the trench 31. The gate structure 35 may extend in a linear shape. The gate structure 35 may be referred to as a 'buried gate structure'.

[0107] The gate insulating layer 32 may be formed on the surface of the trench 31 and the sidewall of the interlayer insulating layer 15 and may be in direct contact with the surface of the trench 31 and the sidewall of the interlayer insulating layer 15. The gate insulating layer 32 may be formed on the sidewall of the contact plug 19B′ and may be in direct contact with the sidewall of the contact plug 19B′. The gate insulating layer 32 may be formed between the contact plug 19B′ and the gate capping layer 34.

[0108] refer to Figure 4E , the plug spacer 18' may include a curved or arcuate outer wall 18'R. The curved or arcuate outer wall 18'R may include a curved or arcuate shape. The plug spacer 18' may include parallel cutting surfaces 18'C. The curved or arcuate outer wall 18'R and the parallel cutting surfaces 18'C may be continuous. The top view of the curved or arcuate outer wall 18'R may form symmetry.

[0109] The top view of the cross section of the plug spacer 18' in the D1 direction may have a discontinuous annular shape at a higher level. The top view of the cross section of the plug spacer 18' in the D1 direction may have an arc shape facing each other at a higher level. The perimeter of the plug spacer 18' may decrease from a higher level to a lower level. Therefore, the cross section of the plug spacer 18' in the D2 direction may have an inclined shape. The top view of the cross section of the plug spacer 18' in the D1 direction may have an annular shape at a lower level.

[0110] The plug spacer 18′ may include a bottom spacer RS. The bottom spacer RS ​​may be connected to the plug spacer 18′. The bottom spacer RS ​​may be located at a lower level than the plug spacer 18′. The bottom spacer RS ​​may partially include parallel cutting surfaces and have a continuous shape. The circumference of the bottom spacer RS ​​may decrease from a higher level to a lower level. The bottom spacer RS ​​may include an annular shape whose circumference decreases from a higher level to a lower level. The bottom spacer RS ​​at a higher level may be thinned by the cutting surface. Therefore, the thickness of the bottom spacer RS ​​may increase from a higher level to a lower level. The thickness of the bottom spacer RS ​​at a lower level may be the same as the thickness of the plug spacer 18′.

[0111] According to the above-described embodiment, the process difficulty in forming the contact plug 19B′ can be reduced by forming the contact plug 19B′ earlier than the gate electrode 33. Further, the short-circuit defect between the contact plug 19B′ and the gate electrode 33 can be alleviated by forming the gate insulating layer 32 on the sidewall of the contact plug 19B′. The short-circuit defect between the contact plug 19B′ and the gate electrode 33 can be further alleviated by forming a bottom spacer RS ​​on the lower outer wall of the contact plug 19B′.

[0112] Figure 5 is a cross-sectional view illustrating a top view of a semiconductor device 300 according to an embodiment of the present disclosure.

[0113] The semiconductor device 300 may include a plurality of memory cells. Each memory cell may include an active region 104, an element isolation layer (not shown), a gate structure BG, a bit line contact plug BLC, a bit line structure BL, and a memory element 125. Each memory cell may include a first trench TC1 and a second trench TC2, which are formed in a substrate and spaced apart from each other. The first trench TC1 may be filled with a first gate structure BG1. The second trench TC2 may be filled with a second gate structure BG2. The gate structure BG may extend in a first direction X, and the bit line structure BL may extend in a second direction Y. The first direction X may intersect with the second direction Y.

[0114] Each gate structure BG may include a gate insulating layer GP, a gate electrode GE, and a gate capping layer (not shown). The gate structure BG may correspond to Figure 1A The gate insulating layer GP may correspond to Figure 1A The gate insulating layer 107 is formed. The gate structure BG may be referred to as a “buried gate structure”.

[0115] Each bit line structure BL may include a bit line hard mask (not shown), a bit line 111, and a barrier layer (not shown). A bit line spacer 115 may be formed on both sidewalls of the bit line structure BL. A bit line contact plug BLC may be formed below the bit line structure BL. Each memory cell may include a storage node contact plug (not shown), a storage element 125, and a landing pad 120. The storage node contact plug (not shown) may be formed below the storage element 125. The storage node contact plug (not shown) may be adjacent to the bit line contact plug BLC. The storage node contact plug (not shown) may be formed to be spaced apart from the gate electrode GE. The landing pad 120 may overlap the storage node contact plug (not shown) and the bit line 111.

[0116] One side wall of the bit line contact plug BLC may be self-aligned with the gate structure BG. The shape of the bit line contact plug BLC may be a rectangular column. The bit line contact plug BLC may include a first side surface in contact with the first gate structure BG1 and a second side surface in contact with the second gate structure BG2. The first side surface may contact the first gate insulating layer included in the first gate structure BG1, and the second side surface may contact the second gate insulating layer included in the second gate structure BG2. The first side surface and the second side surface may be parallel to each other. The first side surface and the second side surface may have a vertical shape. The first side surface and the second side surface may have an inclined shape.

[0117] FIG. 6A to FIG. 6I is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 6A to FIG. 6I is along Figure 5 First, by FIG. 3A to FIG. 3I By using the method shown, source / drain regions SD, contact plugs 19B, plug spacers 18, interlayer insulating layers 15, gate electrodes (not shown), gate insulating layers (not shown), and gate capping layers (not shown) can be formed. FIG. 6A to FIG. 6I The same reference numerals are used to represent Fig. 3I Detailed description of repeated elements may be omitted.

[0118] refer to Fig. 6A, the barrier metal layer 110A may be formed on the interlayer insulating layer 15 and the contact plug 19B and may be in direct contact with the interlayer insulating layer 15 and the contact plug 19B. The height of the barrier metal layer 110A may be less than the height of the interlayer insulating layer 15. The barrier metal layer 110A may include titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), or a combination thereof. According to an embodiment, the barrier metal layer 110A may include a material containing titanium nitride (TiN).

[0119] The bit line layer 111A may be formed on the barrier metal layer 110A and may contact the barrier metal layer 110A. The bit line layer 111A may be formed of a material with a lower resistivity than the contact plug 19B. The bit line layer 111A may include a metal material with a lower resistivity than the contact plug 19B. For example, the bit line layer 111A may include a metal, a metal nitride, a metal silicide, or a combination thereof. The bit line layer 111A may include a tungsten-containing material having tungsten as a main element. For example, the bit line layer 111A may be formed by stacking tungsten silicide, a tungsten nitride film, and a tungsten film. According to an embodiment, the bit line layer 111A may include tungsten W or a tungsten compound.

[0120] The bit line hard mask layer 112A may be formed on the bit line layer 111A and may be in direct contact with the bit line layer 111A. The bit line hard mask layer 112A may be formed of an insulating material. The bit line hard mask layer 112A may be formed of a material having an etching selectivity to the bit line layer 111A. The bit line hard mask layer 112A may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. According to an embodiment, the bit line hard mask layer 112A may be formed of silicon nitride.

[0121] The bit line mask 113 may be formed on the bit line hard mask layer 112A and may contact the bit line hard mask layer 112A. The bit line mask 113 may include a photoresist pattern. The bit line mask 113 may have a line shape extending in any one direction. The line width of the bit line mask 113 may be smaller than the diameter of the top surface of the contact plug 19B.

[0122] refer to Figure 6B , a bit line structure BL may be formed. The bit line structure BL may include a bit line contact plug 19 , a barrier layer 110 , a bit line 111 , and a bit line hard mask 112 .

[0123] The bit line hard mask layer 112A may be etched using the bit line mask 113 as an etching mask. Thus, the bit line hard mask 112 may be formed. The bit line layer 111A, the barrier metal layer 110A, and the contact plug 19B may be etched using the bit line hard mask 112 as an etching mask. Thus, the bit line 111, the barrier layer 110, and the bit line contact plug 19 may be formed. The bit line contact plug 19, the barrier layer 110, the bit line 111, and the bit line hard mask 112 may have the same line width. The bit line 111 may extend in any one direction while covering the barrier layer 110. The bit line 111 may extend in a linear shape.

[0124] As the contact plug 19B is etched, the bit line contact plug 19 may be formed on the source / drain region SD and may contact the source / drain region SD. As the contact plug 19B is etched, the plug spacer 18 may be removed. A gap 114 may be formed in a space where a portion of the plug spacer 18 and the contact plug 19B have been removed. The gap 114 may be formed on both sidewalls of the bit line contact plug 19. The gap 114 may be independently formed on both sidewalls of the bit line contact plug 19. A pair of gaps 114 may be separated by the bit line contact plug 19. The bit line contact plug 19 may interconnect the source / drain region SD with the bit line 111. The diameter of the bit line contact plug 19 may be smaller than the diameter of the contact plug 19B.

[0125] refer to Figure 6C , a bit line spacer 115 may be formed on both sidewalls of the bit line contact plug 19 and both sidewalls of the bit line structure BL. The bit line spacer 115 may have a columnar shape filling the gap 114. The bit line spacer 115 may prevent any material from filling the gap 114 in a subsequent process. The bit line spacer 115 may be independently formed on both sides of the bit line contact plug 19. The bit line spacer 115 may extend in a line shape. The top surface of the bit line spacer 115 may be at the same level as the top surface of the bit line structure BL.

[0126] The bit line spacer 115 may include an insulating material. The bit line spacer 115 may include a low-k material. The bit line spacer 115 may include an oxide or a nitride. The bit line spacer 115 may include, for example, silicon oxide, silicon nitride, or a metal oxide. The bit line spacer 115 may include SiO 2 、Si 3 N 4Or SiN. The bit line spacer 115 may include a multi-layer spacer. The bit line spacer 115 may include an air gap (not shown). Therefore, a pair of linear air gaps may be formed on both sidewalls of the bit line spacer 115. A pair of linear air gaps may be symmetrical to each other. According to one embodiment, the multi-layer spacer may include a first spacer, a second spacer, and a third spacer, and the third spacer may be located between the first spacer and the second spacer. The multi-layer spacer may include a NON structure in which an oxide spacer is located between nitride spacers. According to one embodiment, the multi-layer spacer may include a first spacer, a second spacer, and an air gap between the first spacer and the second spacer.

[0127] According to one embodiment, the gap 114 may be filled with a bit line contact insulating layer (not shown) instead of a bit line spacer 115. The top surface of the bit line contact insulating layer (not shown) may be at the same level as the top surface of the bit line contact plug 19. The bit line spacer 115 may be formed on the bit line contact insulating layer (not shown) and may contact the bit line contact insulating layer. The bit line contact insulating layer (not shown) may include an insulating material.

[0128] refer to Fig.6D , a bit line interlayer insulating layer (not shown) may be formed to fill the space between the bit line structures BL. The bit line interlayer insulating layer (not shown) may be planarized to expose the top of the bit line structure BL. The bit line interlayer insulating layer (not shown) may extend parallel to the bit line structure BL.

[0129] The bit line interlayer insulating layer (not shown) may be formed of a material having an etching selectivity to the bit line spacer 115. The bit line interlayer insulating layer (not shown) may include an insulating material. The bit line interlayer insulating layer (not shown) may include an oxide or a nitride. The bit line interlayer insulating layer (not shown) may include, for example, silicon oxide, silicon nitride, or metal oxide. The bit line interlayer insulating layer (not shown) may include SiO 2 、Si 3 N 4 or SiN. The bit line interlayer insulating layer (not shown) may include a spin-on insulating material (eg, spin-on dielectric (SOD)).

[0130] Subsequently, a storage node contact opening H may be formed in the bit line interlayer insulating layer (not shown). The storage node contact opening H may be formed by etching the bit line interlayer insulating layer (not shown) using a storage node contact opening mask (not shown) as an etching mask. The storage node contact opening H may be formed to be spaced apart from the bit line contact plug 19. The storage node contact opening mask (not shown) may include a photoresist pattern.

[0131] The storage node contact opening H may be formed between the bit line structures BL. The bottom surface of the storage node contact opening H may extend to the inside of the substrate 11. When forming the storage node contact opening H, the element isolation layer 13, the interlayer insulating layer 15, and the source / drain region SD may be recessed to a predetermined depth. The storage node contact opening H may expose a portion of the substrate 11. The bottom surface of the storage node contact opening H may be located at a level lower than the top surface of the substrate 11. The bottom surface of the storage node contact opening H may be at a level higher than the bottom surface of the bit line contact plug 19. The bottom surface of the storage node contact opening H may be at the same level as the bottom surface of the bit line contact plug 19. An leaching and trimming process may be performed to form the storage node contact opening H. The storage node contact opening H may be formed in the bit line spacer 115 without loss by the leaching process. The area of ​​the side surface and the bottom of the storage node contact opening H may be increased by a trimming process. The interlayer insulating layer 15 and a portion of the substrate 11 may be removed by a trimming process. The interlayer insulating layer 15 may be etched by dry etching. According to an embodiment, the interlayer insulating layer 15 may be etched by isotropic etching. Therefore, the source / drain region SD may be exposed through the storage node contact opening H. The lower portion of the storage node contact opening H may extend laterally, thereby forming a bulb shape.

[0132] refer to Fig. 6E , a storage node contact plug SNC may be formed in the storage node contact opening H. The storage node contact plug SNC may include a lower plug 116 , an ohmic contact layer 117 , a conductive liner 118 , and an upper plug 119 . The storage node contact plug SNC may be formed to be spaced apart from the bit line contact plug 19 .

[0133] First, a lower plug 116 may be formed in the storage node contact opening H. In order to form the lower plug 116, polysilicon may be deposited to fill the storage node contact opening H, and then a planarization process and an etch-back process may be sequentially performed. A bit line spacer 115 may be located between the bit line 111 and the lower plug 116. The bit line spacer 115 may be located between the bit line contact plug 19 and the lower plug 116. The bottom surface of the lower plug 116 may be connected to the source / drain region SD. The top surface of the lower plug 116 may be located at a level lower than the top surface of the bit line 111. The lower plug 116 may include a silicon-containing material. The lower plug 116 may be doped with impurities. For example, impurity doping may be performed by a doping process such as implantation. According to one embodiment, the lower plug 116 may include, for example, polysilicon.

[0134] The ohmic contact layer 117 may be formed on the lower plug 116 and may contact the lower plug 116. In order to form the ohmic contact layer 117, deposition and annealing of a silicided metal layer may be performed. The ohmic contact layer 117 may include a metal silicide. The ohmic contact layer 117 may include cobalt silicide (CoSi x According to one embodiment, the ohmic contact layer 117 may include CoSi 2 Therefore, low-resistance cobalt silicide can be formed while enhancing contact resistance.

[0135] The conductive liner 118 may be formed on the top surface of the ohmic contact layer 117 and some side surface portions of the bit line spacer 115 and may be in direct contact with the top surface of the ohmic contact layer 117 and some side surface portions of the bit line spacer 115. The conductive liner 118 may be omitted. The conductive liner 118 may include a metal or a metal nitride. The conductive liner 118 may include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), or a combination thereof. According to one embodiment, the conductive liner 118 may include titanium nitride.

[0136] The upper plug 119 may be formed on the conductive liner 118 and may be in contact with the conductive liner 118. The upper plug 119 may fill the remaining portion of the storage node contact opening H. The upper plug 119 may be formed, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In order to improve the deposition effect, the upper plug 119 may use plasma. For example, the upper plug 119 may be formed by, for example, plasma enhanced CVD (PECVD) or plasma enhanced ALD (PEALD). According to one embodiment, the upper plug 119 may be formed, for example, by chemical vapor deposition (CVD). The upper plug 119 may be planarized to expose the top surface of the bit line structure BL. Therefore, the top surface of the upper plug 119 and the top surface of the bit line structure BL may be at the same level.

[0137] The upper plug 119 may include a metal-containing material. The upper plug 119 may include a conductive material. The upper plug 119 may include one or more of gold (Au), silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), tungsten (W), titanium (Ti), platinum (Pt), palladium (Pd), tin (Sn), lead (Pb), zinc (Zn), indium (In), cadmium (Cd), chromium (Cr), and molybdenum (Mo). According to one embodiment, the upper plug 119 may include a material containing tungsten (W). The upper plug 119 may include tungsten (W).

[0138] refer to Fig. 6F, the landing pad layer 120A may be formed on the upper plug 119, the bit line spacer 115 and the bit line hard mask 112 and may be in direct contact with the upper plug 119, the bit line spacer 115 and the bit line hard mask 112. The landing pad layer 120A may include a metal-containing material. The landing pad layer 120A may be formed of a single film or a multilayer film. The landing pad layer 120A may include a conductive material. The landing pad layer 120A may include a metal-containing material. The landing pad layer 120A may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), tungsten (W), titanium (Ti), platinum (Pt), palladium (Pd), tin (Sn), lead (Pb), zinc (Zn), indium (In), cadmium (Cd), chromium (Cr) and molybdenum (Mo) One or more. According to one embodiment, the landing pad layer 120A may include a material containing tungsten (W). The landing pad layer 120A may include tungsten (W), PVD-W, or a tungsten compound.

[0139] A landing pad hard mask layer 121A and a landing pad mask 122 may be sequentially formed on the landing pad layer 120A. The landing pad hard mask layer 121A may include an insulating material. The landing pad mask 122 may include a photoresist pattern. The landing pad mask 122 may have a line shape extending in any one direction.

[0140] refer to Figure 6G , a landing pad hard mask 121 may be formed by etching a landing pad hard mask layer 121A using a landing pad mask 122 as an etching mask. A landing pad 120 may be formed by etching a landing pad layer 120A using a pad hard mask 121 as an etching mask. The landing pad 120 may partially overlap with the bit line structure BL. The landing pad 120 may be electrically connected to the upper plug 119. A landing pad hole LH may be formed in the upper plug 119. The shape of the landing pad hole LH may not be constant. The bottom surface of the landing pad hole LH may be at a higher level than the bottom surface of the bit line hard mask 112. The top of the upper plug 119 and the bit line spacer 115 may be exposed by etching a portion of the upper plug 119 using the landing pad hard mask 121 as an etching mask.

[0141] Subsequently, a capping layer 123A may be formed on the upper plug 119 and the landing pad 120 and may be in direct contact with the upper plug 119 and the landing pad 120. The capping layer 123A may cover the landing pad 120, the landing pad hard mask 121, the bit line spacer 115, the bit line hard mask 112, and the upper plug 119. The capping layer 123A may fill the landing pad hole LH. The height of the capping layer 123A may be greater than the sum of the height of the landing pad 120 and the height of the landing pad hard mask 121.

[0142] The capping layer 123A may include a material with poor step coverage. For example, the capping layer 123A may be formed using plasma chemical vapor deposition (PECVD). The capping layer 123A may include an insulating material. The capping layer 123A may include an oxide or a nitride. The capping layer 123A may include, for example, silicon oxide or silicon nitride. The capping layer 123A may include, for example, silicon nitride.

[0143] refer to Figure 6H , the cover layer 123A may be etched using a cover mask (not shown) as an etching mask. Thus, the unit cover layer 123 may be formed. As the cover layer 123A is etched, the top surface of the landing pad 120 may be partially etched. The top surface level of the unit cover layer 123 may be the same as the top surface level of the landing pad 120.

[0144] The cell cover layer 123 may fill the space between the upper plug 119 and the landing pad 120. The cell cover layer 123 may cover the top of the bit line spacer 115. The cell cover layer 123 may be planarized to expose the top surface of the landing pad 120. The cell cover layer 123 may extend parallel to the landing pad 120. The cell cover layer 123 may play a role in protecting the landing pad 120 from subsequent processes.

[0145] refer to Fig.6I , the etch stop layer 124 may be formed on the landing pad 120 and the cell cover layer 123 and may contact the landing pad 120 and the cell cover layer 123. The storage element 125 may be formed on the landing pad 120 and may contact the landing pad 120 to be electrically connected to the landing pad 120. The storage element 125 may be implemented in various shapes. The storage element 125 may be a capacitor. Therefore, the storage element 125 may include a storage node in contact with the landing pad 120.

[0146] The shape of the storage node may be cylindrical or columnar. The capacitor dielectric layer may be formed on the surface of the storage node and may be in contact with the surface of the storage node. The capacitor dielectric layer may include at least one selected from zirconium oxide, aluminum oxide, or hafnium oxide. For example, the capacitor dielectric layer may have a ZAZ structure in which a first zirconium oxide, an aluminum oxide, and a second zirconium oxide are stacked on each other. A plate node is formed on the capacitor dielectric layer. The storage node and the plate node may include a metal-containing material. The storage element 125 may include a variable resistor. The variable resistor may include a phase change material. According to one embodiment, the variable resistor may include a transition metal oxide. According to one embodiment, the variable resistor may be a magnetic tunnel junction (MTJ).

[0147] Figure 7It shows that for Fig.6I Steps along Figure 5 A cross-sectional view of the semiconductor device 300 taken along line AA′. Figure 7 The same reference numerals are used to represent Fig.6I Detailed description of repeated elements may be omitted.

[0148] refer to Figure 7 The bit line structure BL may be located on the bit line contact plug 19 and the interlayer insulating layer 15. The bit line structure BL may include a bit line contact plug 19, a barrier layer 110, a bit line 111, and a bit line hard mask 112. A cell capping layer 123 may be formed on the bit line structure BL and may directly contact the bit line structure BL.

[0149] The trench 21 may be located on both sidewalls of the bit line contact plug 19. The trench 21 may be located in the substrate 11 and aligned with both sidewalls of the bit line contact plug 19. A gate insulating layer 22, a gate electrode 23, and a gate capping layer 24 may be located within the trench 21.

[0150] The gate insulating layer 22 may be directly located on the surface of the trench 21 and the sidewall of the bit line contact plug 19. The gate insulating layer 22 may be located between the gate capping layer 24 and the bit line contact plug 19. The gate insulating layer 22 may have a shape vertically extending from the bottom surface of the trench 21.

[0151] The gate electrode 23 may be formed on the gate insulating layer 22 and may be in direct contact with the gate insulating layer 22. The gate electrode 23 may have a recessed shape, which means that it only partially fills the trench 21. The top surface of the gate electrode 23 may be at a lower level than the bottom surface of the bit line contact plug 19. The top surface of the gate electrode 23 may be at a lower level than the top surface of the active region 14. The remaining portion of the trench 21 on the gate electrode 23 may be filled with a gate capping layer 24. The top surface of the gate capping layer 24 may be at the same level as the top surface of the interlayer insulating layer 15.

[0152] The width 19WT of the top of the bit line contact plug 19 may be the same as the width 19WB of the bottom. The bit line contact plug 19 may be adjacent to the gate electrode 23 and the gate cap layer 24, with the gate insulating layer 22 interposed therebetween. The bit line contact plug 19 may directly contact the gate insulating layer 22. The sidewall of the bit line contact plug 19 may be self-aligned with the gate insulating layer 22. The shape of the bit line contact plug 19 may be a rectangular column. The bit line contact plug 19 may correspond to Figure 5 The bottom surface of the bit line contact plug BLC may be as shown in FIG. Figure 7 Shown bent, however the bit line contact plug is not limited to this configuration.

[0153] A short defect between the bit line contact plug 19 and the gate electrode 23 may be alleviated by the gate insulating layer 22. Therefore, the characteristics of the semiconductor device may be enhanced.

[0154] Figure 8 is a cross-sectional view showing a semiconductor device 400 according to an embodiment of the present disclosure. Figure 8 is along Figure 5 A cross-sectional view taken along line AA′. Figure 8 The semiconductor device 400 may be similar to Figure 7 The semiconductor device 300. Figure 8 In the present invention, the same reference numerals are used to represent 4A to 4D and FIG. 6A to FIG. 6I Detailed description of repeated elements may be omitted.

[0155] First, we can combine the above 4A to 4D The gate insulating layer 32, the gate electrode 33 and the gate capping layer 34 are formed in the trench 31 by the method described above. FIG. 6A to FIG. 6I The method described is to form a bit line structure BL, a storage node contact (not shown), a landing pad (not shown), and a storage element (not shown). The bit line structure BL may include a bit line contact plug 19', a barrier layer 110, a bit line 111, and a bit line hard mask 112. A cell capping layer 123 may be formed on the bit line structure BL and may contact the bit line structure BL.

[0156] refer to Figure 8 The bit line structure BL may be located on the bit line contact plug 19 ′ and the interlayer insulating layer 15 . The trench 31 may be located on both sidewalls of the bit line contact plug 19 ′. The gate insulating layer 32 , the gate electrode 33 , and the gate capping layer 34 may be located inside the trench 31 .

[0157] The gate insulating layer 32 may be formed on and may be in direct contact with the surface of the trench 31 and the sidewall of the bit line contact plug 19'. The gate insulating layer 32 may have a shape vertically extending from the bottom surface of the trench 31. The gate insulating layer 32 may be located between the gate capping layer 34 and the bit line contact plug 19'.

[0158] The gate electrode 33 may be formed on the gate insulating layer 32 and may be in direct contact with the gate insulating layer 32. The gate electrode 33 may have a recessed shape, which means that it only partially fills the trench 31. The top surface of the gate electrode 33 may be at a level lower than the bottom surface of the bit line contact plug 19'. The top surface of the gate electrode 33 may be located at a level lower than the top surface of the active region 14. The remaining portion of the trench 31 above the gate electrode 33 may be filled with a gate capping layer 34. The top surface of the gate capping layer 34 may be at the same level as the top surface of the interlayer insulating layer 15.

[0159] The width 19WT′ of the top of the bit line contact plug 19 may be greater than the width 19WB′ of the bottom. The bottom spacer RS ​​may be located on the lower outer wall of the bit line contact plug 19′. The bottom spacer RS ​​may be located on the outer wall of the bit line contact plug 19′ in a region narrower than the width 19WT′ of the top of the bit line contact plug 19′ and wider than the width 19WB′ of the bottom. The bottom spacer RS ​​may be located between the trench 31 and the bottom edge of the bit line contact plug 19′. The bottom spacer RS ​​may have a shape surrounding the lower outer wall of the bit line contact plug 19′. From a top view, the bottom spacer RS ​​may have an annular shape. The thickness of the bottom spacer RS ​​may increase from a higher level to a lower level. The bottom surface of the bottom spacer RS ​​may be located at a level higher than the bottom surface of the bit line contact plug 19′.

[0160] The bit line contact plug 19' may be adjacent to the gate electrode 33 and the gate capping layer 34, with the gate insulating layer 32 interposed therebetween. The bit line contact plug 19' may directly contact the gate insulating layer 32. The sidewall of the bit line contact plug 19' may be self-aligned with the gate insulating layer 32. The bit line contact plug 19' may directly contact the bottom spacer RS. The bit line contact plug 19' may be adjacent to the gate insulating layer 32, with the bottom spacer RS ​​interposed therebetween.

[0161] The short circuit defect between the bit line contact plug 19' and the gate electrode 33 can be alleviated by the gate insulating layer 32. Since the bottom spacer RS ​​is formed on the lower outer wall of the bit line contact plug 19', the short circuit defect between the bit line contact plug 19' and the gate electrode 33 can be further alleviated. Therefore, the characteristics of the semiconductor device can be enhanced.

[0162] Fig. 9A and Fig. 9B is a cross-sectional view showing a top view of a semiconductor device according to an embodiment of the present disclosure. Fig. 9B yes Fig. 9A A magnified view of part Q. Fig. 9A and Fig. 9B The semiconductor device 500 may be similar to Figure 5The semiconductor device 300. Fig. 9A and Fig. 9B In the drawings, the same reference numerals denote Figure 5 Detailed description of repeated elements may be omitted.

[0163] refer to Fig. 9A The semiconductor device 500 may include a plurality of memory cells. Each memory cell may include an active region 104, a gate structure BG, a bit line contact plug BLC, a plug spacer SP, a bit line structure BL, a storage node contact plug (not shown), and a storage element 125.

[0164] Each memory cell may include a first trench TC1 and a second trench TC2 formed in a substrate and spaced apart from each other. The first trench TC1 may be filled with a first gate structure BG1. The second trench TC2 may be filled with a second gate structure BG2.

[0165] Each gate structure BG may include a gate insulating layer GP, a gate electrode GE, and a gate capping layer (not shown). Each bit line structure BL may include a bit line 111, a bit line spacer 115, and a bit line contact plug BLC. Each memory cell may include a storage node contact plug (not shown) and a landing pad 120 on the storage node contact plug (not shown).

[0166] refer to Fig. 9B , one side wall of the bit line contact plug BLC may be self-aligned with the gate structure BG. The shape of the bit line contact plug BLC may be a rectangular column. The bit line contact plug BLC may include a first side surface in contact with the first gate structure BG1 and a second side surface in contact with the second gate structure BG2. The first side surface may be in contact with the first gate insulating layer included in the first gate structure BG1, and the second side surface may be in contact with the second gate insulating layer included in the second gate structure BG2. The first side surface and the second side surface may be parallel to each other. The first side surface and the second side surface may have a vertical shape. The first side surface and the second side surface may have an inclined shape.

[0167] The plug spacer SP may be located below the bit line spacer 115. The plug spacer SP may include a pair of side walls facing each other and located on both sides of the bit line contact plug BLC. The plug spacer SP may include a pair of curved or arcuate side walls facing each other. The plug spacer SP may be located in a direction intersecting the first gate structure BG1 and the second gate structure BG2. The plug spacer SP may not overlap the first gate structure BG1 and the second gate structure BG2. The plug spacer SP may be adjacent to the storage node contact plug (not shown). The thickness of the plug spacer SP may be less than the thickness of the bit line spacer 115. The plug spacer SP may correspond to the plug spacer SP of FIG. 1.

[0168] The plug spacer SP may be located below the bit line spacer 115. The plug spacer SP may include a pair of side walls facing each other and located on both sides of the bit line contact plug BLC. The plug spacer SP may include a pair of curved or arcuate side walls facing each other. The plug spacer SP may be located in a direction intersecting the first gate structure BG1 and the second gate structure BG2. The plug spacer SP may not overlap the first gate structure BG1 and the second gate structure BG2. The plug spacer SP may be adjacent to the storage node contact plug (not shown). The thickness of the plug spacer SP may be less than the thickness of the bit line spacer 115. The plug spacer SP may correspond to the plug spacer SP of FIG. 1.

[0169] refer to Fig. 10A , a barrier metal layer (not shown), a bit line layer (not shown), a bit line hard mask layer (not shown), and a bit line mask (not shown) may be formed on the interlayer insulating layer 15 and the contact plug 19B. The bit line hard mask layer (not shown), the bit line layer (not shown), the barrier metal layer (not shown), and the contact plug 19B may be etched using the bit line mask (not shown) as an etching mask. Thus, a bit line structure BL including a bit line contact plug 19, a barrier layer 110, a bit line 111, and a bit line hard mask 112 may be formed. The bit line contact plug 19, the barrier layer 110, the bit line 111, and the bit line hard mask 112 may have the same line width.

[0170] As the contact plug 19B is etched, a bit line contact plug 19 may be formed on the source / drain region SD. As the contact plug 19B is etched, the plug spacer 18 may not be removed. There may be a pair of plug spacers 18, which face each other and are located on both sides of the bit line contact plug 19. The plug spacer 18 may not directly contact the bit line contact plug 19. The plug spacer 18 may not overlap with the gate electrode (not shown). The plug spacer 18 may not overlap with the trench (not shown). The plug spacer 18 may be formed to extend in a direction parallel to the bit line 111. The top view of the plug spacer 18 may have a curved or arc shape. The sidewall profile of the plug spacer 18 may have an inclined shape. The plug spacer 18 may correspond to the plug spacer SP of Figure 1. The plug spacer 18 may further include a bottom spacer.

[0171] A gap 114' may be formed in a space in which a portion of the contact plug 19B has been removed. The gap 114' may be formed on both sidewalls of the bit line contact plug 19. The gap 114' may be formed between the bit line contact plug 19 and the plug spacer 18. The gap 114' may be independently formed on both sidewalls of the bit line contact plug 19. A pair of gaps 114' may be separated by the bit line contact plug 19. The diameter of the bit line contact plug 19 may be smaller than the diameter of the contact plug 19B.

[0172] refer to Fig. 10B , the bit line spacer 115 may be formed on both sidewalls of the bit line contact plug 19 and both sidewalls of the bit line structure BL. The bit line spacer 115 may have a columnar shape filling the gap 114'. According to one embodiment, the gap 114' may be filled with a bit line contact insulating layer (not shown) instead of the bit line spacer 115. In this case, the bit line spacer 115 may be formed on the bit line contact insulating layer (not shown) and may contact the bit line contact insulating layer (not shown). The bit line spacer 115 may include a multi-layer spacer. The bit line spacer 115 may include an air gap (not shown).

[0173] Subsequently, a storage node contact opening H may be formed between the bit line structures BL. A bottom surface of the storage node contact opening H may extend to the inside of the substrate 11. A portion of the substrate 11 may be exposed by the storage node contact opening H. A lower portion of the storage node contact opening H may extend laterally, thereby forming a bulb shape.

[0174] refer to Fig. 10C, a storage node contact plug SNC may be formed in the storage node contact opening H. The storage node contact plug SNC may include a lower plug 116, an ohmic contact layer 117, a conductive liner 118, and an upper plug 119. The storage node contact plug SNC may be adjacent to the plug spacer 18. The storage node contact plug SNC may be spaced apart from the bit line contact plug 19 and connected to the substrate 11. The storage node contact plug SNC may be spaced apart from the bit line contact plug 19 and a gate electrode (not shown) and connected to the substrate 11.

[0175] refer to Fig. 10D The landing pad 120 may be formed on the bit line structure BL to partially overlap the bit line structure BL. The landing pad 120 may be electrically connected to the upper plug 119.

[0176] Subsequently, a cell capping layer 123 may be formed to cover a portion of the bit line structure BL, a sidewall of the landing pad 120, and a top surface of the upper plug 119. The cell capping layer 123 may fill a space between the upper plug 119 and the landing pad 120.

[0177] The etch stop layer 124 may be formed on and in contact with the landing pad 120 and the cell cover layer 123. The storage element may be formed on the landing pad 120 and may be in contact with the landing pad 120 to be electrically connected to the landing pad 120. The storage element 125 may be implemented in various shapes. The storage element 125 may be a capacitor. Therefore, the storage element 125 may include a storage node in contact with the landing pad 120.

[0178] Along Fig. 9A The cross-sectional view of the semiconductor device 500 taken along line AA′ may be Figure 7 The same ones.

[0179] refer to Figure 7 , the bit line structure BL may be located on the bit line contact plug 19 and the interlayer insulating layer 15. The width 19WT of the top portion of the bit line contact plug 19 may be the same as the width 19WB of the bottom portion. The bit line contact plug 19 may directly contact the gate insulating layer 22. The sidewall of the bit line contact plug 19 may be self-aligned with the gate insulating layer 22. The shape of the bit line contact plug 19 may be a rectangular column. The bit line contact plug 19 may correspond to Fig. 9A The bit line contact plug BLC.

[0180] The short-circuit defect between the bit line contact plug 19 and the gate electrode 23 can be alleviated by the gate insulating layer 22. Since a pair of plug spacers 18 located on both sides of the bit line contact plug 19 and facing each other are retained, the short-circuit defect caused by the bit line contact plug 19' can be further alleviated. Therefore, the characteristics of the semiconductor device can be enhanced.

[0181] Along Fig. 9A The cross-sectional view of the semiconductor device taken along line AA′ may be Figure 8 First, the above combination 4A to 4D The gate insulating layer 32, the gate electrode 33 and the gate capping layer 34 are formed by the method described above. FIG. 10A to FIG. 10D The method is described to form a bit line structure BL, a storage node contact (not shown), a landing pad (not shown), and a memory element (not shown).

[0182] like Figure 8 As shown, the width 19WT' of the top portion of the bit line contact plug 19' may be greater than the width 19WB' of the bottom portion. The bottom spacer RS ​​may have a shape surrounding the lower outer wall of the bit line contact plug 19'. From a top view, the bottom spacer RS ​​may have a ring shape. The thickness of the bottom spacer RS ​​may increase from a higher level to a lower level.

[0183] According to one embodiment, the plug spacer (not shown) may include a bottom spacer RS. The bottom spacer RS ​​may be connected to the plug spacer (not shown). The bit line contact plug 19' may directly contact the bottom spacer RS. The bit line contact plug 19' may not directly contact the plug spacer (not shown).

[0184] The bit line contact plug 19' may directly contact the gate insulating layer 32. A sidewall of the bit line contact plug 19' may be self-aligned with the gate insulating layer 32. The bit line contact plug 19' may be adjacent to the gate insulating layer 32 with a bottom spacer RS ​​interposed therebetween.

[0185] The short circuit defect between the bit line contact plug 19' and the gate electrode 33 can be alleviated by the gate insulating layer 32. Since the bottom spacer RS ​​is formed on the lower outer wall of the bit line contact plug 19', the short circuit defect between the bit line contact plug 19' and the gate electrode 33 can be alleviated. Since a pair of plug spacers 18 located on both sides of the bit line contact plug 19 and facing each other are retained, the short circuit defect caused by the bit line contact plug 19' can be further alleviated. Therefore, the characteristics of the semiconductor device can be enhanced.

[0186] Those skilled in the art will recognize that the various embodiments of the present disclosure as described above are not limited to those shown in the above embodiments and drawings, but may be variously changed, modified or altered without departing from the spirit and scope of the present invention as defined in the appended claims.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: forming a contact hole in a substrate; filling the contact hole with a plug material; forming a contact plug by etching the plug material; forming a trench by etching the substrate to align with the sidewall of the contact plug, the trench exposing the sidewall of the contact plug; forming a gate insulating layer on the exposed sidewalls of the contact plug and the surface of the trench; as well as A gate electrode is formed on the gate insulating layer, the gate electrode partially filling the trench.

2. The method according to claim 1, further comprising: Before filling the contact hole with the plug material, forming a pre-spacer covering a sidewall of the contact hole; as well as The substrate exposed in the contact hole is further recessed using the pre-spacer.

3. The method according to claim 2, wherein: The step of forming the trench includes forming a plug spacer by cutting the pre-spacer, the plug spacer covering an unexposed sidewall of the contact plug.

4. The method according to claim 3, wherein: The plug spacer further includes a bottom spacer located between the trench and a bottom edge of the contact plug.

5. The method according to claim 4, wherein: The bottom spacer has a shape surrounding a lower outer wall of the contact plug.

6. The method according to claim 1, wherein: The steps of forming the contact plug and forming the trench are simultaneously performed using one line mask.

7. The method according to claim 1, wherein: The groove comprises a pair of linear grooves, and wherein: The pair of line-shaped trenches are self-aligned with the exposed sidewalls of the contact plug.

8. The method according to claim 1, wherein: The step of forming the contact hole comprises: forming an interlayer insulating layer on the substrate; forming an etching mask on the interlayer insulating layer; and The interlayer insulating layer and the substrate are etched using the etch mask.

9. The method according to claim 1, further comprising: Before forming the contact hole in the substrate, an element isolation layer defining an active region in the substrate is formed, wherein the trench has a line shape intersecting the active region and the element isolation layer.

10. The method according to claim 1, wherein: A bottom surface of the trench is at a lower level than a bottom surface of the contact plug.

11. The method according to claim 1, wherein: The gate insulating layer is formed by oxidizing the exposed sidewalls of the contact plug and the surface of the trench.

12. The method according to claim 1, wherein: A width of a top portion of the contact plug is the same as a width of a bottom portion of the contact plug.

13. The method according to claim 1, wherein: A width of a top portion of the contact plug is greater than a width of a bottom portion of the contact plug.

14. The method according to claim 1, wherein: The exposed sidewall of the contact plug has a straight profile, and wherein the unexposed sidewall of the contact plug has a curved or arcuate profile.

15. The method according to claim 1, wherein: The plug material includes polysilicon.

16. The method according to claim 1, wherein: A top surface of the gate electrode is at a lower level than a bottom surface of the contact plug.

17. A method for manufacturing a semiconductor device, the method comprising: forming a contact hole in a substrate; forming a plug material filling the contact hole; forming a bit line contact plug by etching the plug material; forming a gate trench by etching the substrate so as to be self-aligned with a sidewall of the bit line contact plug, wherein the gate trench exposes the sidewall of the bit line contact plug; forming a buried gate structure filling the gate trench; as well as A bit line is formed on the bit line contact plug.

18. The method according to claim 17, wherein: The steps of forming the buried gate structure include: forming a gate insulating layer by oxidizing the exposed sidewalls of the bit line contact plug and the surface of the gate trench; and A buried gate electrode is formed on the gate insulating layer such that the buried gate electrode partially fills the gate trench.

19. The method according to claim 17, further comprising: Before forming the plug material, forming a pre-spacer covering a sidewall of the contact hole; as well as further recessing the substrate exposed in the contact hole using the pre-spacer, The step of forming the gate trench includes: forming a plug spacer by cutting the pre-spacer, wherein the plug spacer covers the unexposed sidewall of the bit line contact plug.

20. The method according to claim 17, wherein: The step of forming the contact hole comprises: forming an interlayer insulating layer on the substrate; forming an etching mask on the interlayer insulating layer; and The interlayer insulating layer and the substrate are etched using the etch mask.

21. A semiconductor device comprising: substrate; A bit line contact plug located in the substrate; a trench located in the substrate and aligned with a sidewall of the bit line contact plug; a gate insulating layer formed on a surface of the trench and on the sidewalls of the bit line contact plug; as well as a gate electrode partially filling the trench on the gate insulating layer, Wherein, the gate insulating layer includes a first oxide, and Wherein, the top surface of the gate insulation layer and the top surface of the bit line contact plug are located at the same level.

22. The semiconductor device according to claim 21, wherein The gate insulating layer further includes a second oxide, and Wherein, the second oxide extends from the first oxide.

23. The semiconductor device according to claim 22, wherein: The first oxide and the second oxide include the same material.

24. The semiconductor device according to claim 22, wherein: The first oxide and the second oxide include silicon oxide.

25. The semiconductor device according to claim 21, wherein A top surface of the gate electrode is at a lower level than a bottom surface of the bit line contact plug.

26. The semiconductor device according to claim 21, further comprising: A gate capping layer is located on the gate electrode and fills the trench, wherein the gate insulating layer extends to be located between the gate capping layer and the bit line contact plug.

27. The semiconductor device according to claim 21, further comprising: an interlayer insulating layer on the substrate, The bit line contact plug and the trench penetrate the interlayer insulating layer and extend to the interior of the substrate.

28. The semiconductor device according to claim 21, further comprising: a storage node contact plug spaced apart from the bit line contact plug and the gate electrode and connected to the substrate; as well as A plug spacer does not overlap the trench and is adjacent to the storage node contact plug.

29. The semiconductor device according to claim 21, further comprising: A bottom spacer is located between the trench and a bottom edge of the bit line contact plug.

30. The semiconductor device according to claim 29, wherein The bottom spacer has a shape surrounding a lower outer wall of the bit line contact plug.

31. A semiconductor device comprising: a substrate including an active region; a first trench and a second trench, the first trench and the second trench being spaced apart from each other and extending in the substrate; A bit line contact plug located between the first trench and the second trench and formed in the substrate; a first gate insulating layer formed on a surface of the first trench and one sidewall of the bit line contact plug; a second gate insulating layer formed on a surface of the second trench and another sidewall of the bit line contact plug; a first gate electrode partially filling the first trench on the first gate insulating layer; as well as a second gate electrode partially filling the second trench on the second gate insulating layer, The first gate insulating layer includes an oxide on a side wall of the bit line contact plug, and Wherein, the second gate insulating layer includes an oxide of the other side wall of the bit line contact plug, The top surfaces of the first gate insulating layer and the second gate insulating layer are respectively located at the same level as the top surface of the bit line contact plug.

32. The semiconductor device according to claim 31, wherein The first gate insulating layer further includes an oxide of the substrate, the oxide of the substrate extending from the oxide of the one sidewall of the bit line contact plug, and The second gate insulating layer further comprises an oxide of the substrate, and the oxide of the substrate extends from the oxide of the other side wall of the bit line contact plug.

33. The semiconductor device according to claim 31, wherein Top surfaces of the first gate electrode and the second gate electrode are located at a lower level than a bottom surface of the bit line contact plug.

34. The semiconductor device according to claim 31, further comprising: a first gate capping layer, which is located on the first gate electrode and fills the first trench; as well as a second gate capping layer, which is located on the second gate electrode and fills the second trench; wherein the first gate insulating layer extends to be located between the first gate covering layer and the bit line contact plug, and The second gate insulating layer extends to be located between the second gate covering layer and the bit line contact plug.

35. The semiconductor device according to claim 31, further comprising: a storage node contact plug, which is spaced apart from the bit line contact plug, the first gate electrode and the second gate electrode, and the storage node contact plug is connected to the substrate; as well as A plug spacer does not overlap the first trench and the second trench, and the plug spacer is adjacent to the storage node contact plug.

36. The semiconductor device according to claim 31, further comprising: A bottom spacer is located between the first trench and a bottom edge of the bit line contact plug and between the second trench and the bottom edge of the bit line contact plug.

37. The semiconductor device according to claim 36, wherein: The bottom spacer has a shape surrounding a lower outer wall of the bit line contact plug.

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