Buck circuit and amplifier
By using the comparison voltage VB and ground voltage VSS in the step-down circuit and using the zero temperature coefficient current, the problem of complex structure and uncertain accuracy of the step-down circuit in the prior art is solved, and the high-precision step-down effect is achieved .
Patent Information
- Application Number
- CN202111546682.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-12-16
- Publication Date
- 2024-12-31
- Estimated Expiration
- 2041-12-16
AI Technical Summary
The existing step-down circuit has complex structures, high cost, and the step-down accuracy is easily affected by the process, resulting in uncertainty.
A step-down circuit including a switching tube, a voltage circuit and a control circuit is designed. By comparing the voltage VB with the ground voltage VSS, the zero-temperature coefficient current is used to achieve precise step-down to avoid process influence.
The accuracy of the buck circuit is improved, ensuring that the output voltage is not less than the ground voltage VSS, reducing costs and enhancing the stability of the circuit.
Smart Images
Figure CN114221541B_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of integrated circuits, and in particular to a step-down circuit and an amplifier. Background Art
[0002] The buck circuit is one of the commonly used circuit structures in amplifiers. The existing buck circuit has a complex structure and high cost. At the same time, the buck size is easily affected by the process, which brings uncertainty to the accuracy of the buck of the entire circuit.
[0003] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention
[0004] The object of the present invention is to provide a step-down circuit and an amplifier, the step-down accuracy of which is not affected by the process.
[0005] To achieve the above objective, an embodiment of the present invention provides a step-down circuit, including: a switch tube, a voltage circuit and a control circuit.
[0006] The switch tube is connected to the ground voltage VSS and the output terminal VOUT; the voltage circuit receives a zero temperature coefficient current and provides a comparison voltage VB at the same time; the control circuit is connected between the ground voltage VSS and the voltage circuit and is also connected to the switch tube; when the local voltage VSS is less than the comparison voltage VB, the output terminal VOUT outputs the comparison voltage VB, and when the local voltage VSS is greater than the comparison voltage VB, the control circuit controls the switch tube to be turned on through the control terminal VGN, and the output terminal VOUT outputs the ground voltage VSS.
[0007] In one or more embodiments of the present invention, the switch tube is an NMOS tube MN, the source of the NMOS tube MN is connected to the ground voltage VSS, the gate of the NMOS tube MN is connected to the control terminal VGN, and the drain of the NMOS tube MN is connected to the output terminal VOUT.
[0008] In one or more embodiments of the present invention, the voltage circuit includes an NMOS tube M3, an NMOS tube M4 and a resistor R1, the source of the NMOS tube M3 is connected to one end of the resistor R1 and receives a zero temperature coefficient current at the same time, the other end of the resistor R1 is connected to the source of the NMOS tube M4, the gate of the NMOS tube M3 is connected to the output end VOUT, and the gate of the NMOS tube M4 is connected to the input end VIN.
[0009] In one or more embodiments of the present invention, the comparison voltage VB=VIN-IM4*R1, wherein VIN is the voltage inputted by the input terminal VIN, and IM4 is the zero temperature coefficient current flowing through the resistor R1.
[0010] In one or more embodiments of the present invention, the control circuit includes a current mirror, a current source I1, a PMOS tube M5 and a PMOS tube M6, the current mirror is connected to the ground voltage VSS and the voltage circuit, the drain of the PMOS tube M5 is connected to the gate and one end of the current source I1 and the current mirror, the source of the PMOS tube M5 is connected to the other end of the current source I1 and the power supply voltage VDD, the gate of the PMOS tube M6 is connected to the gate of the PMOS tube M5, the source of the PMOS tube M6 is connected to the power supply voltage VDD, and the drain of the PMOS tube M6 is connected to the control terminal VGN.
[0011] In one or more embodiments of the present invention, the current mirror includes an NMOS tube M1 and an NMOS tube M2, the source of the NMOS tube M1 is connected to the source of the NMOS tube M2 and connected to the ground voltage VSS, the gate of the NMOS tube M1 is connected to the gate of the NMOS tube M2, the drain of the NMOS tube M1 is connected to the drain of the PMOS tube M5, and the drain of the NMOS tube M2 is connected to the voltage circuit.
[0012] In one or more embodiments of the present invention, the step-down circuit further includes a zero temperature coefficient current circuit for generating a zero temperature coefficient current, and the zero temperature coefficient current circuit is connected between the ground voltage VSS and the control circuit.
[0013] In one or more embodiments of the present invention, the zero temperature coefficient current circuit includes an amplifier OPA0, an NMOS tube M0, a resistor R0, a first current mirror and a second current mirror, the positive input terminal of the amplifier OPA0 is connected to the reference voltage VREF, the negative input terminal of the amplifier OPA0 is grounded through the resistor R0, the negative input terminal of the amplifier OPA0 is connected to the source of the NMOS tube M0, the gate of the NMOS tube M0 is connected to the output terminal of the amplifier OPA0, the drain of the NMOS tube M0 is connected to the first current mirror, the first current mirror is connected to the second current mirror, and the second current mirror is connected to the ground voltage VSS and the control circuit.
[0014] In one or more embodiments of the present invention, the first current mirror includes a PMOS tube MS0 and a PMOS tube MS1, the second current mirror includes an NMOS tube MS2 and an NMOS tube MS3, the drain and gate of the PMOS tube MS0 are connected and connected to the drain of the NMOS tube M0 and the gate of the PMOS tube MS1, the source of the PMOS tube MS0 is connected to the power supply voltage VDD, the source of the PMOS tube MS1 is connected to the power supply voltage VDD, the drain of the PMOS tube MS1 is connected to the drain and gate of the NMOS tube MS2 and the gate of the NMOS tube MS3, the source of the PMOS tube MS2 is grounded, the drain of the PMOS tube MS3 is connected to the control circuit, and the source of the PMOS tube MS3 is grounded.
[0015] The present invention also provides an amplifier, comprising the above-mentioned step-down circuit.
[0016] Compared with the prior art, the buck circuit and amplifier according to the embodiment of the present invention compare the comparison voltage VB with the ground voltage VSS. When the comparison voltage VB is not lower than the ground voltage VSS, the output terminal VOUT outputs a higher voltage between the comparison voltage VB and the ground voltage VSS. The comparison voltage VB is mainly affected by the zero temperature coefficient voltage, thereby avoiding the influence of the process, achieving precise voltage reduction, and improving accuracy. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 is a circuit schematic diagram of a step-down circuit according to an embodiment of the present invention;
[0018] Figure 2 is a circuit schematic diagram of a zero temperature coefficient current circuit according to an embodiment of the present invention;
[0019] Figure 3 is a system block diagram of an amplifier OPA according to an embodiment of the present invention. DETAILED DESCRIPTION
[0020] The specific implementation modes of the present invention are described in detail below in conjunction with the accompanying drawings, but it should be understood that the protection scope of the present invention is not limited by the specific implementation modes.
[0021] Unless explicitly stated otherwise, throughout the specification and claims, the term “comprise” or variations such as “include” or “comprising”, etc., will be understood to include the stated elements or components but not to exclude other elements or components.
[0022] Example 1
[0023] like Figure 1 As shown, the buck circuit includes: a switch tube, a zero temperature coefficient current circuit 10 , a voltage circuit 20 and a control circuit 30 .
[0024] The switch tube is connected to the ground voltage VSS and the output terminal VOUT. The zero temperature coefficient current circuit 10, the voltage circuit 20 and the control circuit 30 are connected in sequence. The zero temperature coefficient current circuit 10 is also connected to the ground voltage VSS. The voltage circuit 20 is also connected to the internal circuit 40 of the amplifier OPA. The voltage circuit 20 receives the zero temperature coefficient current generated by the zero temperature coefficient current circuit 10, and provides a comparison voltage VB at the same time. The control circuit 30 is used to control the on and off of the switch tube. When the local voltage VSS is less than the comparison voltage VB, the output terminal VOUT outputs the comparison voltage VB. When the local voltage VSS is greater than the comparison voltage VB, the control circuit controls the switch tube to turn on through the control terminal VGN, and the output terminal VOUT outputs the ground voltage VSS, thereby ensuring that the voltage output by the output terminal VOUT is not less than the ground voltage VSS.
[0025] like Figure 1 As shown, the switch tube is an NMOS tube MN, the source of the NMOS tube MN is connected to the ground voltage VSS, the gate of the NMOS tube MN is connected to the control terminal VGN and connected to the internal circuit 40 of the amplifier OPA through the control terminal VGN, and the drain of the NMOS tube MN is connected to the output terminal VOUT. The buck circuit is a part of the amplifier OPA, wherein the internal circuit 40 of the amplifier OPA is composed of a plurality of connected NMOS tubes and PMOS tubes, and the internal circuit 40 is used to maintain the operation of the buck circuit and other circuits.
[0026] like Figure 2 and Figure 1 As shown, the zero temperature coefficient current circuit 10 includes an amplifier OPA0, an NMOS tube M0, a resistor R0, a first current mirror and a second current mirror. The positive input terminal of the amplifier OPA0 is connected to the reference voltage VREF, the negative input terminal of the amplifier OPA0 is grounded through the resistor R0, the negative input terminal of the amplifier OPA0 is connected to the source of the NMOS tube M0, and the gate of the NMOS tube M0 is connected to the output terminal of the amplifier OPA0. The drain of the NMOS tube M0 is connected to the first current mirror, the first current mirror is connected to the second current mirror, and the second current mirror is connected to the ground voltage VSS and the control circuit 30.
[0027] Wherein, the first current mirror includes PMOS tube MS0 and PMOS tube MS1, and the second current mirror includes NMOS tube MS2 and NMOS tube MS3. The drain and gate of PMOS tube MS0 are connected and connected to the drain of NMOS tube M0 and the gate of PMOS tube MS1, and the source of PMOS tube MS0 is connected to the power supply voltage VDD. The source of PMOS tube MS1 is connected to the power supply voltage VDD, and the drain of PMOS tube MS1 is connected to the drain and gate of NMOS tube MS2 and the gate of NMOS tube MS3. The source of PMOS tube MS2 is grounded, the drain of PMOS tube MS3 is connected to the control circuit 30 through the VS2 terminal, and the source of PMOS tube MS3 is grounded. The zero temperature coefficient current is equal to the reference voltage VREF divided by the resistance value of resistor R0. The zero temperature coefficient current flows to the voltage circuit 20 through the VS2 terminal.
[0028] like Figure 1 As shown, the voltage circuit 20 includes an NMOS tube M3, an NMOS tube M4 and a resistor R1. The source of the NMOS tube M3 is connected to one end of the resistor R1 and receives a zero temperature coefficient current at the same time. Specifically, the source of the NMOS tube M3 is connected to one end of the resistor R1 and is connected to the control circuit 30 through the VD2 terminal. The other end of the resistor R1 is connected to the source of the NMOS tube M4, the gate of the NMOS tube M3 is connected to the output terminal VOUT, and the gate of the NMOS tube M4 is connected to the input terminal voltage VIN. Both the NMOS tube M3 and the NMOS tube M4 use NMOS tubes, which realizes rail-to-rail input and reduces circuit cost.
[0029] Comparison voltage VB = V IN -IM4*R1, where V IN is the voltage input to the input terminal VIN, and IM4 is the zero temperature coefficient current flowing through the resistor R1. The zero temperature coefficient current is determined by the reference voltage VREF and the resistor R0. That is, the voltage on the resistor R1 is mainly affected by the reference voltage VREF, so that accurate reduction can be achieved, avoiding process influence and improving accuracy.
[0030] like Figure 1As shown, the control circuit 30 includes a current mirror, a current source I1, a PMOS tube M5 and a PMOS tube M6. The current mirror is connected to the ground voltage VSS and the voltage circuit 20. In this embodiment, a zero temperature coefficient current circuit 10 is connected between the current mirror and the ground voltage VSS. The current mirror is connected to the zero temperature coefficient current circuit 10 through the VS2 terminal, and the current mirror is connected to the voltage circuit 20 through the VD2 terminal. The drain of the PMOS tube M5 is connected to the gate, one end of the current source I1 and the current mirror, and the source of the PMOS tube M5 is connected to the other end of the current source I1 and the power supply voltage VDD. The gate of the PMOS tube M6 is connected to the gate of the PMOS tube M5, the source of the PMOS tube M6 is connected to the power supply voltage VDD, and the drain of the PMOS tube M6 is connected to the gate of the NMOS tube MN through the control terminal VGN.
[0031] The current mirror includes an NMOS tube M1 and an NMOS tube M2. The source of the NMOS tube M1 is connected to the source of the NMOS tube M2 and to the ground voltage VSS. In this embodiment, the source of the NMOS tube M1 is connected to the source of the NMOS tube M2 and a zero temperature coefficient current circuit 10 is connected between the source of the NMOS tube M1 and the ground voltage VSS, that is, the source of the NMOS tube M1 is connected to the source of the NMOS tube M2 and connected to the drain of the NMOS tube MS3 through the VS2 terminal. The gate of the NMOS tube M1 is connected to the gate of the NMOS tube M2 and forms the VG2 terminal. The drain of the NMOS tube M1 is connected to the drain of the PMOS tube M5 and forms the VG5 terminal. The drain of the NMOS tube M2 is connected to the resistor R1 and the source of the NMOS tube M3 through the VD2 terminal.
[0032] According to the above step-down circuit, when the local voltage VSS is less than the comparison voltage VB, by setting the current of the current source I1 to be less than the current passing through the NMOS tube M1, the VG5 terminal is a high voltage, the PMOS tube M6 is turned off, and the output terminal OUT outputs the comparison voltage VB.
[0033] When the ground voltage VSS is greater than the voltage VB, the NMOS tube M2 enters the linear region, and the difference between the voltage at the VS2 terminal and the voltage at the VG2 terminal becomes larger. At this time, the current passing through the NMOS tube M1 is greater than the current of the current source I1, and the PMOS tube M6 is turned on, so that the VGN terminal is a high voltage, and the NMOS tube MN is turned on. At this time, the output terminal OUT outputs the ground voltage VSS.
[0034] like Figure 3 As shown, in other embodiments, an amplifier OPA is provided, including the above-mentioned buck circuit. The buck circuit is a part of the amplifier OPA. The output terminal VOUT of the amplifier OPA is connected to the negative input terminal of the amplifier OPA. The positive input terminal of the amplifier OPA is connected to the input terminal VIN.
[0035] The foregoing description of specific exemplary embodiments of the present invention is for the purpose of illustration and demonstration. These descriptions are not intended to limit the present invention to the precise form disclosed, and it is clear that many changes and variations can be made based on the above teachings. The purpose of selecting and describing the exemplary embodiments is to explain the specific principles of the present invention and its practical application, so that those skilled in the art can realize and utilize various different exemplary embodiments of the present invention and various different selections and changes. The scope of the present invention is intended to be limited by the claims and their equivalents.
Claims
1. A step-down circuit, characterized in that: include: A switch tube, connecting the ground voltage VSS and the output terminal VOUT; A voltage circuit receives a zero temperature coefficient current and provides a comparison voltage VB, wherein the voltage circuit includes an NMOS tube M3, an NMOS tube M4 and a resistor R1, wherein a source of the NMOS tube M3 is connected to one end of the resistor R1 and receives the zero temperature coefficient current, and the other end of the resistor R1 is connected to a source of the NMOS tube M4, a gate of the NMOS tube M3 is connected to an output terminal VOUT, and a gate of the NMOS tube M4 is connected to an input terminal VIN; as well as The control circuit is connected between the ground voltage VSS and the voltage circuit and is also connected to the switch tube; when the local voltage VSS is less than the comparison voltage VB, the output terminal VOUT outputs the comparison voltage VB; when the local voltage VSS is greater than the comparison voltage VB, the control circuit controls the switch tube to be turned on through the control terminal VGN, and the output terminal VOUT outputs the ground voltage VSS.
2. The step-down circuit according to claim 1, characterized in that: The switch tube is an NMOS tube MN, a source of the NMOS tube MN is connected to a ground voltage VSS, a gate of the NMOS tube MN is connected to a control terminal VGN, and a drain of the NMOS tube MN is connected to an output terminal VOUT.
3. The step-down circuit according to claim 1, wherein: The comparison voltage VB=V IN -IM4*R1, where V IN is the voltage input to the input terminal VIN, and IM4 is the zero temperature coefficient current flowing through the resistor R1.
4. The step-down circuit according to claim 1, characterized in that: The control circuit includes a current mirror, a current source I1, a PMOS tube M5 and a PMOS tube M6. The current mirror is connected to a ground voltage VSS and a voltage circuit. The drain of the PMOS tube M5 is connected to a gate, one end of the current source I1 and the current mirror. The source of the PMOS tube M5 is connected to the other end of the current source I1 and to a power supply voltage VDD. The gate of the PMOS tube M6 is connected to the gate of the PMOS tube M5. The source of the PMOS tube M6 is connected to the power supply voltage VDD. The drain of the PMOS tube M6 is connected to a control terminal VGN.
5. The step-down circuit according to claim 4, characterized in that: The current mirror includes an NMOS tube M1 and an NMOS tube M2, wherein the source of the NMOS tube M1 is connected to the source of the NMOS tube M2 and to the ground voltage VSS, the gate of the NMOS tube M1 is connected to the gate of the NMOS tube M2, the drain of the NMOS tube M1 is connected to the drain of the PMOS tube M5, and the drain of the NMOS tube M2 is connected to the voltage circuit.
6. The step-down circuit according to claim 1, characterized in that: The step-down circuit further includes a zero temperature coefficient current circuit for generating a zero temperature coefficient current, wherein the zero temperature coefficient current circuit is connected between a ground voltage VSS and a control circuit.
7. The step-down circuit according to claim 6, characterized in that: The zero temperature coefficient current circuit includes an amplifier OPA0, an NMOS tube M0, a resistor R0, a first current mirror and a second current mirror. The positive input terminal of the amplifier OPA0 is connected to a reference voltage VREF, the negative input terminal of the amplifier OPA0 is grounded through the resistor R0, the negative input terminal of the amplifier OPA0 is connected to the source of the NMOS tube M0, the gate of the NMOS tube M0 is connected to the output terminal of the amplifier OPA0, the drain of the NMOS tube M0 is connected to the first current mirror, the first current mirror is connected to the second current mirror, and the second current mirror is connected to the ground voltage VSS and the control circuit.
8. The step-down circuit according to claim 7, characterized in that: The first current mirror includes a PMOS tube MS0 and a PMOS tube MS1, and the second current mirror includes an NMOS tube MS2 and an NMOS tube MS3. The drain and gate of the PMOS tube MS0 are connected and connected to the drain of the NMOS tube M0 and the gate of the PMOS tube MS1. The source of the PMOS tube MS0 is connected to the power supply voltage VDD, the source of the PMOS tube MS1 is connected to the power supply voltage VDD, the drain of the PMOS tube MS1 is connected to the drain and gate of the NMOS tube MS2 and the gate of the NMOS tube MS3, the source of the PMOS tube MS2 is grounded, the drain of the PMOS tube MS3 is connected to the control circuit, and the source of the PMOS tube MS3 is grounded.
9. An amplifier, characterized in that: The invention comprises a step-down circuit as claimed in any one of claims 1 to 8.