Memory and method for manufacturing the same

Abstract

An embodiment of the present invention provides a memory and a manufacturing method thereof, wherein the memory comprises: a substrate, an active area located in the substrate, and a bit line structure located on the substrate, wherein the active area extends along a first direction; and a capacitor contact window, wherein the capacitor contact window is located between adjacent bit line structures, wherein at least one center line of the bottom surface of the capacitor contact window extends along a second direction, and an angle between the second direction and the first direction is less than or equal to 45 degrees. The present invention is conducive to improving the signal transmission performance of the memory.

Description

Technical Field

[0001] The embodiments of the present invention relate to the semiconductor field, and in particular to a memory and a manufacturing method thereof. Background Art

[0002] As the feature size of semiconductor integrated circuit devices continues to shrink, the size change of a certain component will have a significant impact on the overall performance of the semiconductor structure, such as the size change of the bit line structure.

[0003] Specifically, increasing the characteristic size of the bit line structure will compress the space of the capacitor contact hole and reduce the cross-sectional area of ​​the capacitor contact window. A small cross-sectional area of ​​the capacitor contact window is likely to cause poor contact, thereby causing storage capacitor failure; reducing the characteristic size of the bit line structure is likely to cause the bit line structure to collapse due to an excessively large aspect ratio.

[0004] How to optimize the performance of semiconductor structures without changing the characteristic dimensions of specific components is the focus of current research. Summary of the invention

[0005] The embodiments of the present invention provide a memory and a manufacturing method thereof, which are beneficial to improving the signal transmission performance of the memory.

[0006] To solve the above problems, an embodiment of the present invention provides a memory, comprising: a substrate, an active area located in the substrate, and a bit line structure located on the substrate, wherein the active area extends along a first direction; a capacitor contact window, wherein the capacitor contact window is located between adjacent bit line structures, and at least one center line of the bottom surface of the capacitor contact window extends along a second direction, and the angle between the second direction and the first direction is less than or equal to 45 degrees.

[0007] In addition, the bottom surface of the capacitor contact window is a parallelogram, the short side of the parallelogram is close to the bit line structure, and the long side of the parallelogram extends along the second direction.

[0008] In addition, the bottom surface of the capacitor contact window is a parallelogram, the long side of the parallelogram is close to the bit line structure, and the short side of the parallelogram extends along the second direction.

[0009] In addition, the bottom surface of the capacitor contact window is elliptical, and the major axis of the ellipse extends along the second direction.

[0010] In addition, the top surface of the capacitor contact window is elliptical, and the major axis of the ellipse extends along the second direction.

[0011] In addition, the capacitor contact window includes a first column in contact with the active area and a second column located on the first column, the top surface of the second column is the ellipse, and in a plane parallel to the substrate surface, the cross-sectional area of ​​the second column is smaller than the cross-sectional area of ​​the first column.

[0012] In addition, the memory further comprises: an isolation layer, which is located between adjacent bit line structures and is used to isolate adjacent capacitor contact windows, and the isolation layer covers the top surface of the first pillar exposed by the second pillar.

[0013] In addition, the capacitor contact windows are arranged in a quadrilateral.

[0014] Correspondingly, an embodiment of the present invention also provides a method for manufacturing a memory, comprising: providing a substrate, an active area located in the substrate, and a bit line structure located on the substrate, wherein the active area extends along a first direction; forming a sacrificial layer filling between adjacent bit line structures, and forming a mask layer covering the top surface of the sacrificial layer, wherein the mask layer is used to form an isolation layer; forming the isolation layer and a capacitor contact window located between adjacent isolation layers, wherein at least one center line of the bottom surface of the capacitor contact window extends along a second direction, and the angle between the second direction and the first direction is less than or equal to 45 degrees.

[0015] In addition, the process steps for forming the capacitor contact window include: forming a first isolation layer and a conductive film and a shielding layer located between adjacent first isolation layers, wherein the shielding layer is located on the conductive film; using a wet etching process to remove a portion of the first isolation layer to smooth the side wall of the shielding layer; using the smoothed shielding layer as a mask to etch at least a portion of the conductive film, and the remaining conductive film serves as the capacitor contact window.

[0016] In addition, in the same etching process, at least a portion of the conductive film and at least a portion of the first isolation layer are etched; after etching the first isolation layer, it also includes: forming a second isolation layer filling between adjacent conductive films, the top surface of the second isolation layer is flush with the top surface of the capacitor contact window, and the second isolation layer and the first isolation layer constitute the isolation layer.

[0017] In addition, etching at least a portion of the conductive film includes: etching through the conductive film so that a bottom surface pattern of the conductive film is the same as a top surface pattern of the conductive film.

[0018] In addition, the top surface of the shielding layer before smoothing is a parallelogram, and the top surface of the shielding layer after smoothing is an ellipse.

[0019] Compared with the prior art, the technical solution provided by the embodiment of the present invention has the following advantages:

[0020] In the above technical solution, by controlling the angle between the extension direction of at least one center line of the bottom surface of the capacitor contact window and the extension direction of the active area to be less than or equal to a preset value, the misalignment between the capacitor contact window and the active area is reduced, so that when the area of ​​the bottom surface of the capacitor contact window is the same, the contact area between the bottom surface of the capacitor contact window and the active area is larger, thereby improving the signal transmission performance of the capacitor contact window.

[0021] In addition, setting the bottom surface of the capacitor contact window to an ellipse with a long axis extending along the second direction is conducive to increasing the spacing between adjacent capacitor contact windows, reducing the parasitic capacitance between adjacent capacitor contact windows, and improving the signal transmission rate of the capacitor contact window. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0023] Figures 1 to 23 A schematic structural diagram corresponding to each step of the method for manufacturing a memory provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the embodiments of the present invention, many technical details are provided to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can be implemented.

[0025] Figures 1 to 23 A schematic structural diagram corresponding to each step of the method for manufacturing a memory provided by an embodiment of the present invention.

[0026] Figure 1 A top view corresponding to a step of a method for manufacturing a memory provided by an embodiment of the present invention; Figure 2 for Figure 1 The structure shown is a schematic cross-sectional structure diagram along the first cross-sectional direction AA1.

[0027] refer to Figure 1 and Figure 2 , providing a substrate 10 , an active region 101 located in the substrate 10 , a bit line structure 11 located on the substrate 10 , and an isolation film 114 .

[0028] The active region 101 extends along a first direction s1 .

[0029] The bit line structure 11 includes a first conductive layer 111, a second conductive layer 112 and a top dielectric layer 113 stacked in sequence. The first conductive layer 111 and the second conductive layer 112 are located in the substrate 10, and the first conductive layer 111 is in contact with the active area 101. The bit line structure 11 also includes a bottom dielectric layer 110, which is used to define the positions of the first conductive layer 111 and the second conductive layer 112.

[0030] The isolation film 114 covers the top surface and sidewalls of the bit line structure 11 , specifically covers the top surface and sidewalls of the top dielectric layer 113 and the sidewalls of the bottom dielectric layer 110 , and also covers the surface of the substrate 10 .

[0031] In this embodiment, the substrate 10 further has a buried word line 102, the bit line structure 11 extends along a first coordinate direction X, and the buried word line 102 extends along a second coordinate direction Y, and the first coordinate direction X is perpendicular to the second coordinate direction Y; in other embodiments, in the same plane, the angle between the first coordinate direction and the second coordinate direction is less than 90 degrees.

[0032] refer to Figure 3 , forming a sacrificial layer 12 filling between adjacent bit line structures 11 , and forming a bonding layer 131 covering the top surface of the sacrificial layer 12 .

[0033] Under the same etching process, the material of the sacrificial layer 12 and the material of the isolation film 114 have a large etching selectivity ratio to avoid the etchant used to remove the sacrificial layer 12 from etching the material of the isolation film 114, thereby ensuring that the bit line structure 11 has good signal transmission performance. Specifically, the material of the sacrificial layer 12 can be a spin-on dielectric (Spin-on Dielectrics, SOD), such as silicon dioxide, and the material of the isolation film 114 can be silicon nitride.

[0034] The bonding layer 131 is used to fix the sacrificial layer 12 and the subsequently formed mask layer to prevent the mask layer from shifting during the process, thereby improving the mask accuracy of the mask layer and improving the position accuracy of the capacitor contact window formed using the mask layer, ensuring good conductivity between the capacitor contact window and the active area 101, thereby enabling the memory to have good signal transmission performance.

[0035] The material of the bonding layer 131 may be tetraethyl orthosilicate (TEOS).

[0036] refer to Figure 4 , forming a mask layer 13 covering the top surface of the bonding layer 131.

[0037] The mask layer 13 may be a single-layer structure or a multi-layer structure stacked in sequence.

[0038] In this embodiment, the mask layer 13 includes a first sub-mask layer 132, a second sub-mask layer 133, a third sub-mask layer 134, a fourth sub-mask layer 135 and a fifth sub-mask layer 136 which are stacked in sequence. The material of the first sub-mask layer 132 may include a carbon-containing compound, the material of the second sub-mask layer 133 may include silicon oxynitride, the third sub-mask layer 134 may be a spin-on carbon layer (SOC), the fourth sub-mask layer 135 may be a silicon-oxygen hard mask intermediate layer structure (SHB), and the fifth sub-mask layer 136 is a photoresist layer.

[0039] refer to Figure 5 and Figure 6 , the fifth sub-mask layer 136 is exposed to form a patterned opening 136a.

[0040] Figure 5 for Figure 4 A top view of the structure shown after the exposure process; Figure 6 for Figure 5 The structure shown is a schematic cross-sectional structure diagram along the second cross-sectional direction BB2.

[0041] The fifth sub-mask layer 136 after exposure is composed of a plurality of mutually parallel and discrete mask strips, and the extension directions of different mask strips are the same; the fifth sub-mask layer 136 after exposure is used to limit the position of the capacitor contact window formed subsequently, specifically to limit the extension direction of at least one center line of the bottom surface of the capacitor contact window, that is, to make the extension direction of at least one center line of the bottom surface of the capacitor contact window the same as the extension direction of the mask strip. In this embodiment, the mask strip extends along the second direction s2, and the angle between the second direction s2 and the first direction s1 is less than or equal to 45 degrees, such as 30 degrees, 20 degrees or 10 degrees. In this way, the angle between the extension direction of at least one center line of the bottom surface of the capacitor contact window and the extension direction of the active area can be controlled to be less than or equal to a preset value, thereby reducing the misalignment between the bottom surface of the capacitor contact window and the active area, so that when the bottom surface area of ​​the capacitor contact window is the same, the contact area between the bottom surface of the capacitor contact window and the active area is larger, thereby making the signal transmission performance of the capacitor contact window better.

[0042] In this embodiment, after forming the fifth sub-mask layer 136, the sacrificial layer 12 is etched using a self-aligned double patterning process (SADP) to form an isolation groove for filling the first isolation layer. The specific process steps of the self-aligned double patterning process are as follows:

[0043] refer to Figure 7 , third sub-mask layer 134 and fourth sub-mask layer 135 are etched, and a sixth sub-mask layer 137 is formed.

[0044] Specifically, by patterning the opening 136a (refer to Figure 6 ) The third sub-mask layer 134 and the fourth sub-mask layer 135 are etched, and after the third sub-mask layer 134 is etched through to expose the second sub-mask layer 133, the remaining fifth sub-mask layer 136 is removed (refer to Figure 6 ); using a deposition process to form a sixth sub-mask layer 137, the sixth sub-mask layer 137 covers the top surface and sidewalls of the fourth sub-mask layer 135, covers the sidewalls of the third sub-mask layer 134 and covers the top surface of the second sub-mask layer 133.

[0045] In this embodiment, the sixth sub-mask layer 137 has a reserved groove 137 a therein.

[0046] refer to Figure 8 and Fig. 9 , a seventh sub-mask layer 138 and an isolation trench 14a are formed, and the isolation trench 14a is used to fill the first isolation layer.

[0047] In this embodiment, the sixth sub-mask layer 137, the second sub-mask layer 133, the first sub-mask layer 132, the bonding layer 131, the sacrificial layer 12 and the underlying dielectric layer 110 are etched in sequence using the seventh sub-mask layer 138, the third sub-mask layer 134 and the fourth sub-mask layer 135 to form an isolation groove 14a exposing the surface of the substrate 10; after the isolation groove 14a is formed, the second sub-mask layer 133, the third sub-mask layer 134, the fourth sub-mask layer 135, the sixth sub-mask layer 137 and the seventh sub-mask layer 138 can be removed by a first planarization process, thereby improving the manufacturing efficiency of the memory.

[0048] In other embodiments, the bottom dielectric layer may not be etched, that is, the isolation groove exposes the surface of the bottom dielectric layer, and the portion of the bottom dielectric layer exposed by the isolation groove is used as a part of the isolation layer formed subsequently, which is helpful to reduce process steps and shorten the process cycle.

[0049] Since the first sub-mask layer 132 is fixed to the sacrificial layer 12 by the bonding layer 131 and has a high fixing strength, directly removing the first sub-mask layer 132 by a planarization process may cause the sacrificial layer 12 indirectly connected to the first sub-mask layer 132 to collapse due to lack of support, or cause the sacrificial layer 12 to have internal defects.

[0050] refer to Fig.10 and Fig.11 , removing the first sub-mask layer 132 and filling the isolation trench 14 a to form a first isolation layer 14 .

[0051] In this embodiment, after the planarization process, the first sub-mask layer 132 is removed by an etching process to avoid damaging the intermediate structure or leaving process defects due to the removal of the first mask layer 132, thereby ensuring that the finally manufactured memory has a high yield.

[0052] refer to Fig.12 , a second planarization process is performed to reduce the height of the first isolation layer 14.

[0053] In this embodiment, the height of the capacitor contact window formed subsequently can be limited by lowering the height of the first isolation layer 14, thereby avoiding structural defects such as collapse and breakage of the first isolation layer 14 and the capacitor contact window due to excessive aspect ratio, thereby ensuring that the finally formed memory has good structural stability.

[0054] In this embodiment, while lowering the height of the first isolation layer 14 , the bonding layer 131 is removed.

[0055] refer to Fig.13 and Fig.14 , remove the remaining sacrificial layer 12 (refer to Fig.12 ), and removing the portion of the underlying dielectric layer 110 exposed by the first isolation layer 14, to form a capacitor contact hole 15a exposing at least a portion of the surface of the active area 101.

[0056] In this embodiment, a wet etching process may be used to remove the remaining sacrificial layer 12 between adjacent first isolation layers 14 , and a maskless dry etching process may be used to remove a portion of the underlying dielectric layer 110 exposed by the first isolation layer 14 .

[0057] It should be noted that, in the process of etching the underlying dielectric layer 110 using a maskless dry etching process, the first isolation layer 14 will also be etched, that is, the height of the first isolation layer 14 will be further reduced. Therefore, if it is necessary to make the finally formed capacitor contact hole 15a have a preset depth, it is necessary to reserve a first isolation layer 14 with a height greater than the preset depth in the second planarization process, and the difference between the actual reserved height and the preset depth is equal to the thickness of the underlying dielectric layer 110 in the direction perpendicular to the substrate 10.

[0058] refer to Figures 15 to 17 , in the capacitor contact hole 15a (reference Fig.14 ) is formed inside the conductive film and the shielding layer 153, and the shielding layer 153 is located on the conductive film.

[0059] In this embodiment, the conductive film includes a first conductive film 151 and a second conductive film 152, the first conductive film 151 is in contact with the active area 101, and the second conductive film 152 is located on the first conductive film 151. The first conductive film 151 and the second conductive film 152 can be formed by first filling the capacitor contact hole 15a and then performing a dry etching process.

[0060] For example, after forming the first conductive film 151 , a deposition process may be used to form a second initial conductive film 152 a filling the capacitor contact hole 15 a , and a dry etching process may be used to etch away a portion of the second initial conductive film 152 a , leaving the remaining second initial conductive film 152 a as the second conductive film 152 .

[0061] In this embodiment, the contact resistance between the capacitor contact window formed by the first conductive film 151 and the second conductive film 152 and the active area 101 can be reduced by controlling the materials of the first conductive film 151 and the second conductive film 152, so that the finally formed memory has good signal transmission performance.

[0062] Specifically, the material of the active region 101 may include single crystal silicon, the material of the first conductive film 151 may include polycrystalline silicon, and the material of the second conductive film 152 may include tungsten.

[0063] In this embodiment, due to the limitation of the mask strip, at least one center line of the bottom surface of the first conductive film 151 extends along the second direction. Specifically, in this embodiment, the bottom surface of the first conductive film 151 is a parallelogram, and the short side of the parallelogram is close to the bit line structure. Due to the limitation of the mask strip, the long side of the parallelogram extends along the second direction s2, that is, the center line parallel to the long side extends along the second direction; in other embodiments, the bottom surface of the first conductive film is a parallelogram, the long side of the parallelogram is close to the bit line structure, and due to the limitation of the mask strip, the center line parallel to the short side extends along the second direction.

[0064] In this embodiment, under the same etching process, the etching selectivity ratio of the material of the shielding layer 153 to the material of the first isolation layer 14 is greater than 50. This is conducive to ensuring that in the process of etching the first isolation layer 14 using a wet etching process, the etchant can smooth the side wall of the shielding layer 153 without causing over-etching, thereby ensuring that the smoothed shielding layer 153 has a precise shielding effect.

[0065] It should be noted that "smoothing" generally includes two levels: first, preliminary smoothing, that is, grinding the right angle into a rounded corner; second, deep smoothing, that is, further grinding the straight line transition into an arc transition. Specifically, preliminary smoothing of a rhombus may refer to grinding the four straight angles of the rhombus into rounded corners, and the rounded corners are still connected and transitioned by straight lines; deep smoothing of a rhombus may refer to grinding the rhombus into an ellipse. "Smoothing" in the embodiments of the present invention refers to deep smoothing.

[0066] refer to Fig.18 , a wet etching process is used to remove part of the first isolation layer 14 to smooth the side wall of the shielding layer 153.

[0067] In this embodiment, the shielding layer 153 includes a plurality of discrete shielding grids, and the shielding grids are located in the capacitor contact hole. Smoothing the sidewalls of the shielding layer 153 actually refers to smoothing the sidewalls of each shielding grid.

[0068] In this embodiment, the shielding grid is a parallelogram before smoothing, and the long side of the parallelogram extends along the second direction s2; after smoothing, the shielding grid is an ellipse, and the long axis of the ellipse extends along the second direction s2.

[0069] In other embodiments, each shielding grid is a parallelogram before smoothing, and the short side of the parallelogram extends along the second direction; after smoothing, the shielding grid is an ellipse, and the long axis of the ellipse extends along the second direction.

[0070] refer to Fig.19 , with a smoothed shielding layer 153 (reference Fig.18 ) is used as a mask to etch at least a portion of the conductive film, and the remaining conductive film serves as a capacitor contact window.

[0071] In this embodiment, the smoothed shielding layer 153 is used as a mask to etch a partial thickness of the second conductive film 152 and the first isolation layer 14. After etching, the top surface of the first isolation layer 14 is higher than the top surface of the first conductive film 151, and the top surface of the second conductive film 152 after etching is the same as the top surface of the shielding grid. After etching the second conductive film 152, the shielding layer 153 is removed.

[0072] In other embodiments, the second conductive film is etched using the smoothed shielding layer as a mask, and the bottom surface of the etched second conductive film is the same as the top surface of the shielding grid; or, the second conductive film and a partial thickness of the first conductive film are etched using the smoothed shielding layer as a mask, and the bottom surface of the etched second conductive film is the same as the top surface of the shielding grid, and the top surface of the etched first conductive film is the same as the top surface of the shielding grid; or, the second conductive film and the first conductive film are etched using the smoothed shielding layer as a mask, and the bottom surface of the etched first conductive film is the same as the top surface of the shielding grid.

[0073] Fig.21 for Fig. 20 A schematic diagram of the three-dimensional structure of the structure shown, Fig. 22 for Fig. 20 Top view of the structure shown. Figure 20 to Figure 22 , forming a second isolation layer 16.

[0074] In this embodiment, after etching the first isolation layer 14 , a second isolation layer 16 is formed to fill between adjacent conductive films. The top surface of the second isolation layer 16 is flush with the top surface of the capacitor contact window. The second isolation layer 16 and the first isolation layer 14 constitute an isolation layer.

[0075] The position of the second isolation layer 16 is related to the etching area of ​​the previous etching process, and the second isolation layer 16 fills the groove etched by the previous etching process.

[0076] In this embodiment, reference Fig.23 The first conductive film 151 and the second conductive film 152 are distributed in a quadrilateral, and in a direction perpendicular to the substrate surface, the central axis of the first conductive film 151 coincides with the central axis of the second conductive film 152.

[0077] In this embodiment, the central axis of the first conductive film 151 has an orthographic projection point 17 perpendicular to the substrate surface direction. In the direction of the line connecting the adjacent orthographic projection points 17, the first spacing d1 between adjacent first conductive films 151 is smaller than the second spacing d2 between adjacent second conductive films 152, that is, the parasitic capacitance between adjacent second conductive films 152 is smaller than the parasitic capacitance between adjacent first conductive films 151. In other words, smoothing the conductive film is beneficial to reducing the parasitic capacitance between adjacent capacitor contact windows and improving the signal transmission performance of the capacitor contact windows.

[0078] In the present embodiment, only a partial thickness of the conductive film is etched to ensure a larger contact area between the bottom surface of the conductive film and the active area, thereby achieving better signal transmission performance between the conductive film and the active area. In other embodiments, the conductive film is etched through to make the bottom surface pattern of the conductive film the same as the top surface pattern of the conductive film, which are both elliptical in the present embodiment. This helps to reduce the parasitic capacitance between adjacent conductive films.

[0079] In the present embodiment, by controlling the angle between the extension direction of at least one center line of the bottom surface of the capacitor contact window and the extension direction of the active area to be less than or equal to a preset value, the misalignment between the capacitor contact window and the active area is reduced, so that when the bottom surface area of ​​the capacitor contact window is the same, the contact area between the bottom surface of the capacitor contact window and the active area is larger, thereby improving the signal transmission performance of the capacitor contact window.

[0080] Correspondingly, an embodiment of the present invention further provides a memory, which can be manufactured using the above-mentioned memory manufacturing method.

[0081] refer to Fig.21 and Fig. 22 The memory includes: a substrate 10, an active area 101 located in the substrate 10, and a bit line structure 11 located on the substrate 10, wherein the active area 101 extends along a first direction s1; a capacitor contact window, wherein the capacitor contact window is located between adjacent bit line structures 11, and at least one center line of the bottom surface of the capacitor contact window extends along a second direction s2, and an angle between the second direction s2 and the first direction s1 is less than or equal to 45 degrees.

[0082] In this embodiment, the bottom surface of the capacitor contact window is a parallelogram, the short side of the quadrilateral is close to the bit line structure 11, and the long side of the parallelogram extends along the second direction s2; in other embodiments, the bottom surface of the capacitor contact window is a parallelogram, the long side of the parallelogram is close to the bit line structure 11, and the short side of the parallelogram extends along the second direction s2.

[0083] In this embodiment, the top surface of the capacitor contact window is elliptical, the bottom surface is a parallelogram, and the major axis of the ellipse extends along the second direction s2; in other embodiments, both the top and bottom surfaces of the capacitor contact window are elliptical, and the major axis of the ellipse extends along the second direction.

[0084] In this embodiment, the capacitor contact window includes a first column in contact with the active area 101 and a second column located on the first column. The top surface of the second column is elliptical. In a plane parallel to the surface of the substrate 10, the cross-sectional area of ​​the second column is smaller than the cross-sectional area of ​​the first column.

[0085] In this embodiment, the first column and the second column are divided by the size of the cross-sectional area; in other embodiments, the first column and the second column are divided by the type of material.

[0086] In this embodiment, the memory further includes: an isolation layer, the isolation layer is located between the bit line structures 11 and is used to isolate adjacent capacitor contact windows, and the isolation layer covers the top surface of the first pillar exposed by the second pillar. Specifically, the isolation layer includes a first isolation layer 14 and a second isolation layer 16 located on the first isolation layer 14, and the second isolation layer 16 covers the top surface of the first pillar exposed by the second pillar.

[0087] In this embodiment, the capacitor contact windows are arranged in a quadrilateral.

[0088] In the present embodiment, by controlling the angle between the extension direction of at least one center line of the bottom surface of the capacitor contact window and the extension direction of the active area to be less than or equal to a preset value, the misalignment between the capacitor contact window and the active area is reduced, so that when the bottom surface area of ​​the capacitor contact window is the same, the contact area between the bottom surface of the capacitor contact window and the active area is larger, thereby improving the signal transmission performance of the capacitor contact window.

[0089] Those skilled in the art will appreciate that the above embodiments are specific examples of the present invention, and in practical applications, various changes may be made to the embodiments in form and detail without departing from the spirit and scope of the present invention. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present invention, and therefore the scope of protection of the present invention shall be subject to the scope defined in the claims.

Claims

1. A memory, characterized in that: include: A substrate, an active region located in the substrate, and a bit line structure located on the substrate, wherein the active region extends along a first direction; A capacitor contact window, wherein the capacitor contact window is located between adjacent bit line structures, at least one center line of a bottom surface of the capacitor contact window extends along a second direction, and an angle between the second direction and the first direction is less than or equal to 45 degrees; The top surface of the capacitor contact window is elliptical, and the major axis of the ellipse extends along the second direction; The capacitor contact window includes a first column in contact with the active area and a second column located on the first column, the top surface of the second column is the ellipse, and in a plane parallel to the substrate surface, the cross-sectional area of ​​the second column is smaller than the cross-sectional area of ​​the first column.

2. The memory according to claim 1, characterized in that: Also includes: An isolation layer is located between adjacent bit line structures and is used to isolate adjacent capacitor contact windows. The isolation layer covers the top surface of the first column exposed by the second column.

3. The memory according to claim 1, characterized in that: The capacitor contact windows are arranged in a quadrilateral.

4. A method for manufacturing a memory, characterized in that: include: Providing a substrate, an active region located in the substrate, and a bit line structure located on the substrate, wherein the active region extends along a first direction; forming a sacrificial layer filled between adjacent bit line structures, and forming a mask layer covering a top surface of the sacrificial layer, wherein the mask layer is used to form an isolation layer; forming the isolation layers and capacitor contact windows located between adjacent isolation layers, wherein at least one center line of the bottom surface of the capacitor contact window extends along a second direction, and an angle between the second direction and the first direction is less than or equal to 45 degrees; The process steps for forming the capacitor contact window include: forming a first isolation layer and a conductive film and a shielding layer located between adjacent first isolation layers, wherein the shielding layer is located on the conductive film; removing part of the first isolation layer by a wet etching process to smooth the side wall of the shielding layer; using the smoothed shielding layer as a mask to etch at least part of the conductive film, and the remaining conductive film serves as the capacitor contact window.

5. The method for manufacturing a memory according to claim 4, characterized in that: In the same etching process, etching at least a portion of the conductive film and at least a portion of the first isolation layer; After etching the first isolation layer, the method further includes: forming a second isolation layer filled between adjacent conductive films, wherein the top surface of the second isolation layer is flush with the top surface of the capacitor contact window, and the second isolation layer and the first isolation layer constitute the isolation layer.

6. The method for manufacturing a memory according to claim 4, characterized in that: The etching of at least a portion of the conductive film includes: etching through the conductive film so that a bottom surface pattern of the conductive film is the same as a top surface pattern of the conductive film.

7. The method for manufacturing a memory according to claim 4, characterized in that: The top surface of the shielding layer before smoothing is a parallelogram, and the top surface of the shielding layer after smoothing is an ellipse.

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