A method for fabricating a gallium oxide floating transistor array

Abstract

The present invention provides a method for preparing a multi-purpose gallium oxide suspended transistor array, which can be used as a solar-blind detector. Combining the two deep ultraviolet detection modes of gallium oxide, the photoconductive mode and the resonant mode, can effectively make up for the shortcomings of a single mode and improve the dynamic range and target accuracy of the detector. It can also be used as a transistor. Compared with traditional silicon-based circuits, the circuit using gallium oxide wide bandgap semiconductor materials has higher power density and lower power consumption. The present invention adopts a wafer-level suspended gallium oxide transistor preparation process to further increase the versatility of the device and reduce costs. It has good application prospects and is also in line with the future development direction of device integration and miniaturization.

Description

Technical Field

[0001] The invention belongs to the technical field of transistor application, and in particular relates to a method for preparing a gallium oxide suspended transistor array. Background Art

[0002] In the field of transistor applications, mainstream power devices composed of silicon are approaching the limits of their basic performance, causing commercial power systems to become bulky and inefficient. The third-generation wide bandgap semiconductor materials have the advantages of large bandgap width, high electron saturation drift velocity, small dielectric constant, and good conductivity.

[0003] Solar-blind detectors are devices that can respond photoelectrically to deep ultraviolet radiation. All short-wave ultraviolet (100-280nm) radiation from the sun is absorbed by diatomic oxygen or ozone in the atmosphere, and very little reaches the earth's surface from the sun. Signals in the spectral region with a wavelength of 200-280nm can be effectively detected without being affected by solar radiation. This region is called the "solar-blind" region. Solar-blind photoelectric detectors have the effect of shielding sunlight. Compared with visible light and infrared light detection, they have significant advantages such as low background noise and undisturbed signals. They can be used in environments such as missile plume tracking, flame detection and environmental monitoring. The bandgap width (4.9eV) of gallium oxide materials determines that its corresponding absorption wavelength is between 200-280nm, which is located in the deep ultraviolet solar-blind region. It is one of the few ideal deep ultraviolet "solar-blind" photoelectric materials.

[0004] On the one hand, mainstream silicon-based transistors are getting closer and closer to the upper limit of their performance. On the other hand, traditional solar-blind detectors mainly use wide-bandgap semiconductor materials such as aluminum gallium nitrogen and oxygen magnesium zinc, which face problems such as growth difficulties and the lack of large-size single crystal substrates during the manufacturing process. Although the existing technology also uses β-gallium oxide to prepare solar-blind detectors, the thermal conductivity problem affects the detection performance of solar-blind detectors. The existing technology also proposes to use micro-nano resonant sensors to make solar-blind detectors, but their sensitivity is relatively low. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a method for preparing a multi-purpose gallium oxide suspended transistor array. The technical problem to be solved by the present invention is achieved by the following technical solution:

[0006] The present invention provides a method for preparing a multi-purpose gallium oxide suspended transistor array, comprising:

[0007] Step 1: Obtain a single crystal gallium oxide substrate and a round wafer;

[0008] Wherein, the wafer is composed of a bottom layer of silicon and a top layer of silicon dioxide;

[0009] Step 2: epitaxially growing a gallium oxide thin film on a single crystal gallium oxide substrate;

[0010] Step 3, injecting hydrogen ions into the gallium oxide layer formed by the gallium oxide thin film to form a hydrogen ion layer;

[0011] Step 4: Covering the silicon dioxide layer of the wafer with a layer of photoresist, and determining a first shape and a first position of a first evaporated metal on the silicon dioxide layer of the wafer;

[0012] Step 5: depositing a metal layer at the location of the first evaporated metal to form a first evaporated metal layer;

[0013] Wherein, the shape of the first evaporated metal layer is a first shape;

[0014] Step 6: removing the photoresist except the first evaporated metal;

[0015] Step 7: depositing a dielectric on the surface of the wafer to form a dielectric layer covering the surface;

[0016] Step 8: Bonding the gallium oxide film after hydrogen ion injection to the wafer on which the dielectric layer is deposited;

[0017] Step 9: stripping the hydrogen ion layer from the hydrogen ion injection point, and stripping the gallium oxide layer on the hydrogen ion layer during the hydrogen ion layer stripping process;

[0018] Step 10: Determine a second shape and a second position of the second evaporated metal on the silicon dioxide layer of the round wafer, and cover the silicon dioxide layer of the round wafer with a layer of photoresist;

[0019] Step 11: depositing a metal layer at a second position of the evaporated metal to form a second shape of the second evaporated metal;

[0020] Step 12: removing the photoresist outside the second position;

[0021] Step 13: Covering a layer of photoresist at the second position;

[0022] Step 14: etching the dielectric layer formed on the surface of the round wafer and removing the photoresist at the second position to obtain a gallium oxide suspended transistor;

[0023] Step 15: Repeat steps 5 to 14 at different positions of the wafer to prepare gallium oxide suspended transistors to obtain a gallium oxide suspended transistor array.

[0024] Optionally, the step 2 includes:

[0025] A gallium oxide thin film is epitaxially grown on a single crystal gallium oxide substrate by a chemical vapor deposition (CVD) method.

[0026] Optionally, determining the first shape and the first position of the first evaporated metal on the silicon dioxide layer of the round wafer includes: determining the first shape and the second position of the first evaporated metal on the silicon oxide layer of the round wafer through a light-transmitting hole on a mask.

[0027] Optionally, step 5 includes:

[0028] Depositing a layer of metallic aluminum on the surface of the wafer to form an aluminum layer;

[0029] A layer of metal gold is deposited on the aluminum layer to protect the aluminum layer.

[0030] Optionally, step 7 includes:

[0031] A silicon dioxide dielectric layer is deposited on the surface of the wafer by plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD) to cover the surface of the wafer.

[0032] Optionally, the step 11 includes:

[0033] Depositing a layer of metal titanium on the surface of the wafer so that the titanium layer forms an ohmic contact with the gallium oxide material on the wafer;

[0034] A layer of metal gold is evaporated on the titanium layer to cover the titanium layer.

[0035] Optionally, step 14 includes:

[0036] The dielectric layer is etched using a buffer oxide or a gas, and the photoresist at the second position is removed to obtain a gallium oxide suspended transistor.

[0037] The present invention provides a method for preparing a multi-purpose gallium oxide suspended transistor array. When used as a solar-blind detector, the two deep ultraviolet detection modes of gallium oxide, the photoconductive mode and the resonant mode, are combined to effectively make up for the shortcomings faced by a single mode, and the dynamic range and target accuracy of the detector can be improved. Fast and high-response ultraviolet solar-blind light detection can be achieved, and solar-blind detector arrays can be further prepared, which has good application prospects. When used as transistors, the performance of power devices can be further improved, and the size, cost, and power consumption of power devices can be greatly reduced. The present invention adopts a wafer-level suspended gallium oxide transistor preparation process, so that the device has multifunctional and multi-purpose characteristics, and reduces costs. At the same time, the suspended transistor array obtained by the present invention is also in line with the future development direction of device integration and miniaturization. The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a flow chart of a method for preparing a gallium oxide dual-mode suspended transistor provided by an embodiment of the present invention;

[0039] Figure 2a It is a schematic diagram of the gallium oxide ion implantation process provided by the present invention;

[0040] Figure 2b It is a schematic diagram of the metal deposition process on a wafer provided by the present invention;

[0041] Figure 3 It is a schematic diagram of the transistor preparation process provided by the present invention;

[0042] Figure 4 is a schematic diagram of the top surface of the suspended transistor array provided by the present invention;

[0043] Figure 5 It is a schematic diagram of a mask in the photolithography process provided by the present invention;

[0044] Figure 6 It is a schematic diagram of another mask in the photolithography process provided by the present invention. DETAILED DESCRIPTION

[0045] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0046] Embodiment 1

[0047] like Figure 1 As shown, the present invention provides a method for preparing a gallium oxide bimodal transistor, comprising:

[0048] Step 1: Obtain a single crystal gallium oxide substrate and a round wafer;

[0049] Wherein, the wafer is composed of a bottom layer of silicon and a top layer of silicon dioxide;

[0050] Step 2: epitaxially growing a gallium oxide thin film on a single crystal gallium oxide substrate;

[0051] As an optional implementation manner of the present invention, the step 2 comprises:

[0052] A gallium oxide thin film is epitaxially grown on a single crystal gallium oxide substrate by a chemical vapor deposition (CVD) method.

[0053] refer to Figure 2a In the step 1 of the neutron diagram a, a gallium oxide thin film is epitaxially grown on a single crystal gallium oxide substrate by chemical vapor deposition (CVD).

[0054] Step 3, injecting hydrogen ions into the gallium oxide layer formed by the gallium oxide thin film to form a hydrogen ion layer;

[0055] refer to Figure 2aAs shown in the annotation 2 of the sub-figure b, after the growth is completed, ion implantation is performed to inject hydrogen ions into the gallium oxide layer.

[0056] Step 4: Covering the silicon dioxide layer of the wafer with a layer of photoresist, and determining a first shape and a first position of a first evaporated metal on the silicon dioxide layer of the wafer;

[0057] As an optional embodiment of the present invention, determining the first shape and first position of the first evaporated metal on the silicon dioxide layer of the wafer includes: determining the first shape and second position of the first evaporated metal on the silicon oxide layer of the wafer through a light-transmitting hole on a mask.

[0058] refer to Figure 2b , in which the underlying silicon Figure 2b As indicated by the label 2 in the sub-figure a, and the top layer of silicon dioxide, such as Figure 2b As indicated by 1 in sub-figure a, photolithography is performed on the wafer. Figure 2b Sub-Figure a. First, a layer of photoresist is covered on the wafer, such as Figure 2b Indicated by label 3 in sub-figure b.

[0059] refer to Figure 5 The shape and position of the evaporated metal on the wafer are determined by the mask. Figure 5 1) The shape and position of the evaporated metal can be determined.

[0060] Step 5: depositing a metal layer at the location of the first evaporated metal to form a first evaporated metal layer;

[0061] Wherein, the shape of the first evaporated metal layer is a first shape;

[0062] As an optional implementation manner of the present invention, step 5 includes:

[0063] Depositing a layer of metallic aluminum on the surface of the wafer to form an aluminum layer;

[0064] A layer of metal gold is deposited on the aluminum layer to protect the aluminum layer.

[0065] Step 6: removing the photoresist except the first evaporated metal;

[0066] It can be understood that after the positive photoresist is exposed, the exposed photoresist dissolves in the developer, and then the metal is deposited by evaporation. First, a layer of metal aluminum is deposited. Figure 2b As indicated by the label 4 in sub-figure d, in order to avoid corrosion of the metal aluminum layer by subsequent processes, a layer of metal gold is deposited on the aluminum layer. Figure 2b As shown in the sub-figure d, the aluminum layer is covered for protection. After step 5 is completed, the photoresist is removed. Figure 2b Sub-figure e.

[0067] Step 7: depositing a dielectric on the surface of the wafer to form a dielectric layer covering the surface;

[0068] As an optional implementation manner of the present invention, step 7 includes:

[0069] A silicon dioxide dielectric layer is deposited on the surface of the wafer by plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD) to cover the surface of the wafer.

[0070] After removing the photoresist, a layer of silicon dioxide is deposited to cover the surface of the wafer by plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD). Figure 2b Subfigure f.

[0071] Step 8: Bonding the gallium oxide film after hydrogen ion injection to the wafer on which the dielectric layer is deposited;

[0072] refer to Figure 3 , the gallium oxide after hydrogen ion injection, such as Figure 2a As shown in sub-figure c, bonding is performed with a wafer having a deposited silicon dioxide layer, such as Figure 3 As shown in sub-figure a.

[0073] Step 9: stripping the hydrogen ion layer from the hydrogen ion injection point, and stripping the gallium oxide layer on the hydrogen ion layer during the hydrogen ion layer stripping process;

[0074] refer to Figure 3 , from the injected hydrogen ion layer, Figure 3 Part of the gallium oxide layer is peeled off at the position marked 1 in sub-figure a, and the gallium oxide layer on the hydrogen ion layer is peeled off, such as Figure 3 Sub-figure b.

[0075] Step 10: Determine a second shape and a second position of the second evaporated metal on the silicon dioxide layer of the round wafer, and cover the silicon dioxide layer of the round wafer with a layer of photoresist;

[0076] Step 11: depositing a metal layer at a second position of the evaporated metal to form a second shape of the second evaporated metal;

[0077] Step 12: removing the photoresist outside the second position;

[0078] Step 13: Covering a layer of photoresist at the second position;

[0079] Step 14: Etch the dielectric layer formed on the surface of the round wafer, and remove the photoresist at the second position to obtain a gallium oxide suspended transistor.

[0080] refer to Figure 6First, a layer of photoresist is applied to the wafer, and then a mask such as Figure 6 The shape and position of the second evaporated metal are determined on the wafer. There are light-transmitting holes on the mask. Figure 6 The position 1 can determine the second shape and the second position of the second evaporated metal. After exposure, the photoresist exposed to light is dissolved in the developer, such as Figure 3 Sub-picture d. Then, the metal is deposited by evaporation. First, a layer of titanium is immersed, such as Figure 3 As indicated by the label 2 in sub-figure e, titanium can form an ohmic contact with the gallium oxide material on the wafer. At the same time, in order to avoid damage to the metal titanium layer, a layer of metal gold is evaporated on the titanium layer, such as Figure 3 As indicated by the label 3 in sub-figure e, the titanium layer is covered for protection. After completion, the photoresist is removed, as shown in FIG. Figure 3 As shown in sub-figure f.

[0081] Using photoresist, such as Figure 3 As shown in the sub-figure g, marked 4, the surface of the wafer is covered for protection, and then the silicon dioxide layer deposited on the metal is etched using a buffered oxide, such as Figure 3 Sub-picture h. Alternatively, hydrofluoric acid (HF), xenon difluoride (XeF2) or the like may be used to remove the intermediate oxide layer, and then the photoresist may be removed, such as Figure 3 As shown in sub-figure i. After completing all the processes, a gallium oxide suspended transistor is obtained. Of course, the top surface of the device of the present invention can have a variety of structures.

[0082] Step 15: Repeat steps 5 to 14 at different positions of the wafer to prepare gallium oxide suspended transistors to obtain a gallium oxide suspended transistor array.

[0083] It can be understood that for the resonator mode, the low thermal conductivity of gallium oxide materials and the high responsiveness of the resonant mode of the electromechanical system to strain can be combined to construct a resonant nanoelectromechanical resonator based on the photothermal effect. Combining the two modes of gallium oxide photoconductive mode and resonant mode deep ultraviolet detection can not only effectively make up for the shortcomings of a single mode, but also greatly improve the dynamic range and target accuracy of detection when used as a solar-blind detector.

[0084] refer to Figure 4 , Figure 4 Schematic diagram of the top surface of a suspended transistor array. The suspended transistor array of the present invention can be regularly distributed to form an array shape, and of course can also form other array shapes, which is not limited in the present invention.

[0085] The present invention provides a method for preparing a multi-purpose gallium oxide transistor array. When used as a solar-blind detector, the two deep ultraviolet detection modes of gallium oxide, the photoconductive mode and the resonant mode, are combined to effectively make up for the shortcomings of a single mode, and can improve the dynamic range and target accuracy of the detector. When used as a transistor, it makes up for the shortcomings of current silicon-based circuits and greatly reduces the size, cost, and power consumption of power devices. The present invention adopts a wafer-level suspended gallium oxide transistor preparation process, which makes the device multifunctional and multi-purpose and reduces the cost. At the same time, the suspended transistor obtained by the present invention also conforms to the development trend of future device integration and miniaturization.

[0086] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A method for preparing a multi-purpose gallium oxide suspended transistor array, characterized in that: include: Step 1: Obtain a single crystal gallium oxide substrate and a round wafer; Wherein, the wafer is composed of a bottom layer of silicon and a top layer of silicon dioxide; Step 2: epitaxially growing a gallium oxide thin film on a single crystal gallium oxide substrate; Step 3, injecting hydrogen ions into the gallium oxide layer formed by the gallium oxide thin film to form a hydrogen ion layer; Step 4: Covering the silicon dioxide layer of the wafer with a layer of photoresist, and determining a first shape and a first position of a first evaporated metal on the silicon dioxide layer of the wafer; Step 5: depositing a metal layer at the location of the first evaporated metal to form a first evaporated metal layer; Wherein, the shape of the first evaporated metal layer is a first shape; Step 6: removing the photoresist except the first evaporated metal; Step 7: depositing a dielectric on the surface of the wafer to form a dielectric layer covering the surface; Step 8: Bonding the gallium oxide film after hydrogen ion injection to the wafer on which the dielectric layer is deposited; Step 9: stripping the hydrogen ion layer from the hydrogen ion injection point, and stripping the gallium oxide layer on the hydrogen ion layer during the hydrogen ion layer stripping process; Step 10: Determine a second shape and a second position of the second evaporated metal on the silicon dioxide layer of the round wafer, and cover the silicon dioxide layer of the round wafer with a layer of photoresist; Step 11: depositing a metal layer at a second position of the evaporated metal to form a second shape of the second evaporated metal; Step 12: removing the photoresist outside the second position; Step 13: Covering a layer of photoresist at the second position; Step 14: etching the dielectric layer formed on the surface of the round wafer and removing the photoresist at the second position to obtain a gallium oxide suspended transistor; Step 15: Repeat steps 5 to 14 at different positions of the wafer to prepare gallium oxide suspended transistors to obtain a gallium oxide suspended transistor array.

2. The preparation method according to claim 1, characterized in that: The step 2 comprises: A gallium oxide thin film is epitaxially grown on a single crystal gallium oxide substrate by a chemical vapor deposition (CVD) method.

3. The preparation method according to claim 1, characterized in that: Determining the first shape and the first position of the first evaporated metal on the silicon dioxide layer of the wafer includes: determining the first shape and the second position of the first evaporated metal on the silicon oxide layer of the wafer through a light-transmitting hole on a mask.

4. The preparation method according to claim 1, characterized in that: The step 5 comprises: Depositing a layer of metallic aluminum on the surface of the wafer to form an aluminum layer; A layer of metal gold is deposited on the aluminum layer to protect the aluminum layer.

5. The preparation method according to claim 1, characterized in that: The step 7 comprises: A silicon dioxide dielectric layer is deposited on the surface of the wafer by plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD) to cover the surface of the wafer.

6. The preparation method according to claim 1, characterized in that: The step 11 comprises: Depositing a layer of metal titanium on the surface of the wafer so that the titanium layer forms an ohmic contact with the gallium oxide material on the wafer; A layer of metal gold is evaporated on the titanium layer to cover the titanium layer.

7. The preparation method according to claim 1, characterized in that: The step 14 comprises: The dielectric layer is etched using a buffer oxide or a gas, and the photoresist at the second position is removed to obtain a gallium oxide suspended transistor.

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