A GPIO testing method and device

Abstract

The present invention provides a GPIO testing method and device, wherein the method adds a Schottky diode to each round-test GPIO in addition to a pull-down resistor, utilizes the unidirectional conductivity of the Schottky diode, and while the high level of the high-level round-test GPIO can be loaded onto the input GPIO through the Schottky diode, it is ensured that the round-test GPIOs do not affect each other, and then, by making the round-test GPIO output high-level signals one by one in turn, the open-circuit fault and the short-circuit fault of the GPIO are automatically detected, thereby improving the detection efficiency, ensuring that after the detection is qualified, all the GPIOs are qualified, and ensuring the qualified rate of the product.

Description

Technical Field

[0001] The invention relates to the field of electrical performance testing, and in particular to open circuit and short circuit fault testing of GPIO. Background Art

[0002] During the production of modules and chips, all GPIOs (General-purpose input / output) need to be tested. Nowadays, there are often dozens or even hundreds of GPIOs. If each GPIO is tested separately, it will take a lot of manpower and be too costly. Therefore, it is necessary to automate GPIO testing.

[0003] The existing GPIO automated test is to short-circuit all GPIOs together, then configure one of the GPIOs as an input port, and let the remaining GPIOs output high levels in turn, and the GPIO configured as the input port will perform the test. When a GPIO is outputting a high level, the GPIO configured as the input port also detects a high level, and the GPIO is considered to have passed the test; otherwise, the GPIO is open and has a fault.

[0004] The existing GPIO automatic testing method has the following problems: the GPIO fault test type is single, and can only detect GPIO with open circuit fault, but cannot detect short circuit fault between GPIO and GPIO. Even if the test is qualified, it cannot guarantee that the GPIO is qualified. Summary of the invention

[0005] The technical solution of the present invention solves the problem that the GPIO fault test has a single type and can only detect GPIOs with open circuit faults, but cannot detect short circuit faults between GPIOs. The GPIO fault test should be able to automatically complete both open circuit fault and short circuit fault tests to ensure that the GPIO is qualified after the test is qualified.

[0006] In a first aspect, an embodiment of the present invention provides a GPIO testing method, the method comprising:

[0007] A pull-down resistor is added to each GPIO of the device to be tested; one of the GPIOs is designated as an input port, called the input GPIO; the remaining GPIOs are called round-test GPIOs; each of the round-test GPIOs is also connected in series with a Schottky diode, with the positive electrode of each Schottky diode connected to its own round-test GPIO and the negative electrode connected to the input GPIO.

[0008] Power on the device under test.

[0009] The GPIOs under test are configured to output mode one by one in turn; the GPIOs under test configured to output mode are called high-level GPIOs under test; the remaining GPIOs are configured to input mode; the GPIOs under test configured to input mode are called input-state GPIOs under test.

[0010] The high level round test GPIO outputs a high level signal.

[0011] Detects the input signals of all GPIOs configured as input mode.

[0012] When the input signal of the input GPIO is the constant high level signal or the constant low level signal, the input GPIO has a fault and the test ends in failure.

[0013] When the input state test GPIO detects the high level signal, it can be determined that the GPIO has a short circuit fault, that is, the device under test has a fault, and the test ends in failure.

[0014] When the input GPIO detects a low level signal, it can be determined that the high level round test GPIO has an open circuit fault, that is, the device under test has a fault, and the test ends in failure.

[0015] In the process that all the GPIOs in the round-test output the high-level signal one by one, the input signal of the input GPIO changes between the high-level signal and the low-level signal, and when the high-level round-test GPIO outputs the high-level signal, each time all the input-state round-test GPIOs detect the low-level signal, and the input GPIO detects the high-level signal, so it can be determined that there is no fault in the device under test and the test is ended.

[0016] In some embodiments, the present invention provides a GPIO testing method, the method further comprising:

[0017] After the device under test is powered on, an open circuit fault pre-check is first performed.

[0018] The open circuit fault pre-check includes:

[0019] Configure all GPIOs to input mode.

[0020] When the GPIO detects the high level signal, there is a GPIO with an open circuit fault, that is, there is a fault in the module to be tested, and the test ends in failure.

[0021] When all the GPIOs detect the low-level signal, there is no GPIO with an open-circuit fault, and the test continues.

[0022] In some embodiments, the present invention provides a GPIO testing method, the method further comprising:

[0023] When the test ends with failure, an error message is displayed.

[0024] In a second aspect, an embodiment of the present invention provides a device for implementing the method described in the first aspect, the device comprising:

[0025] Port configuration unit, used to configure the input / output mode of GPIO.

[0026] The input reading unit is used to read the input signal of the GPIO configured in the input mode.

[0027] The signal output unit is used for signal output of the GPIO configured in output mode.

[0028] The test process unit is used to control the test to be performed according to the process; one of the GPIOs is designated as the input GPIO, and the remaining GPIOs are all round-test GPIOs; the input GPIO is only externally connected to a pull-down resistor; the round-test GPIO is externally connected to a pull-down resistor and a Schottky diode; the positive electrode of each Schottky diode is connected to the respective round-test GPIO, and the negative electrode is connected to the input GPIO; the process includes:

[0029] The port configuration unit configures the round-robin GPIOs to output mode one by one in turn, and the round-robin GPIOs configured to output mode are called high-level round-robin GPIOs; the remaining GPIOs are configured to input mode, and the round-robin GPIOs configured to input mode are called input-state round-robin GPIOs.

[0030] The high-level round-trip GPIO is made to output a high-level signal through the signal output unit.

[0031] The input signal of the GPIO configured as an input port is read by the input reading unit; when the input signal of the input GPIO is the constant high-level signal or the low-level signal, the input GPIO has a fault and the test ends in failure; when the input state test GPIO detects the high-level signal, the GPIO has a short-circuit fault, that is, the device to be tested has a fault, and the test ends in failure; when the input GPIO detects a low-level signal, the high-level test GPIO has an open-circuit fault, that is, the device to be tested has a fault, and the test ends in failure.

[0032] When the input signal of the input GPIO is the constant high level signal or the constant low level signal, the input GPIO has a fault and the test ends in failure.

[0033] In the process that all the GPIOs in the round-test output the high-level signal one by one, the input signal of the input GPIO changes between the high-level signal and the low-level signal, and when the high-level round-test GPIO outputs the high-level signal, each time all the input-state round-test GPIOs detect the low-level signal, and the input GPIO detects the high-level signal, so it can be determined that there is no fault in the device under test and the test is ended.

[0034] In some embodiments, the present invention provides a device for implementing the method described in the first aspect, the device further comprising:

[0035] The open circuit fault pre-check unit is used to perform an open circuit fault pre-check after the device is powered on.

[0036] The open circuit fault pre-check includes:

[0037] All the GPIOs are configured to input mode through the port configuration unit.

[0038] All input signals of the GPIO are read through the input port reading unit.

[0039] When the GPIO detects the high-level signal, there is an open-circuit fault in the GPIO, that is, there is a fault in the device, and the test ends in failure.

[0040] When all the GPIOs detect a low level, there is no GPIO with an open circuit fault, and the test continues.

[0041] In some embodiments, the present invention provides a device for implementing the method described in the first aspect, the device further comprising:

[0042] The fault status display unit is used to prompt an error message when the test ends in failure.

[0043] The beneficial effects of the technical solution of the present invention are:

[0044] The technical solution of the present invention adds a Schottky diode to each round-test GPIO in addition to the pull-down resistor. By utilizing the unidirectional conductivity of the Schottky diode, the high level of the high-level round-test GPIO can be loaded onto the input GPIO through the Schottky diode, while ensuring that the round-test GPIOs do not affect each other. Then, by making the round-test GPIO output high-level signals one by one in turn, the open-circuit fault and the short-circuit fault of the GPIO are automatically detected, thereby improving the detection efficiency, ensuring that after the detection is qualified, all the GPIOs are qualified, and ensuring the qualified rate of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0046] Figure 1 This is an external wiring diagram of a specific embodiment of the GPIO testing method of the present invention.

[0047] Figure 2 The test flow chart of a specific embodiment of the GPIO test method of the present invention.

[0048] Figure 3 The test flow chart of a specific embodiment of the GPIO test method of the present invention. DETAILED DESCRIPTION

[0049] The technical scheme in the embodiment of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiment of the present application. It should be understood by those skilled in the art that the described embodiment is a part of the embodiment of the present invention, rather than all the embodiments. Based on the embodiment in the present application, those skilled in the art can make any appropriate modifications or variations to obtain all other embodiments.

[0050] In a first aspect, an embodiment of the present invention provides a GPIO testing method, the method comprising:

[0051] A pull-down resistor is added to each GPIO of the device to be tested; one of the GPIOs is designated as an input port, called the input GPIO; the remaining GPIOs are called round-test GPIOs; each of the round-test GPIOs is also connected in series with a Schottky diode, with the positive electrode of each Schottky diode connected to its own round-test GPIO and the negative electrode connected to the input GPIO.

[0052] Power on the device under test.

[0053] The GPIOs under test are configured to output mode one by one in turn; the GPIOs under test configured to output mode are called high-level GPIOs under test; the remaining GPIOs are configured to input mode; the GPIOs under test configured to input mode are called input-state GPIOs under test.

[0054] The high level round test GPIO outputs a high level signal.

[0055] Detects the input signals of all GPIOs configured as input mode.

[0056] When the input signal of the input GPIO is the constant high level signal or the constant low level signal, the input GPIO has a fault and the test ends in failure.

[0057] When the input GPIO detects a low level signal, it can be determined that the high level round test GPIO has an open circuit fault, that is, the device under test has a fault, and the test ends in failure.

[0058] When the input state test GPIO detects the high level signal, it can be determined that the GPIO has a short circuit fault, that is, the device under test has a fault, and the test ends in failure.

[0059] In the process that all the GPIOs in the round-test output the high-level signal one by one, the input signal of the input GPIO changes between the high-level signal and the low-level signal, and when the high-level round-test GPIO outputs the high-level signal, each time all the input-state round-test GPIOs detect the low-level signal, and the input GPIO detects the high-level signal, so it can be determined that there is no fault in the device under test and the test is ended.

[0060] In this embodiment, if Figure 1 As shown, it is the external wiring diagram of the GPIO of the device to be tested. The device here can be a module or a chip. Each GPIO is externally connected to a pull-down resistor. One GPIO is designated as an input port. The input port can be any GPIO before designation. After designation, it will not be changed during the test process. The remaining GPIOs other than the input port are all the round-test GPIOs. Each round-test GPIO is connected to a Schottky diode. The positive pole of each Schottky diode is connected to the respective round-test GPIO, and the negative pole is connected to the input GPIO. By using the unidirectional conductivity of the Schottky diode, the high level of the high-level round-test GPIO can be loaded to the input GPIO through the Schottky diode, while ensuring that the round-test GPIOs will not affect each other. Therefore, when each round-test GPIO outputs a high-level signal one by one, the detection can be completed by reading the input signal of the other GPIO configured in input mode.

[0061] After the pull-down resistor and the Schottky diode are connected, the device to be tested is powered on and turned on.

[0062] like Figure 2As shown, it is a flow chart of the present embodiment. The GPIO is configured through the port configuration unit. First, the first GPIO to be tested is configured to the output mode, and the GPIO to be tested configured to the output mode is called the high-level GPIO to be tested. The remaining GPIOs are all configured to the input mode, and the GPIO to be tested configured to the input mode is called the input-state GPIO to be tested. In other words, the input state includes the input GPIO and the input-state GPIO to be tested.

[0063] The signal output unit enables the high-level round-robin GPIO to output a high-level signal. Because only one of the GPIOs is configured as an input mode each time, only one of the high-level round-robin GPIOs outputs a high-level signal each time.

[0064] The input signal of the GPIO configured in the input mode is read by the input reading unit.

[0065] When the input GPIO detects a rising edge or a falling edge, it indicates that the input GPIO can work normally. When the input signal of the input GPIO is a constant high level signal or a constant low level signal, the input GPIO has a fault and the test ends in failure. The rising edge or the falling edge can be detected once and then not detected again, and the test can be directly skipped to the next step, or it can be detected every time.

[0066] Because of the isolation by the Schottky diode, under normal circumstances all the input state test GPIOs should detect low-level signals. Therefore, when the input state test GPIO detects a high-level signal, it can be determined that there is a GPIO with a short-circuit fault, that is, the device under test has a fault and the test ends in failure.

[0067] Because the Schottky diode has unidirectional conductivity, the high-level signal output by the high-level round-test GPIO should be detected by the input GPIO. Therefore, when the input GPIO detects a low-level signal, it can be determined that the high-level round-test GPIO has an open circuit fault, that is, the device under test has a fault, and the test ends in failure.

[0068] The test process is controlled by the test process unit. The process is: suppose there are m GPIOs in total, one of which is the input GPIO, and the rest are the round-test GPIOs. When the first round-test GPIO outputs a high-level signal, the input round-test GPIO detects low-level signals, and the input GPIO detects a low-level signal, then no fault is detected in this test, and the test can continue. Next, configure the second round-test GPIO to output mode, output a high-level signal, and configure the remaining GPIOs to output mode, and repeat the aforementioned test process. If the test does not end in failure due to the detection of a fault, replace the next round-test GPIO to output a high-level signal, and continue the test until the last one, the mth -1 GPIOs to be tested in this round. If the test of the last GPIO in this round is also successfully completed without failure due to fault detection, then all GPIOs of the device to be tested have passed the test, with no open circuit faults and no short circuit faults. It should be pointed out that the judgment that the input GPIO detects a high-level signal and the judgment that all the input GPIOs in this round of testing detect a low-level signal have no logical order, and can be performed simultaneously in actual testing, as long as the device that passes the test can meet both conditions at the same time. Figure 2 In the above, as mentioned above, the detection of whether the input GPIO has a rising edge or a falling edge can be performed once and then no longer detected, and the next step can be directly jumped to, or the detection can be performed every time. Similarly, the detection of the rising edge or the falling edge of the input GPIO, the order of first or later is not important, what is important is to ensure that each substantial condition is met.

[0069] During the test, the configuration, output, reading, judgment and other operations of the GPIO can be performed bit by bit or as a whole on a byte or several bytes.

[0070] In some embodiments, the present invention provides a GPIO testing method, the method further comprising:

[0071] After the device under test is powered on, an open circuit fault pre-check is first performed.

[0072] The open circuit fault pre-check includes:

[0073] Configure all GPIOs to input mode.

[0074] When the GPIO detects the high level signal, there is a GPIO with an open circuit fault, that is, there is a fault in the module to be tested, and the test ends in failure.

[0075] When all the GPIOs detect the low-level signal, there is no GPIO with an open-circuit fault, and the test continues.

[0076] In this embodiment, if Figure 3 As shown in the figure, before the formal test, an open circuit fault pre-check is added. Because the operation of the open circuit fault is relatively simple and takes very little time, if an open circuit fault is detected in the pre-check, the test does not need to be continued, and the next device can be tested immediately, which speeds up the test rhythm and saves the total test time.

[0077] In this open circuit fault pre-check, if Figure 3 As shown, the open circuit fault pre-check unit first configures all the GPIOs to input mode through the port configuration unit. Under normal circumstances, because of the pull-down resistor, all the GPIOs should detect the low-level signal. When the GPIO detects the high-level signal, it indicates that there is a GPIO with an open circuit fault, that is, the module to be tested has a fault, and the test ends in failure. Only when all the GPIOs detect the low-level signal, it indicates that there is no GPIO with an open circuit fault, and the test continues.

[0078] Because the pre-check of the open circuit fault has been carried out, in the subsequent test, the judgment of the open circuit fault can be omitted, or the test can be continued and a secondary check can be performed.

[0079] In some embodiments, the present invention provides a GPIO testing method, the method further comprising:

[0080] When the test ends with failure, an error message is displayed.

[0081] In this embodiment, when the test ends in failure, the error message is prompted. The error message can be a fault light on the device or an error warning on the screen. If the device has a serial number or other product traceability mark, the serial number or mark can be entered into the database, and the specific fault information can be entered at the same time, so as to perform statistical analysis afterwards and find ways to improve product yield.

[0082] In a second aspect, an embodiment of the present invention provides a device for implementing the method described in the first aspect, the device comprising:

[0083] Port configuration unit, used to configure the input / output mode of GPIO.

[0084] The input reading unit is used to read the input signal of the GPIO configured in the input mode.

[0085] The signal output unit is used for signal output of the GPIO configured in output mode.

[0086] The test process unit is used to control the test to be performed according to the process; one of the GPIOs is designated as the input GPIO, and the remaining GPIOs are all round-test GPIOs; the input GPIO is only externally connected to a pull-down resistor; the round-test GPIO is externally connected to a pull-down resistor and a Schottky diode; the positive electrode of each Schottky diode is connected to the respective round-test GPIO, and the negative electrode is connected to the input GPIO; the process includes:

[0087] The port configuration unit configures the round-robin GPIOs to output mode one by one in turn, and the round-robin GPIOs configured to output mode are called high-level round-robin GPIOs; the remaining GPIOs are configured to input mode, and the round-robin GPIOs configured to input mode are called input-state round-robin GPIOs.

[0088] The high-level round-trip GPIO is made to output a high-level signal through the signal output unit.

[0089] The input signal of the GPIO configured as an input port is read by the input reading unit; when the input signal of the input GPIO is the constant high-level signal or the low-level signal, the input GPIO has a fault and the test ends in failure; when the input state test GPIO detects the high-level signal, the GPIO has a short-circuit fault, that is, the device to be tested has a fault, and the test ends in failure; when the input GPIO detects a low-level signal, the high-level test GPIO has an open-circuit fault, that is, the device to be tested has a fault, and the test ends in failure.

[0090] In the process that all the GPIOs in the round-test output the high-level signal one by one, the input signal of the input GPIO changes between the high-level signal and the low-level signal, and when the high-level round-test GPIO outputs the high-level signal, each time all the input-state round-test GPIOs detect the low-level signal, and the input GPIO detects the high-level signal, so it can be determined that there is no fault in the device under test and the test is ended.

[0091] In this embodiment, if Figure 1As shown, it is the external wiring diagram of the GPIO of the device to be tested. The device here can be a module or a chip. Each GPIO is externally connected to a pull-down resistor. One GPIO is designated as an input port. The input port can be any GPIO before designation. After designation, it will not be changed during the test process. The remaining GPIOs other than the input port are all the round-test GPIOs. Each round-test GPIO is connected to a Schottky diode. The positive pole of each Schottky diode is connected to the respective round-test GPIO, and the negative pole is connected to the input GPIO. By using the unidirectional conductivity of the Schottky diode, the high level of the high-level round-test GPIO can be loaded to the input GPIO through the Schottky diode, while ensuring that the round-test GPIOs will not affect each other. Therefore, when each round-test GPIO outputs a high-level signal one by one, the detection can be completed by reading the input signal of the other GPIO configured in input mode.

[0092] After the pull-down resistor and the Schottky diode are connected, the device to be tested is powered on and turned on.

[0093] like Figure 2 As shown, it is a flow chart of the present embodiment. The GPIO is configured through the port configuration unit. First, the first GPIO to be tested is configured to the output mode, and the GPIO to be tested configured to the output mode is called the high-level GPIO to be tested. The remaining GPIOs are all configured to the input mode, and the GPIO to be tested configured to the input mode is called the input-state GPIO to be tested. In other words, the input state includes the input GPIO and the input-state GPIO to be tested.

[0094] The signal output unit enables the high-level round-robin GPIO to output a high-level signal. Because only one of the GPIOs is configured as an input mode each time, only one of the high-level round-robin GPIOs outputs a high-level signal each time.

[0095] The input signal of the GPIO configured in the input mode is read by the input reading unit.

[0096] When the input GPIO detects a rising edge or a falling edge, it indicates that the input GPIO can work normally. When the input signal of the input GPIO is a constant high level signal or a constant low level signal, the input GPIO has a fault and the test ends in failure. The rising edge or the falling edge can be detected once and then not detected again, and the test can be directly skipped to the next step, or it can be detected every time.

[0097] Because of the isolation by the Schottky diode, under normal circumstances all the input state test GPIOs should detect low-level signals. Therefore, when the input state test GPIO detects a high-level signal, it can be determined that there is a GPIO with a short-circuit fault, that is, the device under test has a fault and the test ends in failure.

[0098] Because the Schottky diode has unidirectional conductivity, the high-level signal output by the high-level round-test GPIO should be detected by the input GPIO. Therefore, when the input GPIO detects a low-level signal, it can be determined that the high-level round-test GPIO has an open circuit fault, that is, the device under test has a fault, and the test ends in failure.

[0099] The test process is controlled by the test process unit. The process is: suppose there are m GPIOs in total, one of which is the input GPIO, and the rest are the round-test GPIOs. When the first round-test GPIO outputs a high-level signal, the input round-test GPIO detects low-level signals, and the input GPIO detects a low-level signal, then no fault is detected in this test, and the test can continue. Next, configure the second round-test GPIO to output mode, output a high-level signal, and configure the remaining GPIOs to output mode, and repeat the aforementioned test process. If the test does not end in failure due to the detection of a fault, replace the next round-test GPIO to output a high-level signal, and continue the test until the last one, the mth -1 GPIOs to be tested in this round. If the test of the last GPIO in this round is also successfully completed without failure due to fault detection, then all GPIOs of the device to be tested have passed the test, with no open circuit faults and no short circuit faults. It should be pointed out that the judgment that the input GPIO detects a high-level signal and the judgment that all the input GPIOs in this round of testing detect a low-level signal have no logical order, and can be performed simultaneously in actual testing, as long as the device that passes the test can meet both conditions at the same time. Figure 2 In the above, as mentioned above, the detection of whether the input GPIO has a rising edge or a falling edge can be performed once and then no longer detected, and the next step can be directly jumped to, or the detection can be performed every time. Similarly, the detection of the rising edge or the falling edge of the input GPIO, the order of first or later is not important, what is important is to ensure that each substantial condition is met.

[0100] During the test, the configuration, output, reading, judgment and other operations of the GPIO can be performed bit by bit or as a whole on a byte or several bytes.

[0101] In some embodiments, the present invention provides a device for implementing the method described in the first aspect, the device further comprising:

[0102] The open circuit fault pre-check unit is used to perform an open circuit fault pre-check after the device is powered on.

[0103] The open circuit fault pre-check includes:

[0104] All the GPIOs are configured to input mode through the port configuration unit.

[0105] All input signals of the GPIO are read through the input port reading unit.

[0106] When the GPIO detects the high-level signal, there is an open-circuit fault in the GPIO, that is, there is a fault in the device, and the test ends in failure.

[0107] When all the GPIOs detect a low level, there is no GPIO with an open circuit fault, and the test continues.

[0108] In this embodiment, if Figure 3 As shown in the figure, before the formal test, an open circuit fault pre-check is added. Because the operation of the open circuit fault is relatively simple and takes very little time, if an open circuit fault is detected in the pre-check, the test does not need to be continued, and the next device can be tested immediately, which speeds up the test rhythm and saves the total test time.

[0109] In this open circuit fault pre-check, if Figure 3 As shown, the open circuit fault pre-check unit first configures all the GPIOs to input mode through the port configuration unit. Under normal circumstances, because of the pull-down resistor, all the GPIOs should detect the low-level signal. When the GPIO detects the high-level signal, it indicates that there is a GPIO with an open circuit fault, that is, the module to be tested has a fault, and the test ends in failure. Only when all the GPIOs detect the low-level signal, it indicates that there is no GPIO with an open circuit fault, and the test continues.

[0110] Because the pre-check of the open circuit fault has been carried out, in the subsequent test, the judgment of the open circuit fault can be omitted, or the test can be continued and a secondary check can be performed.

[0111] In some embodiments, the present invention provides a device for implementing the method described in the first aspect, the device further comprising:

[0112] The fault status display unit is used to prompt an error message when the test ends in failure.

[0113] In this embodiment, when the test ends in failure, the error message is prompted. The error message can be a fault light on the device or an error warning on the screen. If the device has a serial number or other product traceability mark, the serial number or mark can be entered into the database, and the specific fault information can be entered at the same time, so as to perform statistical analysis afterwards and find ways to improve product yield.

Claims

1. A GPIO testing method, characterized in that: The method comprises: A pull-down resistor is added to each GPIO of the device to be tested; one of the GPIOs is designated as an input port, called an input GPIO; the remaining GPIOs are called round-test GPIOs; each of the round-test GPIOs is also connected in series with a Schottky diode, the positive electrode of each Schottky diode is connected to the respective round-test GPIO, and the negative electrode is connected to the input GPIO; Powering on the device under test; The round-test GPIOs are configured to output mode one by one in sequence; the round-test GPIOs configured to output mode are called high-level round-test GPIOs; the remaining round-test GPIOs are configured to input mode; The round-test GPIO configured in input mode is called input-state round-test GPIO; The high-level round-test GPIO outputs a high-level signal; Detecting input signals of all the GPIOs configured in input mode; When the input signal of the input GPIO is the constant high level signal or low level signal, the input GPIO has a fault, and the test ends in failure; When the input state test GPIO detects the high level signal, it can be determined that there is the GPIO with a short circuit fault, that is, the device under test has a fault, and the test ends in failure; When the input GPIO detects a low level signal, it can be determined that the high level round test GPIO has an open circuit fault, that is, the device under test has a fault, and the test ends in failure; In the process that all the round-test GPIOs output the high-level signal one by one in turn, the input signal of the input GPIO changes between the high-level signal and the low-level signal, and when the high-level round-test GPIO outputs the high-level signal, all the input-state round-test GPIOs detect the low-level signal each time, and the input GPIO detects the high-level signal, so it can be determined that there is no fault in the device under test and the test is ended.

2. The method according to claim 1, characterized in that The method further comprises: After the device to be tested is powered on, an open circuit fault pre-check is first performed; The open circuit fault pre-check includes: Configure all of the GPIOs to input mode; When the GPIO detects the high level signal, there is a GPIO with an open circuit fault, that is, the device under test has a fault, and the test ends in failure; When all the GPIOs detect the low-level signal, there is no GPIO with an open-circuit fault, and the test continues.

3. The method according to claim 1 or 2, characterized in that: The method further comprises: When the test ends in failure, an error message is prompted.

4. A device for implementing the method according to claim 1, characterized in that: The device comprises: Port configuration unit, used to configure the input / output mode of GPIO; An input reading unit, configured to read an input signal of the GPIO configured in input mode; A signal output unit, configured to output the signal of the GPIO configured in output mode; The test process unit is used to control the test to be performed according to the process; designate one of the GPIOs as an input GPIO, and the remaining GPIOs are all round-test GPIOs; the input GPIO is only externally connected to a pull-down resistor; the round-test GPIO is externally connected to a pull-down resistor and a Schottky diode; the positive electrode of each Schottky diode is connected to the respective round-test GPIO, and the negative electrode is connected to the input GPIO; the process includes: The round-test GPIOs are configured into output mode one by one in sequence through the port configuration unit, and the round-test GPIOs configured into output mode are called high-level round-test GPIOs; the remaining round-test GPIOs are configured into input mode, and the round-test GPIOs configured into input mode are called input-state round-test GPIOs; Make the high-level round-trip test GPIO output a high-level signal through the signal output unit; The input signal of the GPIO configured as an input port is read by the input reading unit; when the input signal of the input GPIO is the constant high-level signal or low-level signal, the input GPIO has a fault, and the test ends in failure; when the input state test GPIO detects the high-level signal, there is a GPIO with a short-circuit fault, that is, the device to be tested has a fault, and the test ends in failure; when the input GPIO detects a low-level signal, the high-level test GPIO has an open-circuit fault, that is, the device to be tested has a fault, and the test ends in failure; In the process that all the round-test GPIOs output the high-level signal one by one in turn, the input signal of the input GPIO changes between the high-level signal and the low-level signal, and when the high-level round-test GPIO outputs the high-level signal, all the input-state round-test GPIOs detect low-level signals each time, and the input GPIO detects the high-level signal, so it can be determined that there is no fault in the device under test and the test is ended.

5. The device according to claim 4, characterized in that The device further comprises: An open circuit fault pre-detection unit, used to perform an open circuit fault pre-detection after the device is powered on; The open circuit fault pre-check includes: Configuring all the GPIOs to input mode through the port configuration unit; Reading input signals of all the GPIOs through the input port reading unit; When the GPIO detects the high-level signal, there is a GPIO with an open circuit fault, that is, the device has a fault, and the test ends in failure; When all the GPIOs detect a low level, there is no GPIO with an open circuit fault, and the test continues.

6. The device according to claim 4 or 5, characterized in that The device further comprises: The fault status display unit is used to prompt an error message when the test ends in failure.

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