Chip and electronic device

Abstract

An embodiment of the present application provides a chip and an electronic device, including: a multi-layer wiring layer arranged in a channel area; each wiring layer in the multi-layer wiring layer is wired along one direction; wherein the first wiring layer in the multi-layer wiring layer arranges a group of signal lines along the channel direction of the channel area; and the second wiring layer adjacent to the first wiring layer is set as a protective ground plane.

Description

Technical Field

[0001] The present application relates to the field of chips, and in particular to a chip and an electronic device. Background Art

[0002] At present, the chip design method of system-on-chip (SoC) chips or media processing chips is channel design. Channel-designed chips have complex chip structures, a large number of integrated IPs and IP types, complex chip clock definitions, and complex product definitions. Therefore, the design of channel-designed chips is very difficult and is usually achieved by reserving channels on the chip and routing in the channels.

[0003] However, a large number of signal lines run in parallel in a narrow channel. The mutual capacitance and mutual inductance between adjacent signal lines cause the signal to couple its own voltage, current and other signal parts to adjacent signal lines during the transmission process, which easily causes crosstalk between signals.

[0004] Currently, signal crosstalk can be reduced by increasing the spacing between signal lines or adding a protective ground line between adjacent signal lines. However, the above method will increase the channel area of ​​the chip, thereby increasing the manufacturing cost of the chip. Summary of the invention

[0005] The embodiments of the present application provide a chip and an electronic device, which can reduce crosstalk between signals without changing the channel area of ​​the chip, thereby reducing the manufacturing cost of the chip.

[0006] The technical solution of this application is implemented as follows:

[0007] The embodiment of the present application provides a chip, the chip comprising: a plurality of wiring layers arranged in a channel region; each wiring layer in the plurality of wiring layers is wired along one direction;

[0008] Wherein, a first wiring layer in the multi-layer wiring layer arranges a group of signal lines along the channel direction of the channel region; and a second wiring layer adjacent to the first wiring layer is set as a protective ground plane.

[0009] In the above chip, wiring directions of the first wiring layer and the second wiring layer are perpendicular to each other.

[0010] In the above chip, the second wiring layer arranges a group of ground lines along a direction perpendicular to the channel direction.

[0011] In the above chip, the channel region includes a first channel sub-region and a second channel sub-region; a channel direction of the first channel sub-region is perpendicular to a channel direction of the second channel sub-region;

[0012] In a case where the wiring direction of the first wiring layer is the same as the channel direction of the first channel sub-region, a first wiring region of the first wiring layer arranges a group of signal lines along the channel direction of the first channel sub-region, and a second wiring region of the first wiring layer arranges a group of ground lines along the channel direction of the first channel sub-region; the first wiring region corresponds to the first channel sub-region, and the second wiring region corresponds to the second channel sub-region;

[0013] When the wiring direction of the first wiring layer is the same as the channel direction of the second channel sub-region, the second wiring region arranges a group of signal lines along the channel direction of the second channel sub-region, and the first wiring region arranges a group of ground lines along the channel direction of the second channel sub-region.

[0014] In the above chip, when the wiring direction of the first wiring layer is the same as the channel direction of the first channel sub-region, the third wiring region of the second wiring layer arranges a group of ground lines along the channel direction of the first channel sub-region, and the fourth wiring region of the second wiring layer arranges a group of signal lines along the channel direction of the first channel sub-region; the third wiring region corresponds to the first channel sub-region, and the fourth wiring region corresponds to the second channel sub-region;

[0015] When the wiring direction of the first wiring layer is the same as the channel direction of the second channel sub-region, the fourth wiring region arranges a group of ground lines along the channel direction of the second channel sub-region, and the third wiring region arranges a group of signal lines along the channel direction of the second channel sub-region.

[0016] In the above chip, a signal transmission hole is provided at the intersection of the signal lines of the first wiring layer and the second wiring layer;

[0017] When the wiring direction of the first wiring layer is the same as the channel direction of the first channel sub-region, the signal transmission hole conducts a group of signal lines arranged in the first wiring region and a group of signal lines arranged in the fourth wiring region;

[0018] When the wiring direction of the first wiring layer is the same as the channel direction of the second channel sub-region, the signal transmission hole conducts a group of signal lines arranged in the second wiring region and a group of signal lines arranged in the third wiring region.

[0019] In the above chip, a power supply point is set on the top layer of the multi-layer wiring layer, power lines are arranged on each wiring layer of the multi-layer wiring layer, and power holes are set at the intersections of the power lines of adjacent wiring layers.

[0020] In the above chip, the power supply point supplies power to the multiple wiring layers layer by layer through the power supply lines and power supply holes of each wiring layer.

[0021] In the above chip, the group of ground lines are arranged in parallel in the second wiring layer.

[0022] An embodiment of the present application provides an electronic device, which includes a chip as described in any one of the above items.

[0023] The embodiment of the present application provides a chip and an electronic device, the chip comprising: a multi-layer wiring layer arranged in a channel region; each wiring layer in the multi-layer wiring layer is wired in one direction; wherein the first wiring layer in the multi-layer wiring layer arranges a group of signal lines along the channel direction of the channel region; the second wiring layer adjacent to the first wiring layer is set as a protective ground plane. By adopting the above chip implementation scheme, the first wiring layer in the multi-layer wiring layer is set to arrange a group of signal lines along the channel direction of the channel region, and the second wiring layer adjacent to the first wiring layer is set as a protective ground plane, the second wiring layer can be used to reduce the crosstalk of the signal in the channel without occupying the winding resources and increasing the chip area, thereby reducing the manufacturing cost of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a chip schematic diagram of a channelless chip;

[0025] Figure 2 The chip schematic diagram of the channel chip;

[0026] Figure 3 This is a schematic diagram of the channel wiring of the channel chip;

[0027] Figure 4 This is a schematic diagram of the signal line phase of the channel chip;

[0028] Figure 5 A schematic diagram of a channel wiring for a current channel chip Figure 1 ;

[0029] Figure 6 A schematic diagram of a channel wiring for a current channel chip Figure 2 ;

[0030] Figure 7 A schematic diagram of the structure of a chip provided in an embodiment of the present application;

[0031] Figure 8 A wiring diagram of an exemplary multi-layer wiring layer provided in an embodiment of the present application Figure 1 ;

[0032] Fig. 9A wiring diagram of an exemplary wiring layer in an L-type channel region provided in an embodiment of the present application Figure 2 ;

[0033] Fig.10 is an exemplary channel wiring diagram;

[0034] Fig.11 is a schematic diagram of signal crosstalk of an exemplary conventional chip;

[0035] Fig.12 An exemplary signal crosstalk schematic diagram provided for an embodiment of the present application;

[0036] Fig.13 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0038] According to different product features, the chip can include two implementation modes: channel and channelless. Among them, the chip structure and clock structure of the channelless chip are relatively simple, with a large number of repeated instantiation IPs, such as Figure 1 As shown in the figure, a large number of repeated digital signal processing (DSP) modules are arranged in the channelless chip, as well as a double data rate synchronous dynamic random access memory (DDR) module, a logic module, a CPU module and a SERDES module. These modules are closely connected in the channelless chip. Such chips are usually large in scale. The use of channelless chips can greatly save chip area, such as data communication chips, video processing chips, artificial intelligence (AI) chips, etc.

[0039] The chip structure of Channel chip is relatively complex, and the number and types of integrated IP are large. The design of this type of chip is very difficult, and it is generally implemented by channel routing, such as SoC chip, media processing chip, etc. Figure 2As shown in FIG. 1 , the channel chip includes a graphics processing unit (GPU) module, a DDR module, a universal serial bus (USB) module, a neural-network processing unit (NPU) module, a peri module, a peripheral component interconnect express (PCIE) module, a CPU module, and an MDM module. The above modules are arranged on both sides of the channel of the channel chip, and the communication and control between the above modules are realized through the signal lines arranged in the channel. The channel routing of the channel chip can be as follows: Figure 3 As shown in FIG. 1 , 7 signal lines are arranged in parallel in the channel region, and a BUF unit is set at the same position of each signal line. The BUF unit is used to maintain the waveform when transmitting the signal and solve the signal attenuation during the transmission process. The crosstalk between the signals is as shown in FIG. Figure 4 As shown in FIG. 1 , the greatest impact of the NET_aggressor_a signal line and the NET_aggressor_c signal line on the NET_victim signal line occurs when all three signal lines are at the rising edge, at which time the crosstalk is completely superimposed.

[0040] In order to reduce the signal crosstalk in the channel area of ​​the channel chip, the signal line spacing can be widened by routing. Figure 3 and Figure 5 , only three signal lines can be arranged in parallel in the channel area of ​​the same width; or a protective ground line can be added between adjacent signal lines, refer to Figure 3 and Figure 6 , only three signal lines can be arranged in parallel in the channel area of ​​the same width. However, the above measures are all at the expense of the channel space in exchange for the reduction of crosstalk. The larger the area of ​​the channel chip, the higher the manufacturing cost of the chip.

[0041] In order to solve the above problems, the present application proposes a chip and a signal transmission method within the chip, which will be specifically described through the following embodiments.

[0042] The present application embodiment provides a chip 1, such as Figure 7 As shown, the chip 1 comprises: a plurality of wiring layers arranged in a channel region; each wiring layer in the plurality of wiring layers is wired along one direction;

[0043] Wherein, a first wiring layer in the multi-layer wiring layer arranges a group of signal lines along the channel direction of the channel region; and a second wiring layer adjacent to the first wiring layer is set as a protective ground plane.

[0044] In the embodiment of the present application, the chip may be a channel-designed chip such as a SoC chip or a media processing chip.

[0045] It should be noted that the number of wiring layers in the chip can be determined according to factors such as chip type, channel width, signal line spacing, number of modules on the chip, etc. The specific number can be selected according to actual conditions, and the embodiments of this application do not make specific limitations.

[0046] In the embodiment of the present application, the number of second wiring layers is one or two. When the first wiring layer is at the top layer or the bottom layer of the multi-layer wiring layer, the number of second wiring layers adjacent to the first wiring layer is one; when the first wiring layer is not at the top layer or the bottom layer of the wiring layer, the number of second wiring layers adjacent to the first wiring layer is two. The specific number of second wiring layers is determined according to the position of the first wiring layer in the multi-layer wiring layer, and the embodiment of the present application does not make any specific limitation.

[0047] It should be noted that the bottom layer of the multi-layer wiring layer is a wiring layer adjacent to the device layer of the chip. It can be understood that the top layer of the multi-layer wiring layer is a wiring layer farthest from the device layer.

[0048] In the embodiment of the present application, the channel direction of the channel region can be horizontal and / or vertical, that is, the channel region can be a horizontal channel region, a vertical channel region, or a channel region composed of a horizontal channel part and a vertical channel part. The specific setting can be based on actual conditions, and the embodiment of the present application does not make specific limitations.

[0049] In an optional embodiment, if Figure 8 As shown, for the lateral channel, a group of signal lines are arranged horizontally in the wiring layer of the Mn layer, and a protective ground plane is respectively provided in the wiring layer of the Mn+1 layer and the wiring layer of the Mn-1 layer.

[0050] In an embodiment of the present application, a group of signal lines are arranged in parallel in the channel area, wherein the number of signal lines is multiple, and a group of relay units are provided on each signal line for maintaining the reporting waveform during data transmission and reducing attenuation during data transmission.

[0051] Optionally, wiring directions of the first wiring layer and the second wiring layer are perpendicular.

[0052] It should be noted that since each wiring layer is wired in one direction and the wiring directions of the first wiring layer and the second wiring layer are perpendicular, if the first wiring layer is set to be wired in the channel direction, the second wiring layer is wired in a direction perpendicular to the channel direction.

[0053] It should be noted that since the wiring directions of the first wiring layer and the second wiring layer are perpendicular, that is, the multi-layer wiring layers are wired layer by layer in the wiring form of horizontal wiring-vertical wiring-horizontal wiring, or vertical wiring-horizontal wiring-vertical wiring.

[0054] Furthermore, for the lateral channel, a group of signal lines are arranged horizontally in the wiring layer of the Mn layer, and a protective ground plane is set in the wiring layer of the Mn+1 layer and the wiring layer of the Mn-1 layer. Then a group of signal lines are still arranged horizontally in the wiring layer of the Mn+2 layer and the wiring layer of the Mn-2 layer, and a protective ground plane is set in the wiring layer of the Mn+3 layer and the wiring layer of the Mn-3 layer, and so on, until the layout and wiring of the multiple wiring layers are completed.

[0055] Optionally, the second wiring layer arranges a group of ground lines along a direction perpendicular to the channel direction.

[0056] In the embodiment of the present application, since the wiring direction between the second wiring layer is perpendicular to the first wiring layer, the protection ground plane can be provided in the second wiring layer by arranging a group of ground lines in a direction perpendicular to the channel direction.

[0057] It should be noted that the number of a group of ground wires can be determined based on the degree of anti-crosstalk between signals or other parameters. The embodiments of the present application do not make specific limitations. It can be understood that the more the number of a group of ground wires, the higher the degree of anti-crosstalk between signals.

[0058] Optionally, the group of ground lines are arranged in parallel in the second wiring layer.

[0059] For a horizontal channel, the first wiring layer arranges a group of signal lines horizontally, and the second wiring layer arranges a group of ground lines vertically; for a vertical channel, the first wiring layer arranges a group of signal lines vertically, and the second wiring layer arranges a group of ground lines horizontally.

[0060] Optionally, the channel region includes a first channel sub-region and a second channel sub-region; a channel direction of the first channel sub-region is perpendicular to a channel direction of the second channel sub-region;

[0061] In a case where the wiring direction of the first wiring layer is the same as the channel direction of the first channel sub-region, a first wiring region of the first wiring layer arranges a group of signal lines along the channel direction of the first channel sub-region, and a second wiring region of the first wiring layer arranges a group of ground lines along the channel direction of the first channel sub-region; the first wiring region corresponds to the first channel sub-region, and the second wiring region corresponds to the second channel sub-region;

[0062] When the wiring direction of the first wiring layer is the same as the channel direction of the second channel sub-region, the second wiring region arranges a group of signal lines along the channel direction of the second channel sub-region, and the first wiring region arranges a group of ground lines along the channel direction of the second channel sub-region.

[0063] It should be noted that, in practical applications, the direction of the channel region of the chip can be determined according to the specific arrangement of each functional module in the chip, and the type of the channel region can be a transverse channel, a longitudinal channel, or a combined channel region of a transverse channel sub-region and a longitudinal channel sub-region such as an L-shaped channel. For the combined channel region, the channel region is divided into a first channel sub-region and a second channel sub-region, wherein the channel directions of the first channel sub-region and the second channel sub-region are perpendicular, that is, when the channel direction of the first channel sub-region is transverse, the channel direction of the second channel sub-region is longitudinal; when the channel direction of the first channel sub-region is longitudinal, the channel direction of the second channel sub-region is transverse.

[0064] It should be noted that the number of the first channel sub-regions is at least one, the number of the second channel sub-regions is at least one, and the first channel sub-regions and the second channel sub-regions are alternately connected.

[0065] In the embodiment of the present application, for the combined channel region, each wiring layer in the multi-layer wiring layer is also divided into two regions accordingly, and for the first wiring layer, it is divided into a first wiring region and a second wiring region, wherein the first wiring layer corresponds to the first channel sub-region, and the second wiring layer corresponds to the second channel sub-region. In the case where the wiring direction of the first wiring layer is set to be the same as the channel direction of the first channel sub-region, the first wiring region arranges a group of signal lines along the channel direction of the first channel sub-region, and the second wiring region arranges a group of ground lines along the channel direction of the first channel sub-region; correspondingly, in the case where the wiring direction of the first wiring layer is set to be the same as the channel direction of the second channel sub-region, the first wiring region arranges a group of ground lines along the channel direction of the second channel sub-region, and the second wiring region arranges a group of signal lines along the channel direction of the second channel sub-region.

[0066] Exemplarily, the wiring direction of the first wiring layer is set to horizontal wiring. When the channel direction of the first channel sub-region is horizontal and the channel direction of the second channel sub-region is vertical, a group of signal lines are horizontally arranged in the first wiring region corresponding to the first channel sub-region, and a group of ground lines are horizontally arranged in the second wiring region corresponding to the second channel sub-region; when the channel direction of the first channel sub-region is vertical and the channel direction of the second channel sub-region is horizontal, a group of ground lines are horizontally arranged in the first wiring region, and a group of signal lines are horizontally arranged in the second wiring region.

[0067] Optionally, when the wiring direction of the first wiring layer is the same as the channel direction of the first channel sub-region, the third wiring region of the second wiring layer arranges a group of ground lines along the channel direction of the second channel sub-region, and the fourth wiring region of the second wiring layer arranges a group of signal lines along the channel direction of the second channel sub-region; the third wiring region corresponds to the first channel sub-region, and the fourth wiring region corresponds to the second channel sub-region;

[0068] When the wiring direction of the first wiring layer is the same as the channel direction of the second channel sub-region, the fourth wiring region arranges a group of ground lines along the channel direction of the first channel sub-region, and the third wiring region arranges a group of signal lines along the channel direction of the first channel sub-region.

[0069] It should be noted that, for the combined channel region, the second wiring layer adjacent to the first wiring layer is also divided into a third wiring region and a fourth wiring region, wherein the third wiring region corresponds to the first channel sub-region, and the fourth wiring region corresponds to the second channel sub-region. Thus, the first channel sub-region corresponds to the first wiring region and the third wiring region, respectively, and the second channel sub-region corresponds to the second wiring region and the fourth wiring region, respectively. In the case where the wiring direction of the first wiring layer is set to be the same as the channel direction of the first channel sub-region, the wiring direction of the second wiring layer is the same as the channel direction of the second channel sub-region. At this time, the third wiring region arranges a group of ground lines along the channel direction of the second channel sub-region, and the fourth wiring region arranges a group of signal lines along the channel direction of the second channel sub-region; in the case where the wiring direction of the first wiring layer is set to be the same as the channel direction of the second channel sub-region, the wiring direction of the second wiring layer is the same as the channel direction of the first channel sub-region. At this time, the third wiring region arranges a group of signal lines along the channel direction of the first channel sub-region, and the fourth wiring region arranges a group of ground lines along the channel direction of the first channel sub-region.

[0070] Exemplarily, the wiring direction of the first wiring layer is set to horizontal wiring, and the wiring direction of the second wiring layer is vertical wiring. When the channel direction of the first channel sub-region is horizontal and the channel direction of the second channel sub-region is vertical, the third wiring region corresponding to the first channel sub-region arranges a group of ground lines vertically, and the fourth wiring region corresponding to the second channel sub-region arranges a group of signal lines vertically; when the channel direction of the first channel sub-region is vertical and the channel direction of the second channel sub-region is horizontal, the third wiring region arranges a group of signal lines vertically, and the fourth wiring region arranges a group of ground lines vertically.

[0071] like Fig. 9 As shown, for the L-shaped channel region, two wiring layers, wiring layer 1 and wiring layer 2, are arranged thereon, and wiring layer 1 includes wiring area 10 and wiring area 11 (through Fig. 9The wiring layer 2 includes a wiring area 20 and a wiring area 21 (divided by the dotted line in FIG. Fig. 9 ), the wiring area 10 and the wiring area 20 correspond to the channel sub-area 1 of the L-shaped channel area, and the wiring area 11 and the wiring area 21 correspond to the channel sub-area 2 of the L-shaped channel area; wherein, the channel direction of the channel sub-area 1 is horizontal, and the channel direction of the channel sub-area 2 is vertical, the wiring direction of the wiring layer 1 is horizontal, and the wiring direction of the wiring layer 2 is vertical, then the wiring area 10 arranges a group of signal lines horizontally ( Fig. 9 The wiring area 20 is vertically arranged with a group of ground lines ( Fig. 9 A group of ground lines are arranged horizontally in the wiring area 11 ( Fig. 9 The wiring area 21 is vertically arranged with a group of signal lines ( Fig. 9 The long vertical lines in the wiring area 21 in FIG.

[0072] Optionally, a signal transmission hole is provided at the intersection of the signal lines of the first wiring layer and the second wiring layer;

[0073] When the wiring direction of the first wiring layer is the same as the channel direction of the first channel sub-region, the signal transmission hole conducts a group of signal lines arranged in the first wiring region and a group of signal lines arranged in the fourth wiring region;

[0074] When the wiring direction of the first wiring layer is the same as the channel direction of the second channel sub-region, the signal transmission hole conducts a group of signal lines arranged in the second wiring region and a group of signal lines arranged in the third wiring region.

[0075] In an embodiment of the present application, for the combined channel area, a signal transmission hole is set by punching a hole at the intersection of the signal lines of two adjacent wiring layers. The signal transmission hole is used to connect the corresponding signal lines between the two adjacent wiring layers, so that the signal to be transmitted can be transmitted between the two adjacent wiring layers, thereby achieving the purpose of transmitting the signal to be transmitted to the target functional module on the chip through the combined channel area.

[0076] It should be noted that the chip includes functional modules distributed on both sides of the channel area. Figure 2 The functional modules include GPU module, DDR module, USB module, NPU module, PERI module, PCIE module, CPU module and MDM module. The signal lines arranged in the multi-layer wiring layer are used to connect the functional modules respectively. The signals can be transmitted between the functional modules through the signal lines arranged in the multi-layer wiring layer, thereby realizing the communication and control process within the chip.

[0077] In an optional embodiment, when the wiring direction of the first wiring layer is the same as the channel direction of the first channel sub-region, the first wiring area of ​​the first wiring layer and the fourth wiring area of ​​the second wiring layer are arranged with signal lines. At this time, the signal transmission hole connects a group of signal lines arranged in the first wiring area and a group of signal lines arranged in the fourth wiring area; the signal to be transmitted can be transmitted between the first wiring area and the fourth wiring area through the signal transmission hole.

[0078] In another optional embodiment, when the wiring direction of the first wiring layer is the same as the channel direction of the second channel sub-region, the second wiring area of ​​the first wiring layer and the third wiring area of ​​the second wiring layer are arranged with signal lines, and the signal transmission hole connects a group of signal lines arranged in the second wiring area and a group of signal lines arranged in the third wiring area; the signal to be transmitted can be transmitted between the second wiring area and the third wiring area through the signal transmission hole.

[0079] Optionally, a power supply point is set on the top layer of the multi-layer wiring layer, power lines are arranged on each wiring layer of the multi-layer wiring layer, and power holes are set at the intersections of the power lines of adjacent wiring layers.

[0080] In an embodiment of the present application, a power supply layout is performed for the multi-layer wiring layer according to a preset power supply plan. Specifically, a power supply point is set on the top layer of the multi-layer wiring layer, power lines are arranged on each layer of the multi-layer wiring layer, and power holes are set at the intersection of the power lines of adjacent wiring layers.

[0081] Optionally, the power supply point supplies power to the multiple wiring layers layer by layer through the power supply lines and power supply holes of each wiring layer.

[0082] Furthermore, the specific layout and wiring method of the above-mentioned wiring layer is only a partial implementation process of the chip layout and wiring. The chip is laid out and wired based on the specific layout and wiring method of the above-mentioned wiring layer until other work of the physical design of the chip is completed. The specific layout and wiring forms of other parts of the chip are not discussed in detail in this application.

[0083] It can be understood that the first wiring layer in the multi-layer wiring layer arranges a group of signal lines along the channel direction of the channel area, and the second wiring layer adjacent to the first wiring layer is set as a protective ground plane. The second wiring layer can be used to reduce the crosstalk of the signal in the channel without occupying winding resources and increasing the chip area, thereby reducing the manufacturing cost of the chip.

[0084] For example, Fig.10As shown in the figure, there are 5 signal lines out_22_5_NET, out_23_5_NET, out_24_5_NET, out_25_5_NET and out_26_5_NET in the channel area. For the existing layout and wiring method, the 4 signal lines on both sides have crosstalk to the middle signal line out_24_5_NET. Without any processing and through SPICE simulation, the crosstalk values ​​of each signal line to out_24_5_NET are as follows Fig.11 As shown; after adding a single-layer protective ground plane, the spice array is performed, and the crosstalk value of each signal line to out_24_5_NET is as follows Fig.12 shown; according to Fig.11 and Fig.12 It can be seen that the layout and wiring method of adding a protective ground plane proposed in this application can greatly reduce the signal crosstalk between signal lines in the chip.

[0085] Based on the above embodiments, the present application also provides an electronic device, Fig.13 This is a schematic diagram of the structure of an electronic device proposed in an embodiment of the present application. Fig.13 As shown, in an embodiment of the present application, the electronic device 2 includes the above-mentioned chip 1.

[0086] It should be noted that, in the embodiment of the present application, the electronic device 2 may be a terminal such as a smart phone or a tablet computer, in which the chip 1 is disposed. The specific electronic device 2 is not limited in the embodiment of the present application.

[0087] It should be noted that, in the embodiments of the present application, the electronic device 2 may include not only the chip 1, but also devices such as a display screen and a battery to provide corresponding functions, which is not limited in the embodiments of the present application.

[0088] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0089] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed in the utility application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A chip, characterized in that: The chip comprises: a plurality of wiring layers arranged in a channel region; each wiring layer in the plurality of wiring layers is wired in one direction; The first wiring layer in the multi-layer wiring layer arranges a group of signal lines along the channel direction of the channel region, the number of the signal lines is multiple, and a group of relay units is arranged on each signal line; the second wiring layer adjacent to the first wiring layer is set as a protective ground plane; Among them, a power supply point is set on the top layer of the multi-layer wiring layer, power lines are arranged on each wiring layer of the multi-layer wiring layer, and power holes are set at the intersection of the power lines of adjacent wiring layers; the power supply point supplies power to the multi-layer wiring layer layer by layer through the power lines and power holes of each wiring layer.

2. The chip according to claim 1, characterized in that: The wiring directions of the first wiring layer and the second wiring layer are perpendicular to each other.

3. The chip according to claim 1, characterized in that: The second wiring layer arranges a group of ground lines along a direction perpendicular to the channel direction.

4. The chip according to claim 1, characterized in that: The channel region includes a first channel sub-region and a second channel sub-region; a channel direction of the first channel sub-region is perpendicular to a channel direction of the second channel sub-region; In a case where the wiring direction of the first wiring layer is the same as the channel direction of the first channel sub-region, a first wiring region of the first wiring layer arranges a group of signal lines along the channel direction of the first channel sub-region, and a second wiring region of the first wiring layer arranges a group of ground lines along the channel direction of the first channel sub-region; the first wiring region corresponds to the first channel sub-region, and the second wiring region corresponds to the second channel sub-region; When the wiring direction of the first wiring layer is the same as the channel direction of the second channel sub-region, the second wiring region arranges a group of signal lines along the channel direction of the second channel sub-region, and the first wiring region arranges a group of ground lines along the channel direction of the second channel sub-region.

5. The chip according to claim 4, characterized in that: In the case where the wiring direction of the first wiring layer is the same as the channel direction of the first channel sub-region, a third wiring region of the second wiring layer arranges a group of ground lines along the channel direction of the first channel sub-region, and a fourth wiring region of the second wiring layer arranges a group of signal lines along the channel direction of the first channel sub-region; the third wiring region corresponds to the first channel sub-region, and the fourth wiring region corresponds to the second channel sub-region; When the wiring direction of the first wiring layer is the same as the channel direction of the second channel sub-region, the fourth wiring region arranges a group of ground lines along the channel direction of the second channel sub-region, and the third wiring region arranges a group of signal lines along the channel direction of the second channel sub-region.

6. The chip according to claim 5, characterized in that: A signal transmission hole is provided at the intersection of the signal lines of the first wiring layer and the second wiring layer; When the wiring direction of the first wiring layer is the same as the channel direction of the first channel sub-region, the signal transmission hole conducts a group of signal lines arranged in the first wiring region and a group of signal lines arranged in the fourth wiring region; When the wiring direction of the first wiring layer is the same as the channel direction of the second channel sub-region, the signal transmission hole conducts a group of signal lines arranged in the second wiring region and a group of signal lines arranged in the third wiring region.

7. The chip according to claim 3, characterized in that: The group of ground lines are arranged in parallel in the second wiring layer.

8. An electronic device, characterized in that: The electronic device comprises the chip as described in any one of claims 1-7.

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