A method for analyzing the failure of read-only memory using bit dislocation

Abstract

The present invention discloses a method for analyzing dislocation failure of a read-only memory, comprising: step 1, peeling off all back-end metal wire layers of the read-only memory and exposing the contact hole surface. Step 2, selecting a first cutting area outside a failure module and cutting to form a first groove extending in the column direction, the side of each row of polysilicon strips is exposed on the side of the first groove, and the first groove also exposes the surface of the semiconductor substrate. Step 3, forming a first metal layer on the inner surface of the first groove, the first metal layer makes each row of polysilicon strips and the semiconductor substrate contact and grounded. Step 4, performing voltage contrast imaging and forming a first voltage contrast image, in which the grounded polysilicon strips form a bright image, and the drain contact hole of a storage unit with a normal structure forms a dark image, and the storage unit whose image of the drain contact hole is a bright image is located as a dislocation failure position in the failure module. The present invention can quickly locate the dislocation failure position through the voltage contrast image.

Description

Technical Field

[0001] The present invention relates to a semiconductor integrated circuit manufacturing method, and in particular to a read-only memory (ROM) dislocation failure analysis (FA) method. Background Art

[0002] As for ROM products, there is one type of ROM product that transfers information from a mask to a cell array. This method has a low manufacturing cost and is often used to open electronic devices or store some basic programs of smart card products. This product defines data as "0" or "1" by defining the active area (AA) or controlling whether the active area is connected to a "row or column". The active area is composed of a semiconductor substrate surrounded by field oxygen such as a shallow trench field oxygen. The source area and the drain area are usually self-aligned and formed in the active area on both sides of the polysilicon gate. The channel area between the source area and the drain area and covered by the polysilicon gate is also formed in the active area. Defining the active area means defining the formation area of ​​the source area, drain area or channel area. The data stored when the formation area of ​​the source area, drain area and channel area is the active area is different from the data stored when the formation area of ​​the source area, drain area or channel area is the field oxygen. Controlling whether the active area is connected to a "row or column" means that the formation area of ​​the source area, drain area and channel area are all active areas, but the corresponding data is defined by controlling whether the source area or drain area is connected to a "row or column". Once the ROM is manufactured, the user cannot modify it, so some conventional failure location analysis is performed based on this characteristic of the ROM.

[0003] For ROM failure, electrical failure analysis (EFA) can be performed, for example, the chip can be powered on through a tester or some boards to make it spit out an actual internal code. Figure 1 101 shows the Mask definition data, and 102 shows the actual read data, both of which are binary data. It can be seen that the column data shown in the box 103 in the diagram 102 are all 0, so EFA can only get the failed column, but not the failed bit.

[0004] Physical failure analysis (PFA) requires precise positioning of the failure site, followed by TEM sample preparation, TEM imaging and analysis of the located failure site.

[0005] Existing methods use voltage contrast images (VC) to define the failure location. The imaging mechanism of voltage contrast images includes: when the electron beam or ion beam scans the sample surface, it will produce inelastic collisions with the surface and emit some low-energy secondary electrons such as <50eV. These secondary electrons can generally only leave the surface within 30nm. These secondary electrons are absorbed and imaged by applying a voltage of several hundred volts at the front end of the detector. The potential of the sample surface will affect the yield of secondary electrons. The higher the potential, the less secondary electrons are emitted, and the lower the potential, the more radiation. This voltage contrast image can be used to determine short circuits and open circuits of connecting wires including metal, polysilicon or contact holes.

[0006] In practical applications, low-voltage electron beams or high-voltage ion beams are generally used for voltage contrast experiments. The source and drain regions of the storage cells in the ROM are all of the same type, such as N-type implants. At this time, if the semiconductor substrate AA is damaged, we cannot confirm the location of the abnormality through the voltage contrast image of the contact hole. Figure 2 As shown, it is a voltage contrast image 104 formed in the existing read-only memory dislocation failure analysis method; the images of each contact hole in the voltage contrast image 104 are completely normal, and it is impossible to distinguish which images are abnormal. Figure 1 The coordinates of the column of the box 103 in the voltage contrast image 104 are used to find the corresponding failure column 103a. Figure 2 The voltage contrast image 104 shown can only be used to infer the failure column 103a through the physical address converted from the binary code. Since the substrate implants are all N-type, the specific failure position cannot be determined through VC, resulting in the inability to continue the analysis. Summary of the invention

[0007] The technical problem to be solved by the present invention is to provide a method for analyzing dislocation failure of a read-only memory, which can quickly locate the dislocation failure position through a voltage contrast image.

[0008] In order to solve the above technical problems, the present invention provides a method for analyzing the dislocation failure of a read-only memory, comprising:

[0009] Step 1: Strip all back-end metal line layers of the read-only memory and expose the top surface of the contact hole.

[0010] Step 2: Select a first cutting area outside the failure module and cut the first cutting area to form a first groove, wherein the first groove extends along the column direction of the storage cell array of the read-only memory; polysilicon gates of the storage cells in the same row are connected together to form a polysilicon strip, and the side surfaces of the polysilicon strips in each row are exposed at the side surfaces of the first groove, and the first groove also exposes the surface of the semiconductor substrate.

[0011] Step three: forming a first metal layer on the inner surface of the first groove, wherein the first metal layer enables each row of the polysilicon strips to contact and be grounded to the semiconductor substrate.

[0012] Step 4: Perform voltage contrast imaging on the read-only memory device and form a first voltage contrast image, in which the grounded polysilicon strip forms a bright image, and the drain contact hole of the memory cell with a normal structure forms a dark image, and the memory cell with the image of the drain contact hole as a bright image is located as a dislocation failure position in the failure module.

[0013] A further improvement is that, in step one, the stripping process of the back-end metal wire layer includes stripping using a focused ion beam (FIB).

[0014] A further improvement is that in step 2, the failure module is formed by preliminarily locating the dislocation failure position.

[0015] A further improvement is that the preliminary positioning includes performing EFA analysis on the read-only memory before step one.

[0016] A further improvement is that the EFA analysis includes reading data from the read-only memory, and when there is a column failure, there is a bit dislocation failure in the storage unit column corresponding to the column failure, and a module including the failure column is selected as the failure module.

[0017] A further improvement is that in step 2, the cutting process for forming the first groove adopts FIB etching.

[0018] A further improvement is that gallium ion beam is used for etching in the FIB etching.

[0019] A further improvement is that during the FIB etching process, gallium ions will remain on the cut surface, and the first metal layer in step three is directly composed of the gallium layer remaining on the inner surface of the first groove.

[0020] A further improvement is that in step 4, a drain contact hole of a bright image is searched on the failure column to thereby locate the dislocation failure position.

[0021] A further improvement is that after step 4 is completed, it also includes:

[0022] Performing TEM sample preparation, wherein the TEM sample includes the dislocation failure position;

[0023] The TEM samples were imaged and analyzed.

[0024] A further improvement is that, in the memory cell array of the read-only memory, the drain regions of the memory cells in the same column are connected to the bit lines through the drain contact holes.

[0025] A further improvement is that, in the memory cell array of the read-only memory, source regions of the memory cells in the same row are connected together in the semiconductor substrate to form a source region row.

[0026] A further improvement is that the source region row is connected to a source line.

[0027] A further improvement is that, on both sides of the module of the memory cell array, a gate contact hole is formed on the top of each of the polysilicon strips.

[0028] A further improvement is that both the source region and the drain region are N+ doped; at the dislocation failure position, the bottom of the drain contact hole contacts the semiconductor substrate.

[0029] The present invention forms a first groove by cutting on the outside of the failure module and forms a first metal layer on the inner surface of the first groove, and then performs voltage contrast imaging. In the first voltage contrast image formed at this time, the images of the drain contact holes of the storage unit with dislocation defects and the storage unit with normal structure can be distinguished, thereby locating the dislocation failure position. Therefore, the present invention can quickly locate the dislocation failure position through the voltage contrast image. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0031] Figure 1 It is a comparison diagram of defined data and read data when a bit error failure occurs in an existing read-only memory;

[0032] Figure 2 It is a voltage contrast image formed in the existing dislocation failure analysis method of read-only memory;

[0033] Figure 3 is a flow chart of a method for analyzing a dislocation failure of a read-only memory according to an embodiment of the present invention;

[0034] Figure 4A The layout of the polysilicon body and the contact hole obtained in the stripping process of step 1 of the method for analyzing dislocation failure of a read-only memory according to an embodiment of the present invention;

[0035] Figure 4B The active area layout is obtained during the stripping process of step 1 of the method for analyzing dislocation failure of a read-only memory according to an embodiment of the present invention;

[0036] Figure 5AThis is a schematic diagram of the device structure before cutting in step 2 of the method for analyzing dislocation failure of a read-only memory according to an embodiment of the present invention;

[0037] Figure 5B It is a schematic diagram of the device structure after cutting in step 2 of the method for analyzing dislocation failure of a read-only memory according to an embodiment of the present invention;

[0038] Figure 5C yes Figure 5B The corresponding top view;

[0039] Fig. 6A It is a voltage contrast image formed by the existing dislocation failure analysis method of read-only memory for comparison;

[0040] Figure 6B is a first voltage contrast image formed in step 4 of the method for analyzing dislocation failure of a read-only memory according to an embodiment of the present invention;

[0041] Figure 7 is a TEM photograph formed at a dislocation failure position by a dislocation failure analysis method for a read-only memory according to an embodiment of the present invention;

[0042] Figure 8 It is a schematic diagram of a dislocation failure circuit in a method for analyzing dislocation failure of a read-only memory according to an embodiment of the present invention. DETAILED DESCRIPTION

[0043] like Figure 3 FIG. 1 is a flow chart of a method for analyzing a bit dislocation failure of a read-only memory according to an embodiment of the present invention. The method for analyzing a bit dislocation failure of a read-only memory according to an embodiment of the present invention comprises:

[0044] Step 1: Strip all back-end metal line layers of the read-only memory and expose the top surface of the contact hole.

[0045] In the embodiment of the present invention, the stripping process of the back-end metal wire layer includes stripping using FIB.

[0046] like Figure 4A , is a layout of the polysilicon body 201 and the contact hole obtained during the stripping process of step 1 of the method for analyzing dislocation failure of a read-only memory according to an embodiment of the present invention; it can be seen that the layout shows:

[0047] The polysilicon body 201 is formed by connecting polysilicon gates in the same row, the source region is located in the area corresponding to the bracket 202, and the drain region is located in the area corresponding to the bracket 203. Regions 202 and 203 are respectively located on both sides of each polysilicon body 201. Figure 4A The mid-polysilicon body 201 is also represented by poly.

[0048] The contact holes include a drain contact hole 204a formed at the top of the drain region; a gate contact hole 204b formed at the end of one side of the polysilicon body 201; and a source contact hole 204c formed at the end of one side of the source region row. The dotted box 205 represents the drain contact holes 204a located on the same column, and the drain contact holes 204a in the same column will be connected to the same bit line (BL). The source regions of the memory cells in the same row are connected together in the semiconductor substrate to form a source region row. The source region row is represented by SL. The source region row is connected to the source line through the source contact hole 204c.

[0049] like Figure 4B , is a layout of the active region 206 obtained during the stripping process of step 1 of the method for analyzing dislocation failure of a read-only memory according to an embodiment of the present invention; Figure 4B The image of the polysilicon strip 201 is not specifically shown, the polysilicon strip 201 is represented by a dotted frame, and the polysilicon gate constituting the polysilicon strip 201 is also represented by poly gate. Figure 4B It is also shown that regions 202 and 203 are located on both sides of the polysilicon strip 201. The bit line on top of the drain region is denoted by BL. Figure 4B In the example, the active region 206 has a patterned structure, and programming is achieved by patterning the active region 206. The active region 206 needs to be formed in the formation regions of the source region, the channel region, and the drain region of a complete memory cell, so that the memory cell will store one type of data; if field oxygen is used in more than one formation region of the source region, the channel region, or the drain region, the memory cell cannot be turned on, and thus another type of data is stored.

[0050] Please also refer to Figure 5C As shown, in the memory cell array of the read-only memory, the drain regions of the memory cells in the same column are connected to the same bit line BL through the drain contact hole 204a.

[0051] In the memory cell array of the read-only memory, the source regions of the memory cells in the same row are connected together in the semiconductor substrate to form a source region row. The source region row is represented by SL. The source region row is connected to the source line through the source contact hole 204c.

[0052] The gate contact holes 204b are formed at the tops of the polysilicon strips 201 on both sides of the module of the memory cell array; the source contact holes 204c are formed at the tops of the source region rows on both sides of the module of the memory cell array.

[0053] Step 2: Select a first cutting area outside the failure module and cut the first cutting area to form a first groove 402 .

[0054] The first groove 402 extends along the column direction of the memory cell array of the read-only memory; the polysilicon gates of the memory cells in the same row are connected together to form a polysilicon strip 201, and the side surfaces of the polysilicon strips 201 in each row are exposed at the side surfaces of the first groove 402, and the first groove 402 also exposes the surface of the semiconductor substrate.

[0055] In the embodiment of the present invention, the failure module is formed by preliminarily locating the dislocation failure position.

[0056] The preliminary positioning includes performing EFA analysis on the read-only memory before step 1. For EFA analysis, please refer to Figure 1 As shown, the EFA analysis includes reading data from the read-only memory. When there is a column failure, the storage unit column corresponding to the column failure has a bit dislocation failure, and the module including the failure column is selected as the failure module.

[0057] In the embodiment of the present invention, the cutting process for forming the first groove 402 adopts FIB etching.

[0058] like Figure 5A As shown, it is a schematic diagram of the device structure before cutting in step 2; in order to facilitate a more intuitive understanding, Figure 5A A top view and a cross-sectional view are given at the same time, wherein the top view 301 is on the left side of the dotted line AA, and the cross-sectional view 302 is on the right side of the dotted line AA. The top view 301 includes a structural schematic diagram of a portion of the storage units on the polysilicon strip 201; the cross-sectional view 302 is a structural schematic diagram along the cross section of the polysilicon strip 201 in Figure 301.

[0059] The top view 301 shows a plurality of drain regions 203a and drain contact holes 204a formed on the top of the drain regions 203a. The top view 301 also includes a storage unit having a dislocation failure defect 303. The drain contact hole of the storage unit having the dislocation failure defect 303 is individually marked with a mark 204a1.

[0060] In the cross-sectional view 302 , a semiconductor substrate 401 is shown, and the polysilicon strip 201 is formed on the surface of the semiconductor substrate 401 ; Figure 5A In the embodiment, the surface of the semiconductor substrate 401 is further patterned etched, and the protruding portion of the semiconductor substrate 401 after the patterned etching is separately marked with a mark 401a.

[0061] The source region and the drain region are both N+ doped; at the dislocation failure position, the bottom of the drain contact hole 204a1 contacts the semiconductor substrate 401 .

[0062] exist Figure 5AWhen voltage contrast imaging is performed under the condition of , the image of the polysilicon strip 201 is a dark image, and the images of the drain contact holes 204a are all bright images. At this time, the voltage contrast image 501 formed by voltage contrast imaging of the read-only memory is as shown in FIG. Fig. 6A As shown, Fig. 6A and Figure 2 Similarly, the positioning of the drain contact hole indicated by the mark 204a1 cannot be achieved.

[0063] like Figure 5B , which is a schematic diagram of the device structure after cutting in step 2, and Figure 5A compared to, Figure 5B The first groove 402 is formed therein.

[0064] like Figure 5C As shown, Figure 5B From the corresponding top view, it can be seen that the gate contact hole 204b and the source contact hole 204c are respectively provided at two ends of the failure module, and the first groove 402 is located outside the failure module, so the first groove 402 will not damage the failure site.

[0065] Step three: forming a first metal layer 403 on the inner surface of the first groove 402 , wherein the first metal layer 403 enables each row of the polysilicon strips 201 to contact and be grounded to the semiconductor substrate.

[0066] In the embodiment of the present invention, the FIB etching in step 2 is performed by etching with a gallium ion beam.

[0067] During the FIB etching process, gallium ions may remain on the cut surface, and the first metal layer 403 in step three is directly composed of the gallium layer remaining on the inner surface of the first groove 402 .

[0068] Step 4: Perform voltage contrast imaging on the read-only memory device and form a first voltage contrast image, in which the grounded polysilicon strip 201 forms a bright image, and the drain contact hole of the memory cell with a normal structure forms a dark image, and the memory cell with a bright image of the drain contact hole is located as a dislocation failure position in the failure module.

[0069] like Figure 5B As shown, Figure 5B When the structure shown in the figure is subjected to voltage contrast imaging, the polysilicon strip 201 is grounded through the first metal layer 403, and the image of the polysilicon strip 201 is a bright image; and Figure 5A The image of the polysilicon strip 201 in the FIB is dark, which is just the opposite. In the embodiment of the present invention, the FIB scanning is realized by voltage contrast imaging, and the grounding in the FIB will appear as a bright image.

[0070] Likewise, the drain contact hole 204a1 with the dislocation failure position will also be grounded through the semiconductor substrate 401, and finally present a bright image.

[0071] The drain contact holes 204a of other memory cells with normal functions are not grounded, so they all appear dark. Therefore, the embodiment of the present invention can distinguish the drain contact hole 204a1 from the normal drain contact hole 204a, so as to locate the actual failure position of the dislocation.

[0072] like Figure 6B As shown, it is a first voltage contrast image 502 formed in step 4 of the method for analyzing dislocation failure of a read-only memory according to an embodiment of the present invention; Figure 6B is Figure 5B A first voltage contrast image 502 corresponding to the entire read-only memory formed on the basis of; Figure 6B The image 503 in FIG. 5 is an enlarged image in the white box of the first voltage contrast image 502. From the image 503, it can be seen that the bright image of the polysilicon strip 201, the dark image of the drain contact hole 204a at the normal position, and the bright image of the drain contact hole 204a1 at the dislocation failure position.

[0073] In the embodiment of the present invention, the drain contact hole 204a1 of the bright image is found on the failure column 504 to locate the dislocation failure position. Figure 1 corresponds to column 103 in .

[0074] After step 4 is completed, it also includes:

[0075] Performing TEM sample preparation, wherein the TEM sample includes the dislocation failure position;

[0076] The TEM samples were imaged and analyzed.

[0077] like Figure 7 As shown, it is a TEM photo 601 formed at the dislocation failure position of the read-only memory dislocation failure analysis method according to an embodiment of the present invention, Figure 7 The enlarged photo 602 in the box of the TEM photo 601 is also included. The photos 601 and 602 show the polysilicon gate corresponding to the polysilicon strip 201, the semiconductor substrate 401 at the bottom of the polysilicon gate, and the drain contact hole 204a1 at the top of the drain region. The area corresponding to the arrow has a dislocation failure defect 303.

[0078] like Figure 8, which is a schematic diagram of a dislocation failure circuit in a dislocation failure analysis method for a read-only memory according to an embodiment of the present invention. The memory cells 701 are all NMOS, which include a source region S, a drain region D and a gate G. The drain region D is connected to the bit line BL through a drain contact hole 204a, and the source region S is connected together through a source region row SL and grounded through a source contact hole 204c. At the dislocation failure position, the dislocation failure defect 303 causes the drain contact hole 204a1 to contact the semiconductor substrate 401, so that it can be located through a voltage contrast image.

[0079] The embodiment of the present invention forms a first groove 402 by cutting on the outside of the failure module and forms a first metal layer 403 on the inner surface of the first groove 402, and then performs voltage contrast imaging. In the first voltage contrast image formed at this time, the images of the drain contact holes of the storage unit with dislocation defects and the storage unit with normal structure can be distinguished, thereby locating the dislocation failure position. Therefore, the embodiment of the present invention can quickly locate the dislocation failure position through the voltage contrast image.

[0080] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A method for analyzing dislocation failure of a read-only memory, characterized in that: include: Step 1: stripping off all back-end metal line layers of the read-only memory and exposing the top surface of the contact hole; Step 2: selecting a first cutting area outside the failure module and cutting the first cutting area to form a first groove, wherein the first groove extends along the column direction of the memory cell array of the read-only memory; connecting the polysilicon gates of the memory cells in the same row together to form a polysilicon strip, and the side surfaces of the polysilicon strips in each row are exposed at the side surfaces of the first groove, and the first groove also exposes the surface of the semiconductor substrate; Step 3: forming a first metal layer on the inner surface of the first groove, wherein the first metal layer enables each row of the polysilicon strips to contact and be grounded to the semiconductor substrate; Step 4: Perform voltage contrast imaging on the read-only memory device and form a first voltage contrast image, in which the grounded polysilicon strip forms a bright image, and the drain contact hole of the memory cell with a normal structure forms a dark image, and the memory cell with the image of the drain contact hole as a bright image is located as a dislocation failure position in the failure module.

2. The method for analyzing dislocation failure of a read-only memory according to claim 1, wherein: In step 1, the stripping process of the back-end metal wire layer includes stripping using FIB.

3. The method for analyzing dislocation failure of a read-only memory according to claim 2, wherein: In step 2, the failure module is formed by preliminarily locating the dislocation failure position.

4. The method for analyzing dislocation failure of a read-only memory according to claim 3, wherein: The preliminary positioning includes performing EFA analysis on the read-only memory before step one.

5. The method for analyzing dislocation failure of a read-only memory according to claim 4, wherein: The EFA analysis includes reading data from the read-only memory. When there is a column failure, the storage unit column corresponding to the column failure has a bit dislocation failure, and a module including the failure column is selected as the failure module.

6. The method for analyzing dislocation failure of a read-only memory according to claim 1, wherein: In step 2, the cutting process for forming the first groove adopts FIB etching.

7. The method for analyzing dislocation failure of a read-only memory according to claim 6, wherein: Gallium ion beam is used for etching in the FIB etching.

8. The method for analyzing dislocation failure of a read-only memory according to claim 7, wherein: During the FIB etching process, gallium ions will remain on the cut surface, and the first metal layer in step three is directly composed of the gallium layer remaining on the inner surface of the first groove.

9. The method for analyzing dislocation failure of a read-only memory according to claim 5, wherein: In step 4, the drain contact hole of the bright image is searched on the failure column to locate the dislocation failure position.

10. The method for analyzing dislocation failure of a read-only memory according to claim 1, wherein: After step 4 is completed, it also includes: Performing TEM sample preparation, wherein the TEM sample includes the dislocation failure position; The TEM samples were imaged and analyzed.

11. The method for analyzing dislocation failure of a read-only memory according to claim 5, wherein: In the memory cell array of the read-only memory, the drain regions of the memory cells in the same column are connected to the bit lines through the drain contact holes.

12. The method for analyzing dislocation failure of a read-only memory according to claim 11, wherein: In the memory cell array of the read-only memory, source regions of the memory cells in the same row are connected together in the semiconductor substrate to form a source region row.

13. The method for analyzing dislocation failure of a read-only memory according to claim 12, wherein: The source region row is connected to the source line.

14. The method for analyzing dislocation failure of a read-only memory according to claim 12, wherein: On both sides of the module of the memory cell array, a gate contact hole is formed on the top of each of the polysilicon strips.

15. The method for analyzing dislocation failure of a read-only memory according to claim 12, wherein: The source region and the drain region are both N+ doped; at the dislocation failure position, the bottom of the drain contact hole contacts the semiconductor substrate.

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