Display Panel

Abstract

The embodiment of the present application provides a display panel, including: a plurality of multiplexer groups, each of which includes a plurality of multiplexer units, the plurality of multiplexer units in the multiplexer group are symmetrically arranged in two columns, and each multiplexer unit includes a first signal terminal, a second signal terminal, and a third signal terminal; a plurality of first input lines, each of which is connected to all first signal terminals in a multiplexer group; a plurality of second input lines, each of which is connected to all second signal terminals in a multiplexer group; a plurality of third input lines, each of which is connected to a third signal terminal of a column of multiplexer units in a multiplexer group, and two third input lines are provided between two columns of multiplexer units in the multiplexer group. The same signal terminal shares the input line, and there is no need to set an input line for each signal terminal, which reduces the number of input lines and can reduce the distance between two columns of multiplexer units, thereby providing space for the arrangement of thin film transistors.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and in particular, relates to a display panel. Background Art

[0002] With the development of display industry technology, touch technology is being used more and more widely in display panels. Among them, Touch and Display Driver Integration (TDDI) chips are also being developed continuously. TDDI chips are touch chips and display chips in one, thus improving the integration of display panel chips.

[0003] Among them, in the self-capacitive display panel with TDDI chip, each multiplexer (MUX) circuit used for touch contains three signals: load-free driving signal (LFD), ground signal (GND) and touch signal (Touch Panel, TP). The GND signal and LFD signal are used to test the short circuit and opening of the touch path respectively, and the TP board is used to input the TP signal to each touch sensor.

[0004] Each multiplexer has at least 1 driving 6, that is, one touch signal drives six touch electrodes. Therefore, the number of signals transmitted by multiple multiplexers is large, and the corresponding required signal lines occupy a large space. However, the existing circuit structure arrangement of the multiplexer is unreasonable, resulting in a large space occupied by the multiplexer, which affects the arrangement and performance of the thin film transistor (TFT) device. Summary of the invention

[0005] The embodiment of the present application provides a display panel, which reasonably arranges the circuit structure of the multiplexer to reduce the space occupied by the multiplexer, thereby reducing the impact on the arrangement and performance of the thin film transistors.

[0006] An embodiment of the present application provides a display panel, including:

[0007] A plurality of multiplexer groups, each of the multiplexer groups comprises a plurality of multiplexer units, the plurality of multiplexer units in the multiplexer groups are symmetrically arranged in two columns, and each of the multiplexer units in the multiplexer groups comprises a first signal terminal, a second signal terminal and a third signal terminal;

[0008] A plurality of first input lines, each of which is connected to the first signal terminals of all the multiplexer units in one multiplexer group, and each of which is arranged between two columns of multiplexer units in the multiplexer group;

[0009] a plurality of second input lines, each of which is connected to the second signal terminals of all the multiplexer units in one multiplexer group, and each of which is arranged between two columns of multiplexer units in the multiplexer group;

[0010] A plurality of third input lines, each of which is connected to a third signal terminal of a column of multiplexer units in one of the multiplexer groups, and two third input lines are provided between two columns of multiplexer units in the multiplexer group.

[0011] Optionally, the first signal ends, the second signal ends and the third signal ends of the two multiplexer units in each row of multiplexer units in the multiplexer group are arranged in the same order.

[0012] Optionally, each multiplexer unit in the multiplexer group includes:

[0013] three thin film transistors, the three thin film transistors correspond to the first signal terminal, the second signal terminal and the third signal terminal one by one, and the region where the three thin film transistors are located has a first width;

[0014] There is a second width between two columns of multiplexer units in the multiplexer group, and the second width is smaller than the first width.

[0015] Optionally, the first signal end, the second signal end and the third signal end of every two adjacent rows of multiplexer units in the multiplexer group are symmetrically arranged.

[0016] Optionally, two adjacent thin film transistors of each two adjacent rows of multiplexer units in the multiplexer group share a source;

[0017] The source and drain of two adjacent thin film transistors in each multiplexer unit are symmetrically arranged;

[0018] The display panel further includes:

[0019] A plurality of gate lines, each of which is connected to a signal end of a row of multiplexer units in each multiplexer group, and each of which is arranged between a source and a drain of a thin film transistor.

[0020] Optionally, a channel width of each of the thin film transistors is greater than 30 microns.

[0021] Optionally, the display panel further includes:

[0022] A plurality of touch electrodes;

[0023] A plurality of touch control lines, one end of each of the touch control lines is connected to a multiplexer unit in the multiplexer group, the other end of each of the touch control lines is connected to the touch control electrode, and each of the touch control lines is arranged between two adjacent multiplexer groups.

[0024] Optionally, the display panel further includes:

[0025] A first test board connected to the plurality of first input lines;

[0026] A second test board connected to the plurality of second input lines;

[0027] A plurality of third test boards are respectively connected to the plurality of third input lines in a one-to-one correspondence.

[0028] Optionally, the first test board, the second test board and the plurality of third test boards are arranged in a row and multiple columns, and the plurality of third test boards are located between the first test board and the second test board.

[0029] Optionally, the display panel includes a display area and a non-display area surrounding the display area, and the display panel further includes:

[0030] The chip is arranged in a non-display area, and the orthographic projection of the chip in the non-display area covers the orthographic projections of multiple multiplexer groups in the non-display area and the orthographic projections of the first test board, the second test board and multiple third test boards in the non-display area.

[0031] Optionally, the display panel further includes:

[0032] A plurality of enable signal plates are connected to the plurality of gate lines in a one-to-one correspondence, each of the enable signal plates is used to provide an enable signal for a thin film transistor, and the orthographic projections of the plurality of enable signal plates in the non-display area do not overlap with the orthographic projections of the chip in the non-display area.

[0033] Optionally, a column of multiplexer units in each of the multiplexer groups includes six multiplexer units.

[0034] Optionally, each of the multiplexer units includes a plurality of line-changing arches, each of the line-changing arches is used to connect metals of different layers, and the plurality of line-changing arches are arranged in M ​​rows and N columns, where M and N are both positive integers.

[0035] In the display panel of the embodiment of the present application, by arranging the multiple multiplexer units in the multiplexer group symmetrically in two columns, all the first signal terminals and all the second signal terminals in the multiple multiplexer units in one multiplexer group only need one first input line and one second input line respectively, all the third signal terminals in one column of multiplexer units only need one third input line, the same signal terminals share the input line, there is no need to set an input line for each signal terminal, the number of input lines is reduced, and the distance between the two columns of multiplexer units can be reduced, thereby providing space for the arrangement of thin film transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A schematic diagram of the first structure of a display panel provided in an embodiment of the present application.

[0037] Figure 2 for Figure 1 A schematic diagram of a first arrangement structure of touch electrodes in a display panel is shown.

[0038] Figure 3 for Figure 1 A schematic diagram of a second arrangement structure of touch electrodes in a display panel is shown.

[0039] Figure 4 A second structural schematic diagram of a display panel provided in an embodiment of the present application.

[0040] Figure 5 An equivalent circuit diagram of multiple multiplexer groups provided in an embodiment of the present application.

[0041] Figure 6 for Figure 1 A first partial structural schematic diagram of a display panel is shown.

[0042] Figure 7 for Figure 1 A second partial structural schematic diagram of a display panel is shown.

[0043] Figure 8 for Figure 1 A third partial structural schematic diagram of a display panel is shown.

[0044] Fig. 9 for Figure 1 A fourth partial structural schematic diagram of a display panel is shown.

[0045] Fig.10 for Figure 1 A fifth partial structural schematic diagram of a display panel is shown.

[0046] Fig.11 for Figure 1 A sixth partial structural schematic diagram of a display panel is shown.

[0047] Fig.12 for Figure 1 FIG. 7 is a schematic diagram of a seventh partial structure of a display panel shown in FIG. DETAILED DESCRIPTION

[0048] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0049] In order to solve the problem that the circuit structure of the existing multiplexer is not arranged reasonably, resulting in the multiplexer occupying a large space and affecting the arrangement and performance of the thin film transistor device, an embodiment of the present application provides a display panel, which will be described below with reference to the accompanying drawings.

[0050] See also Figure 1 , Figure 1 A schematic diagram of the first structure of a display panel provided in an embodiment of the present application. An embodiment of the present application provides a display panel 1, which may be an organic light-emitting diode (OLED) type display panel or a liquid crystal display (LCD) type display panel. The display principles of the two are different. The LCD display relies on a backlight panel to emit light, and then the light is polarized by the liquid crystal to display different colors. OLED does not require a backlight panel because the pixels of OLED emit light themselves. The display panel 1 can be applied to electronic devices, for example, the electronic device may be a television, a computer, a mobile phone, a car display device, an augmented reality (AR) device, a virtual reality (VR) device, and other devices with display and touch functions.

[0051] Exemplarily, the display panel 1 is divided into a display area and a non-display area, and the non-display area is arranged around the display area. The display area can be used to display images, and the display area is also used for touch interaction with users. The non-display area is used to arrange wires, flexible circuit boards, chips, etc. Figure 1 Also see Figure 2 and Figure 3 , Figure 2 for Figure 1 The first arrangement structure diagram of the touch electrodes in the display panel is shown in FIG. Figure 3 for Figure 1The second arrangement structure diagram of the touch electrodes in the display panel is shown. The display panel 1 may include a touch layer 10 and a chip 20. The touch layer 10 may include a plurality of touch electrodes 11. The touch electrodes 11 may also be called touch sensors. The chip 20 may be connected to all the touch electrodes 11 to send control signals or receive touch signals from the user. Figures 1 to 3 Also see Figure 4 , Figure 4 A second structural schematic diagram of a display panel provided in an embodiment of the present application. The display panel 1 may further include a pixel layer 30, which may be stacked with the touch layer 10, and the pixel layer 30 may include a plurality of pixel electrodes 31, and the pixel electrodes 31 and the touch electrodes 11 do not correspond one to one. For example, one touch electrode 11 may correspond to 60 pixel electrodes 31, that is, the projections of the 60 pixel electrodes 31 on the touch electrode 11 are within the touch electrode 11. The pixel electrode 31 and the touch electrode 11 may both be located in the display area. The chip 20 is arranged in the non-display area. The chip 20 may be a touch driver chip connected only to the touch electrode 11, or the chip 20 may be a touch driver and display driver integrated chip connected to the touch electrode 11 and the pixel electrode 31, that is, a TDDI chip. The embodiment of the present application is described by taking the chip 20 as a TDDI chip as an example.

[0052] In the prior art, each multiplexer circuit used for touch control in a self-contained (SDOT) TDDI product includes three signals: an anti-load drive signal, a ground signal, and a touch signal. The ground signal and the anti-load drive signal are used to test the short circuit (Short) and open (Open) of the touch path, respectively, and the touch panel or signal input panel is used to input a touch signal to each touch electrode. Each multiplexer has at least 1 drive 6, that is, one touch signal drives six touch electrodes, and each multiplexer circuit includes three signals. Therefore, the number of signals transmitted by multiple multiplexers is large, and the corresponding required signal lines occupy a large space. However, the circuit structure arrangement of the multiplexer in the prior art is unreasonable, resulting in a large space occupied by the multiplexer, which affects the arrangement and performance of the thin film transistor device.

[0053] In order to solve the above problems, the embodiment of the present application designs the arrangement of the multiplexer, and the component structure and arrangement of the multiplexer will be described below.

[0054] For example, please combine Figures 1 to 4 Also see Figures 5 to 7 , Figure 5 An equivalent circuit diagram of multiple multiplexer groups provided in an embodiment of the present application, Figure 6 for Figure 1 The first partial structural diagram of the display panel shown in FIG. Figure 7 for Figure 1A second partial structural schematic diagram of a display panel is shown.

[0055] In the embodiment of the present application, a column of multiplexer units 210 in each multiplexer group 21 includes 6 multiplexer units 210 as an example, each multiplexer unit 210 includes 3 signal terminals, and each signal terminal is corresponding to a thin film transistor 214. Therefore, a column of multiplexer units 210 includes 18 thin film transistors 214, and each multiplexer group 21 includes 36 thin film transistors 214. One touch signal can drive 6 touch electrodes.

[0056] The arrangement relationship of the multiplexer groups 21 will be described below. The display panel 1 may include multiple multiplexer groups 21, multiple first input lines 22a, multiple second input lines 22b, and multiple third input lines 22c. Each multiplexer group 21 includes multiple multiplexer units 210, and the multiple multiplexer units 210 in the multiplexer group 21 are arranged symmetrically in two columns. Each multiplexer unit 210 in the multiplexer group 21 includes a first signal terminal 211, a second signal terminal 212, and a third signal terminal 213. Each first input line 22a is connected to the first signal terminal 211 of all the multiplexer units 210 in one multiplexer group 21, and each first input line 22a is arranged between two columns of multiplexer units 210 in the multiplexer group 21. Each second input line 22b is connected to the second signal terminals 212 of all the multiplexer units 210 in one multiplexer group 21, and each second input line 22b is arranged between two columns of multiplexer units 210 in the multiplexer group 21. Each third input line 22c is connected to the third signal terminal 213 of one column of multiplexer units 210 in one multiplexer group 21, and there are two third input lines 22c between two columns of multiplexer units 210 in the multiplexer group 21.

[0057] By arranging the multiple multiplexer units 210 in the multiplexer group 21 symmetrically in two columns, all the first signal terminals 211 and all the second signal terminals 212 in the multiple multiplexer units 210 in one multiplexer group 21 only need one first input line 22a and one second input line 22b respectively, and all the third signal terminals 213 in one column of multiplexer units 210 only need one third input line 22c. The same signal terminals share the input line, and there is no need to set an input line for each signal terminal, thereby reducing the number of input lines, and further reducing the distance between the two columns of multiplexer units 210, thereby providing space for the arrangement of thin film transistors.

[0058] It should be noted that the space occupied by the multiplexer groups 21 in the display panel 1 is reduced in the horizontal direction and the vertical direction. The horizontal direction is the direction from left to right or from right to left in the figure, and the vertical direction is the direction from top to bottom or from bottom to top in the figure. The following will be explained from the two directions respectively.

[0059] Firstly, the space occupied in the horizontal direction is reduced because the multiple multiplexer units 210 in each multiplexer group 21 are symmetrically arranged in two columns, so that the same signal end in different multiplexer units 210 in the multiplexer group 21 can be input with only one input line or only two input lines, and there is no need to set an input line for each signal end of different multiplexer units 210, thereby reducing the number of input lines, thereby reducing the distance between the two columns of multiplexer units 210 in the multiplexer group 21, thereby reducing the space occupied by the multiple multiplexer groups 21 in the horizontal direction.

[0060] It should be noted that each multiplexer unit 210 in the multiplexer group 21 includes three thin film transistors 214, and the three thin film transistors 214 correspond to the first signal terminal 211, the second signal terminal 212 and the third signal terminal 213. The area where the three thin film transistors 214 are located has a first width W1. There is a second width W2 between two columns of multiplexer units 210 in the multiplexer group 21, and the second width W2 is smaller than the first width W1. It can be understood that by reducing the number of input lines between two columns of multiplexer units 210 in the multiplexer group 21, the space occupied by the input lines can be reduced, thereby reducing the second width W2 between two columns of multiplexer units 210 in the multiplexer group 21, so that the first width W1 of the area where the three thin film transistors 214 are located can be unaffected or even increased. The width of the thin film transistor 214 is not affected, that is, its channel width can be guaranteed, so that the driving capability of the thin film transistor 214 can be ensured.

[0061] Exemplarily, the arrangement order of the first signal terminals 211, the second signal terminals 212, and the third signal terminals 213 of the two multiplexer units 210 in each row of the multiplexer units 210 in the multiplexer group 21 is the same. That is to say, the two columns of multiplexer units 210 in the multiplexer group 21 are symmetrically arranged, which is reflected in the arrangement mode on each multiplexer unit 210, that is, the arrangement order of the first signal terminals 211, the second signal terminals 212, and the third signal terminals 213 of the two multiplexer units 210 in each row of the multiplexer units 210 in the multiplexer group 21 is the same. By symmetrically arranging the two columns of multiplexer units 210 in the multiplexer group 21, the number of signal terminal input lines and the occupied space between the two columns of multiplexer units 210 in the multiplexer group 21 can be reduced, and thus the space occupied by multiple multiplexer groups 21 in the horizontal direction can be reduced.

[0062] For example, please combine Figures 1 to 7 Also see Figure 8 and Fig. 9 , Figure 8 for Figure 1 The third partial structural diagram of the display panel shown in FIG. Fig. 9 for Figure 1A fourth partial structural diagram of the display panel shown. Taking the first signal terminal 211, the second signal terminal 212 and the third signal terminal 213 as the ground signal terminal GND, the anti-load drive signal terminal LFD and the touch signal terminal TP respectively, a column of multiplexer units 210 in each multiplexer group 21 may include 6 multiplexer units 210. There are four input lines between two columns of multiplexer units 210 in the multiplexer group 21, that is, a first input line 22a, a second input line 22b and two third input lines 22c. The three thin film transistors 214 of each multiplexer unit 210 have a first width W1. If the two columns of multiplexer units 210 in the multiplexer group 21 are not arranged symmetrically, a total of 36 input lines are required for the two columns of multiplexer units 210 in the corresponding multiplexer group 21. The space occupied by the 36 input lines is relatively large, which will make the second width W2 between the two columns of multiplexer units 210 in the multiplexer group 21 much larger than the first width W1, so that the lateral space occupied by the multiplexer groups 21 becomes larger. In order to reduce this occupied space, it is necessary to compress the first width W1, which will affect the width of the channel of the thin film transistor 214, so that the driving ability of the thin film transistor 214 decreases. Therefore, the second width W2 between the two columns of multiplexer units 210 in the multiplexer group 21 is smaller than the first width W1 of the thin film transistor 214, so that the occupied space of the thin film transistor 214 is sufficient, thereby making the performance of the thin film transistor 214 not limited by space. For example, in the above setting of multiple multiplexer groups 21, the channel width of the thin film transistor 214 can be greater than 30 microns, while the W / L of the conventional thin film transistor is 30 / 3.5 microns, so that the occupied space of the thin film transistor 214 is not affected, and even the space that the thin film transistor 214 can occupy is expanded, thereby ensuring the performance of the thin film transistor 214.

[0063] It should be noted that the connection between each input line and the signal terminal can be realized by a connecting line. For example, each input line can be a straight line, and the connecting line can be perpendicular to the input line to connect different signal terminals. Multiple connecting lines can be arranged in parallel.

[0064] Secondly, reducing the occupied space in the vertical direction can also be achieved through symmetrical arrangement.

[0065] Exemplarily, the first signal terminal 211, the second signal terminal 212 and the third signal terminal 213 of each two adjacent rows of multiplexer units 210 in the multiplexer group 21 are symmetrically arranged. For example, the signal terminal arrangement of two adjacent rows of multiplexer units 210 in the multiplexer group 21 can be: the first signal terminal 211, the second signal terminal 212, the third signal terminal 213, the third signal terminal 213, the second signal terminal 212 and the first signal terminal 211.

[0066] Taking the ground signal terminal GND, the anti-load drive signal terminal LFD and the touch signal terminal TP as examples, the ground signal terminal GND, the anti-load drive signal terminal LFD and the touch signal terminal TP of two adjacent rows of multiplexer units 210 in the multiplexer group 21 are symmetrical, and the ground signal terminal GND of two adjacent rows of multiplexer units 210 in the multiplexer group 21 is adjacent, the anti-load drive signal terminal LFD is adjacent or the touch signal terminal TP is adjacent. The adjacent and symmetrical arrangement of the same signal terminals can reduce the space occupied by the multiplexer group 21 in the vertical direction. Since the adjacent and symmetrical arrangement of different signal terminals is prone to interference between signals, the embodiment of the present application arranges the same signal terminals adjacently and symmetrically, which can reduce the space occupied by the multiplexer group 21 in the vertical direction and prevent interference between different signal terminals.

[0067] It can be understood that there are three arrangements of signal terminals above: in the first case, the ground signal terminals GND of two adjacent rows of multiplexer units 210 in the multiplexer group 21 are adjacent and symmetrical, and the anti-load drive signal terminals LFD and the touch signal terminals TP of two adjacent rows of multiplexer units 210 in the multiplexer group 21 are symmetrically arranged. The proximity relationship between the anti-load drive signal terminal LFD and the touch signal terminal TP and the ground signal terminal GND can be set as needed. For example, compared with the distance between the touch signal terminal TP and the ground signal terminal GND, the anti-load drive signal terminal LFD can be made closer to the ground signal terminal GND. Of course, the touch signal terminal TP can also be made closer to the ground signal terminal GND. In the second case, the anti-load drive signal terminals LFD of two adjacent rows of multiplexer units 210 in the multiplexer group 21 are adjacent and symmetrical, and the ground signal terminals GND and the touch signal terminals TP of two adjacent rows of multiplexer units 210 in the multiplexer group 21 are symmetrically arranged. The proximity relationship can refer to the description of the first case, which will not be repeated here. In the third case, the touch signal terminals TP of two adjacent rows of multiplexer units 210 in the multiplexer group 21 are adjacent and symmetrical, and the ground signal terminals GND and the anti-load driving signal terminals LFD of two adjacent rows of multiplexer units 210 in the multiplexer group 21 are symmetrically arranged. The proximity relationship can refer to the description of the first case, which will not be repeated here.

[0068] Since each signal terminal corresponds to a thin film transistor 214, the above-mentioned symmetrical method can be symmetrically arranged in the structural arrangement of the thin film transistor 214. For example, the two adjacent thin film transistors 214 of each two adjacent rows of multiplexer units 210 in the multiplexer group 21 share the source S. The shared source S can reduce the number of sources S and the space occupied, thereby reducing the space occupied by the thin film transistor 214 in the vertical direction. For another example, the source S and the drain D of the two adjacent thin film transistors 214 in each multiplexer unit 210 are symmetrically arranged. The symmetrical arrangement of the source S and the drain D of the two adjacent thin film transistors 214 can make the two adjacent thin film transistors 214 share the source S or the drain D, thereby reducing the number of sources S and drain D and the space occupied, and further reducing the space occupied by the thin film transistor 214 in the vertical direction.

[0069] It should be noted that the thin film transistor 214 is a triode, and the thin film transistor 214 may include a gate G, a source S, and a drain D. The thin film transistor 214 may also include an active portion and a channel region, and the gate G is arranged corresponding to the channel region, and the channel region is used for the flow of carriers to connect the source S and the drain D, or to disconnect the source S and the drain D. The gate G, the source S, and the drain D work together to realize the switching and driving performance of the thin film transistor 214. Exemplarily, the gate G may be arranged between the source S and the drain D.

[0070] Exemplarily, the display panel 1 may further include a plurality of gate lines 23 , each gate line 23 connected to a signal terminal of a row of multiplexer units 210 in each multiplexer group 21 , and each gate line 23 disposed between a source S and a drain D of a thin film transistor 214 .

[0071] By symmetrically arranging the thin film transistors 214 to share a common source S or drain D, the number and occupied space of the source S and drain D can be reduced, thereby reducing the occupied space of the multiplexer groups 21 in the vertical direction.

[0072] The devices in the multiple multiplexer groups 21 are arranged symmetrically left and right and symmetrically up and down to reduce the space occupied by the multiple multiplexer groups 21 in the horizontal and vertical directions respectively, without affecting the channel width of the thin film transistor 214, so that the wire arrangement of the display panel 1 is reasonable, the driving performance of the thin film transistor 214 is improved, and the display effect of the display panel 1 is improved.

[0073] Exemplarily, the display panel 1 may further include a plurality of touch lines 24, one end of each touch line 24 is connected to a multiplexer unit 210 in the multiplexer group 21, the other end of each touch line 24 is connected to the touch electrode 11, and each touch line 24 is arranged between two adjacent multiplexer groups 21. Since the touch line 24 is connected to the touch electrode 11, and the number of the touch electrodes 11 is large, in order to reduce the lateral space occupied by the multiple multiplexer groups 21, on the basis of reducing the lateral space occupied by each multiplexer group 21, in order not to affect the above-mentioned reduction in occupied space, the touch line 24 is arranged between two adjacent multiplexer groups 21, so that the occupied space of the multiple multiplexer groups 21 as a whole is still reduced.

[0074] For example, please combine Figures 1 to 9 Also see Figures 10 to 12 , Fig.10 for Figure 1 A fifth partial structural diagram of a display panel is shown, Fig.11 for Figure 1 The sixth partial structural diagram of the display panel shown in FIG. Fig.12 for Figure 1 The seventh partial structural diagram of the display panel shown. The display panel 1 may also include a first test board 25, a second test board 26 and a plurality of third test boards 27. The first test board 25 is connected to a plurality of first input lines 22a. The second test board 26 is connected to a plurality of second input lines 22b. A plurality of third test boards 27 are respectively connected to a plurality of third input lines 22c in a one-to-one correspondence. The first test board 25, the second test board 26 and the plurality of third test boards 27 may be arranged in a row and multiple columns, and the plurality of third test boards 27 are located between the first test board 25 and the second test board 26. Exemplarily, the first test board 25 may be a ground signal test board, that is, to test whether the GND signal can be transmitted normally. The second test board 26 may be a load-resistant drive signal LFD test board, that is, to test whether the LFD signal can be transmitted normally. The third test board 27 may be a touch signal test board, that is, to test whether the TP signal can be transmitted normally.

[0075] A regulating circuit may be provided between each third test board 27 and a third input line 22c. For example, the regulating circuit may be used to filter the signal.

[0076] Multiple multiplexer groups 21 and the first test board 25, the second test board 26 and the third test boards 27 can be arranged in the non-display area of ​​the display panel 1. Exemplarily, the orthographic projection of the chip 20 in the non-display area covers the orthographic projection of the multiple multiplexer groups 21 in the non-display area and the orthographic projection of the first test board 25, the second test board 26 and the third test boards 27 in the non-display area. In other words, multiple multiplexer groups 21, the first test board 25, the second test board 26 and the third test boards 27 can be arranged below the chip 20 to save the occupied area of ​​the above devices in the non-display area, which is conducive to the design of a narrow frame of the display panel 1.

[0077] Exemplarily, the display panel 1 may also include a plurality of enable signal boards 28, wherein the plurality of enable signal boards 28 are connected to the plurality of gate lines 23 in a one-to-one correspondence, and each enable signal board 28 is used to provide an enable signal for a thin film transistor 214 to support the completion of the signal test. Among them, the plurality of enable signal boards 28 are arranged in the non-display area, and the orthographic projections of the plurality of enable signal boards 28 in the non-display area do not overlap with the orthographic projections of the chip 20 in the non-display area. For example, the plurality of enable signal boards 28 may be arranged on one side of the chip 20. By arranging the enable signal board 28 on one side of the chip 20, it is convenient to operate the enable signal board 28 during testing.

[0078] It should be noted that the multiple multiplexer groups 21 can be used to drive multiple multiplexers during testing and when the display panel 1 is working normally, that is, one signal drives multiple touch electrodes 11. During the manufacturing process of the display panel 1, the first test board 25, the second test board 26 and the multiple third test boards 27 can test whether the signal transmission of the multiple touch electrodes 11 in the display area is normal through the first input line 22a, the second input line 22b and the multiple third input lines 22c. After the display panel 1 is manufactured, the first input line 22a, the second input line 22b and the multiple third input lines 22c can be connected to the chip 20 to send control signals to the multiple touch electrodes 11 in the display area through the chip 20.

[0079] It should be noted that the multiple multiplexer groups 21 should not only reduce their horizontal occupied space, but also reduce their vertical occupied space, so as to provide space for the setting of the test board without affecting the setting of other devices in the display panel 1.

[0080] Exemplarily, each multiplexer unit 210 includes a plurality of line-changing arches 215, each of which is used to connect conductive layers of different layers. For example, in the process of setting the source S, the drain D, and the gate G, two layers of metal can be overlapped through the line-changing arch 215 to achieve connection, so as to increase the conductive area of ​​the source S, the drain D, or the gate G under the same area, thereby reducing the impedance and the voltage drop, and improving the conductive performance of the source S, the drain D, or the gate G. In addition, by overlapping the two layers of metal through the line-changing arch 215, the occupied area of ​​the multiplexer unit 210 can also be reduced. Multiple line-changing arches 215 can be arranged in M ​​rows and N columns, and M and N are both positive integers. For example, M and N can both be 4, and the distance between the rows of the line-changing arches 215 is greater than the distance between the columns. Of course, line-changing arches 215 can also be set at other positions to facilitate the connection between the various devices.

[0081] By arranging the multiple multiplexer units 210 in the multiplexer group 21 symmetrically in two columns, all the first signal terminals 211 and all the second signal terminals 212 in the multiple multiplexer units 210 in one multiplexer group 21 only need one first input line 22a and one second input line 22b respectively, and all the third signal terminals 213 in one column of multiplexer units 210 only need one third input line 22c. The same signal terminals share the input line, and there is no need to set an input line for each signal terminal, thereby reducing the number of input lines, and further reducing the distance between the two columns of multiplexer units 210, thereby providing space for the arrangement of the thin film transistors 214.

[0082] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0083] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features.

[0084] The display panel provided in the embodiment of the present application is introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, characterized in that: include: A plurality of multiplexer groups, each of the multiplexer groups comprises a plurality of multiplexer units, the plurality of multiplexer units in the multiplexer groups are symmetrically arranged in two columns, and each of the multiplexer units in the multiplexer groups comprises a first signal terminal, a second signal terminal and a third signal terminal; A plurality of first input lines, each of which is connected to the first signal terminals of all the multiplexer units in one multiplexer group, and each of which is arranged between two columns of multiplexer units in the multiplexer group; a plurality of second input lines, each of which is connected to the second signal terminals of all the multiplexer units in one multiplexer group, and each of which is arranged between two columns of multiplexer units in the multiplexer group; A plurality of third input lines, each of which is connected to a third signal terminal of a column of multiplexer units in one of the multiplexer groups, and two third input lines are provided between two columns of multiplexer units in the multiplexer group.

2. The display panel according to claim 1, characterized in that: The first signal terminals, the second signal terminals and the third signal terminals of two multiplexer units in each row of multiplexer units in the multiplexer group are arranged in the same order.

3. The display panel according to claim 2, characterized in that: Each multiplexer unit in the multiplexer group comprises: three thin film transistors, the three thin film transistors correspond to the first signal terminal, the second signal terminal and the third signal terminal one by one, and the region where the three thin film transistors are located has a first width; There is a second width between two columns of multiplexer units in the multiplexer group, and the second width is smaller than the first width.

4. The display panel according to claim 3, characterized in that: The first signal end, the second signal end and the third signal end of every two adjacent rows of multiplexer units in the multiplexer group are symmetrically arranged.

5. The display panel according to claim 4, characterized in that: Two adjacent thin film transistors of each two adjacent rows of multiplexer units in the multiplexer group share a source electrode; The source and drain of two adjacent thin film transistors in each multiplexer unit are symmetrically arranged; The display panel further includes: A plurality of gate lines, each of which is connected to a signal end of a row of multiplexer units in each multiplexer group, and each of which is arranged between a source and a drain of a thin film transistor.

6. The display panel according to claim 3, characterized in that: The channel width of each of the thin film transistors is greater than 30 micrometers.

7. The display panel according to any one of claims 1 to 6, characterized in that: The display panel further includes: A plurality of touch electrodes; A plurality of touch control lines, one end of each of the touch control lines is connected to a multiplexer unit in the multiplexer group, the other end of each of the touch control lines is connected to the touch control electrode, and each of the touch control lines is arranged between two adjacent multiplexer groups.

8. The display panel according to claim 5, characterized in that: The display panel further includes: A first test board connected to the plurality of first input lines; A second test board connected to the plurality of second input lines; A plurality of third test boards are respectively connected to the plurality of third input lines in a one-to-one correspondence.

9. The display panel according to claim 8, characterized in that: The first test board, the second test board and the plurality of third test boards are arranged in a row and multiple columns, and the plurality of third test boards are located between the first test board and the second test board.

10. The display panel according to claim 8, characterized in that: The display panel includes a display area and a non-display area surrounding the display area, and the display panel further includes: The chip is arranged in a non-display area, and the orthographic projection of the chip in the non-display area covers the orthographic projections of multiple multiplexer groups in the non-display area and the orthographic projections of the first test board, the second test board and multiple third test boards in the non-display area.

11. The display panel according to claim 10, characterized in that: The display panel further includes: A plurality of enable signal plates are connected to the plurality of gate lines in a one-to-one correspondence, each of the enable signal plates is used to provide an enable signal for a thin film transistor, and the orthographic projections of the plurality of enable signal plates in the non-display area do not overlap with the orthographic projections of the chip in the non-display area.

12. The display panel according to claim 1, characterized in that: A column of multiplexer units in each of the multiplexer groups includes six multiplexer units.

13. The display panel according to claim 1, characterized in that: Each of the multiplexer units includes a plurality of line-changing arches, each of which is used to connect metals of different layers, and the plurality of line-changing arches are arranged in M ​​rows and N columns, where M and N are both positive integers.

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