A motherboard and related components

Abstract

The invention discloses a mainboard and related components, and relates to the field of board design. A BGA group comprises a first BGA chip and a second BGA chip, each pin of which is arranged in a one-to-one correspondence and is respectively placed on a top layer and a bottom layer. A plurality of mutually spaced and straight conductive through holes are provided on a PCB board. Since the pins are arranged in a corresponding manner, a first conductive material is plated in the conductive through holes to realize a straight connection of UPI signals, which greatly shortens the length of the UPI wiring. A double-sided layout method is used to replace the original single-sided layout method, which reduces the area of ​​the PCB board and improves the space utilization rate of the PCB board. The thickness of the first conductive material is set to be the same as the thickness of an inner copper foil, and the width is set to be the same as the preset UPI wiring width, which solves the impedance mismatch problem of the UPI wiring in the prior art, no residual piles exist, and there is no need to additionally set an anti-pad, which simplifies the PCB design, is simple to process and manufacture, has a low process cost, is easy to realize, and is more practical.

Description

Technical Field

[0001] The present invention relates to the technical field of board design, and in particular to a mainboard and related components. Background Art

[0002] With the development of electronic information technology and the increasing demand for signal transmission rate, R&D designers need to consider and deal with many problems in the design process of the PCB (Printed Circuit Board) of the motherboard more carefully. Specifically, BGA technology (Ball Grid Array) is currently widely used in the layout and packaging of CPU chips (Central Processing Unit). Taking a dual-channel motherboard as an example, in the prior art, two CPU chips after BGA packaging will be arranged on the same side of the multi-layer PCB board, that is, the top side, such as Figure 1 As shown in the figure, one CPU is defined as CPU0 and the other CPU is defined as CPU1. The UPI signal used for communication between the two CPU chips will fan out from CPU0 and reach CPU1 through the open area in the middle to realize the UPI (Ultra Path Interconnect) signal routing. The specific routing diagram is shown in the figure. Figure 2 shown.

[0003] It can be seen that currently, for CPU chips processed by BGA technology, only a single-sided layout method (i.e., all layouts are on the top surface) can be adopted. This method occupies a large PCB board space, which is not conducive to reducing product design and production costs; the transmission rate of UPI signals is very high, and according to actual needs, a CPU usually includes multiple groups of UPI signals, and each group further includes, for example, 16 pairs of UPI routing lines, which requires R&D technicians to spend more time and energy on designing in order to achieve routing across the middle area while ensuring UPI transmission performance, but referring to Figure 2It can be seen that in the BGA fan-out area, the UPI routing in this way needs to occupy a large number of wiring layers and cross a very long routing channel. For the routing channel, due to the limitation of the PCB board space, some routing cannot be set according to the normal UPI routing width, and can only be routed according to the neck mode (neck mode) narrower than the original routing width until there is enough space, and then restored to the original normal UPI routing width. However, this will make it impossible to control the impedance of the UPI signal in this area, resulting in discontinuous impedance of the UPI signal in the BGA fan-out area. In addition, in this single-sided layout method, in order to meet the routing of different wiring layers, vias need to be set from top to bottom. The via design is usually A large section of stubs will remain (for example, assuming that the number of layers of the PCB board is 10, the via design will be directly opened from the 1st layer to the 10th layer, but the actual routing only uses layers 1 to 5, and the remaining stubs are not used, causing signal integrity problems). In the prior art, an additional back drilling process is required to shorten the stubs, but this has increased production costs. Moreover, this method is limited by the process and can only reduce a part of the stubs. A section of the stubs (such as 10 mils) remains that cannot be eliminated at all, which is not conducive to reducing signal reflections. In addition, there is a need to set an additional anti-pad near the via to solve the impedance discontinuity problem at the via, which also makes the PCB board design and process implementation more complicated, which is not conducive to production practice. Summary of the invention

[0004] The purpose of the present invention is to provide a mainboard and related components, which greatly shorten the length of the UPI routing, utilize a double-sided layout method to replace the single-sided layout method in the prior art, greatly reduce the area of ​​the PCB board, improve the space utilization rate of the PCB board, solve the impedance mismatch problem faced by the UPI routing in the prior art, and no longer have residual piles, and do not need to additionally set up anti-pads, thereby simplifying the PCB design, simplifying the processing and manufacturing, and having low process cost, easy to implement, and more practical.

[0005] In order to solve the above technical problems, the present invention provides a motherboard, comprising a multi-layer PCB board and a BGA group, wherein the BGA group comprises a first BGA chip arranged on the top layer of the PCB board and a second BGA chip arranged on the bottom layer of the PCB board, and each pin of the first BGA chip and each pin of the second BGA chip are arranged in a one-to-one correspondence;

[0006] The PCB board includes a plurality of conductive through holes which are spaced apart from each other and vertically penetrate from the top layer to the bottom layer, wherein the conductive through holes are plated with a first conductive material having a thickness equal to that of the inner copper foil of the PCB board and a width equal to a preset UPI trace width;

[0007] The conductive through hole is used to electrically connect the first UPI port of the first BGA chip and the second UPI port of the second BGA chip which are placed in a one-to-one correspondence.

[0008] Preferably, the PCB board also includes a connecting through hole, in which a second conductive material is plated, and the connecting through hole vertically penetrates from the top layer to the bottom layer;

[0009] The connecting through hole is used to electrically connect the first power port of the first BGA chip and the second power port of the second BGA chip which are placed in a one-to-one correspondence.

[0010] Preferably, it further comprises a top heat dissipation module arranged on the top layer and a bottom heat dissipation module arranged on the bottom layer;

[0011] The top-layer heat dissipation module is used to dissipate heat for the first BGA chip;

[0012] The bottom heat dissipation module is used to dissipate heat for the second BGA chip.

[0013] Preferably, the top-layer heat dissipation module and the bottom-layer heat dissipation module are air-cooled radiators or liquid-cooled radiators.

[0014] Preferably, the first BGA chip further includes a first routing end to be fanned out; the second BGA chip further includes a second routing end to be fanned out;

[0015] The PCB board also includes a plurality of first recessed grooves spaced apart from each other, wherein the first recessed grooves near the edge of the first BGA chip are shallower, and the first recessed grooves near the center of the first BGA chip are deeper;

[0016] The first sink groove is plated with a third conductive material having the same thickness as the inner copper foil, and is used to fan out each of the first to-be-fanned routing ends of the first BGA chip through the corresponding first sink groove;

[0017] The PCB board also includes a plurality of second sunken grooves spaced apart from each other, wherein the second sunken grooves near the edge of the second BGA chip are shallower, and the second sunken grooves near the center of the second BGA chip are deeper, and the first sunken grooves are not connected to the second sunken grooves;

[0018] The second sink groove is plated with a third conductive material having the same thickness as the inner copper foil, and is used to fan out each of the second to-be-fanned routing ends of the second BGA chip through the corresponding second sink groove.

[0019] Preferably, the PCB board is further provided with a plurality of function module groups, each of the function module groups comprises a first function module provided at the top layer and a second function module provided at the bottom layer, and each pin of the first function module is provided in a one-to-one correspondence with each pin of the second function module;

[0020] The PCB board also includes a plurality of third sink grooves spaced apart from each other, the third sink grooves are connected to each of the functional sink grooves one by one, and the third sink grooves are plated with the third conductive material having the same thickness as the inner copper foil; the third sink grooves are used to electrically connect the functional fan-out routing end with the corresponding target functional end of the target functional module in combination with the functional sink grooves;

[0021] Among them, the functional sink is a first sink or a second sink, and when the functional sink is a first sink, the functional routing end to be fanned out is a first routing end to be fanned out and the target functional module is a first functional module; when the functional sink is a second sink, the functional routing end to be fanned out is a second routing end to be fanned out and the target functional module is a second functional module.

[0022] Preferably, the first routing end to be fanned out is a first PCIE routing end or a first CLK routing end or a first storage signal end or a first DDR signal end;

[0023] Correspondingly, the second routing end to be fanned out is a second PCIE routing end or a second CLK routing end or a second storage signal end or a second DDR signal end.

[0024] In order to solve the above technical problems, the present invention further provides a method for opening a conductive through hole, which is used to open the conductive through hole on the above-mentioned PCB board. The method for opening the conductive through hole comprises:

[0025] Acquire a first target position of the first UPI port to be installed and a second target position of the second UPI port to be installed;

[0026] Based on the first target position and the second target position, drilling N first preset through holes whose central axes coincide with each other and are at first preset angles to each other, wherein the first preset through holes vertically penetrate from the top layer to the bottom layer, and N is an integer not less than 2;

[0027] Electroplating the first conductive material in each of the first preset through holes with a thickness equal to that of the inner copper foil;

[0028] With the central axis as the center axis, a second preset through hole with a diameter smaller than the length of the first preset through hole is drilled, and the second preset through hole vertically penetrates from the top layer to the bottom layer, so as to cut the through hole structure composed of the first preset through holes into 2N conductive through holes, and the width of the first conductive material electroplated in each of the conductive through holes is the preset UPI routing width, and the edges of each of the conductive through holes do not overlap, so that the first UPI port and the corresponding second UPI port are electrically connected through the first conductive material in the corresponding conductive through hole.

[0029] In order to solve the above technical problems, the present invention further provides a method for opening a connecting through hole, which is used to open the connecting through hole on the above-mentioned PCB board. The method for opening the connecting through hole comprises:

[0030] Acquire a third target position of the first power port to be installed and a fourth target position of the second power port to be installed;

[0031] Based on the third target position and the fourth target position, M third preset through holes whose central axes coincide with each other and are at a second preset angle to each other are drilled, wherein the third preset through holes vertically penetrate from the top layer to the bottom layer, and M is a positive integer;

[0032] The connecting through holes are obtained after the second conductive material is electroplated in each of the third preset through holes, so that the first power port is electrically connected to the corresponding second power port through the second conductive material in the corresponding connecting through holes.

[0033] In order to solve the above technical problem, the present invention further provides an electronic device, comprising the mainboard as described above.

[0034] The present application provides a mainboard and related components, the mainboard includes a multi-layer PCB board and a BGA group, the BGA group includes pins arranged one by one to place a first BGA chip and a second BGA chip on the top layer and the bottom layer of the PCB board respectively, the PCB board includes a plurality of conductive through holes spaced from each other and vertically penetrating from the top layer to the bottom layer, due to the corresponding placement of the pins, the first conductive material is plated in the conductive through holes, the UPI signal direct connection between the first BGA chip and the second BGA chip can be achieved, the length of the UPI routing is greatly shortened, the signal loss is effectively reduced, and the transmission quality of the UPI signal is improved. The double-sided layout method is used to replace the single-sided layout method in the prior art, which greatly reduces the area of ​​the PCB board, improves the space utilization rate of the PCB board, and reduces the design cost. The thickness of the first conductive material is set to be the same as the thickness of the inner copper foil of the PCB board, and the width is set to be the same as the width of the preset UPI line, which solves the impedance mismatch problem faced by the UPI line in the prior art. There are no residual piles, and there is no need to set up an additional anti-pad, which simplifies the PCB design, is simple to process and manufacture, has a low process cost, is easy to implement, is more practical, and is convenient for large-scale application in the field of PCB board processing and manufacturing of motherboards. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the prior art and the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0036] Figure 1 It is a structural schematic diagram of a single-sided layout of a dual-channel motherboard in the prior art;

[0037] Figure 2 It is a structural schematic diagram of specific wiring in a single-sided layout mode of a dual-channel motherboard in the prior art;

[0038] Figure 3 A schematic diagram of the structure of a mainboard provided by the present invention;

[0039] Figure 4 A schematic diagram of the structure of another mainboard provided by the present invention;

[0040] Figure 5 A schematic diagram of the structure of another mainboard provided by the present invention;

[0041] Figure 6 A schematic diagram of the structure of another mainboard provided by the present invention;

[0042] Figure 7A schematic diagram of a double-sided layout structure of a functional module group on a mainboard provided by the present invention;

[0043] Figure 8 A schematic diagram of the structure of a conductive through hole provided by the present invention;

[0044] Fig. 9 A schematic diagram of the structure of another conductive through hole provided by the present invention;

[0045] Fig.10 A schematic diagram of the structure of another conductive through hole provided by the present invention;

[0046] Fig.11 A schematic diagram of the structure of a connecting through hole provided by the present invention;

[0047] Fig.12 A schematic structural diagram of another connecting through hole provided by the present invention. DETAILED DESCRIPTION

[0048] The core of the present invention is to provide a mainboard and related components, which greatly shorten the length of the UPI routing, use a double-sided layout method to replace the single-sided layout method in the prior art, greatly reduce the area of ​​the PCB board, improve the space utilization rate of the PCB board, solve the impedance mismatch problem faced by the UPI routing in the prior art, and no longer have residual piles, and no need to set up additional anti-pads, simplifying the PCB design, simple processing and manufacturing, low process cost, easy to implement, and more practical.

[0049] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0050] Please refer to Figure 1 , Figure 2 and Figure 3 , Figure 1 The schematic diagram of the structure of a single-sided layout of a dual-channel motherboard in the prior art is shown in FIG. Figure 2 It is a structural schematic diagram of specific wiring in a single-sided layout mode of a dual-channel motherboard in the prior art. Figure 3 A schematic structural diagram of a mainboard provided by the present invention.

[0051] The motherboard includes a multi-layer PCB board 1 and a BGA group, wherein the BGA group includes a first BGA chip 2 arranged on the top layer of the PCB board 1 and a second BGA chip 3 arranged on the bottom layer of the PCB board 1, and each pin of the first BGA chip 2 and each pin of the second BGA chip 3 are arranged in a one-to-one correspondence;

[0052] The PCB board 1 includes a plurality of conductive through holes 4 which are spaced apart from each other and vertically penetrate from the top layer to the bottom layer. The conductive through holes 4 are plated with a first conductive material having a thickness equal to that of the inner copper foil of the PCB board 1 and a width equal to a preset UPI trace width;

[0053] The conductive through hole 4 is used to electrically connect the first UPI port of the first BGA chip 2 with the second UPI port of the second BGA chip 3 which is placed in a one-to-one correspondence.

[0054] In this embodiment, considering that the layout of the motherboard in the prior art usually adopts a single-sided layout, the specific reference is made to Figure 1 and Figure 2 As shown ( Figure 1 and Figure 2 In the examples above, a dual-channel motherboard is used as an example), which results in a large space occupied by the PCB board 1, which is not conducive to reducing the design and production costs of the product. Figure 2 It can be seen that the routing of UPI signals in the prior art needs to occupy a large number of wiring layers and the routing channel is very long. Due to the limitation of the board space, it is easy to have impedance mismatch problems; and in order to meet the routing needs of different wiring layers, vias are set, but usually residual piles are left. Even if a complex back drilling process is used, the residual piles cannot be completely eliminated, and there is also a need to set anti-pads to solve the problem of impedance discontinuity at the vias, resulting in complex design and process implementation of the PCB board 1 of the entire motherboard, which is not conducive to production practice. In order to solve the above technical problems, the present invention provides a motherboard, which uses a double-sided layout method instead of the single-sided layout method in the prior art to solve the above-mentioned technical problems.

[0055] First of all, it should be noted that the number of the BGA groups can be one group or multiple groups, which is not particularly limited here; the BGA chip can be various types of chips involved in PCB design, specifically, the first BGA chip 2 includes but is not limited to a first CPU chip processed by BGA technology, and correspondingly, the second BGA chip 3 can be a second CPU chip processed by BGA technology; therefore, the first BGA chip 2 is placed on the top layer of the PCB board 1 and the second BGA chip 3 is placed on the bottom layer of the PCB board 1. It should be noted that the pins of the first BGA chip 2 and the pins of the second BGA chip 3 are placed in a one-to-one correspondence, that is, the BGA group is placed according to the principle of pin overlap relative to the board. Specifically, the one-to-one placement can be understood as: the signal definitions on the two one-to-one corresponding pins are the same. For example, a pin of the first BGA chip 2 on the top layer is defined as a UPI signal, and the pin at the same position of the correspondingly placed second BGA chip 3 on the bottom layer is also defined as a UPI signal. In this way, the UPI signal only needs to pass through one hole (i.e., the conductive through hole 4) from the top layer to reach the bottom layer during routing, thereby realizing the connection of the pins at corresponding positions, and the path is very short.

[0056] For details, please refer to Figure 3 , Figure 3 A schematic diagram of the structure of a mainboard provided by the present invention, wherein the Figure 3 As an example of a three-dimensional structure, the multi-layer PCB board 1 specifically includes four layers of copper foil, and due to the three-dimensional structure, the edge of part of the PCB board 1 is drawn with a dotted line, which is limited by Figure 3 For the purpose of illustration, only the first BGA chip 2 includes two first UPI ports (in Figure 3 The second BGA chip 3 includes two second UPI ports (in the form of black circles) placed one by one with the above-mentioned first UPI ports. Figure 3 In the figure, it is still given as a black circle) as an example, and for the sake of clarity, in fact Figure 3 The first UPI port and the second UPI port in the figure are enlarged by a considerable multiple. In the real object, they are usually very small UPI ports. Figure 3 , showing that only one conductive through hole 4 is needed to realize electrical connection between the first UPI port located at the upper layer and the second UPI port located at the same position at the lower layer (it can be understood that the electrical connection is limited by Figure 3 The display space and three-dimensional display, here the conductive through hole 4 is shown in a simple structure in the form of dotted lines and shadows, and the actual design should meet the description of the above text part, therefore, Figure 3 This is just a simple explanation of the arrangement of the conductive via 4).

[0057] It is understood that the description of the width and thickness of the first conductive material in the conductive through hole is detailed in the following embodiments. Fig.10 And the corresponding explanations will not be repeated here.

[0058] It should be noted that the UPI signal is essentially the interconnection between the first BGA chip 2 and the second BGA chip 3. The total number of the first UPI ports of the first BGA chip 2 is usually multiple, and the total number of the second UPI ports of the corresponding second BGA chip 3 is the same as the total number of the first UPI ports and is also the multiple. It can be understood that the conductive through hole 4 used for electrical connection of a group of UPI ports (i.e., a first UPI port and a correspondingly placed second UPI port) is not the same as the conductive through hole 4 used for electrical connection of another group of UPI ports (i.e., another first UPI port and a correspondingly placed second UPI port); the first conductive material includes but is not limited to copper. In combination with actual application, the thickness of the first conductive material is but is not limited to 1.2 mils (mils), and the preset UPI routing width can be determined according to the actual setting requirements, but the width of the first conductive material should be equal to it; in addition, the conductive through holes 4 themselves are not interconnected, that is, they are spaced apart from each other.

[0059] It should also be noted that the method for actually operating the conductive through hole 4 can be: first determine the position of the first UPI port on the top layer and the position of the second UPI port on the bottom layer, and then drill holes with a certain diameter directly near the two positions. However, due to the limitations of the current drilling process (such as the minimum aperture limit), in actual operation, drilling holes of relatively small sizes may not be easy or even impossible to achieve, that is, the drilling results obtained in this way may not be able to meet the routing requirements of the PCB board 1. Therefore, the present application also provides a method for opening a conductive through hole 4, which is specifically described in the following embodiments.

[0060] In summary, the present application provides a motherboard, which includes a multi-layer PCB board 1 and a BGA group. The BGA group includes pins arranged one by one to be placed on the top layer and the bottom layer of the PCB board 1, respectively. The PCB board 1 includes a plurality of conductive through holes 4 that are spaced apart from each other and vertically penetrate from the top layer to the bottom layer. Since the pins are placed in correspondence, a first conductive material is plated in the conductive through hole 4, so that a UPI signal direct connection between the first BGA chip 2 and the second BGA chip 3 can be achieved, which greatly shortens the length of the UPI routing, effectively reduces the signal loss, and improves the transmission quality of the UPI signal. The surface layout mode replaces the single-sided layout mode in the prior art, greatly reduces the area of ​​the PCB board 1, improves the space utilization rate of the PCB board 1, improves the layout density of the PCB board 1, and reduces the design cost. The thickness of the first conductive material is set to be the same as the thickness of the inner copper foil of the PCB board 1 and the width is the same as the preset UPI wiring width, which solves the impedance mismatch problem faced by the UPI wiring in the prior art, and no residual piles exist, and there is no need to set up an additional anti-pad, which simplifies the PCB design, is simple to process and manufacture, has a low process cost, is easy to implement, and is more practical, so that it is convenient for large-scale application in the processing and manufacturing field of the PCB board 1 of the motherboard.

[0061] Based on the above embodiments:

[0062] As a preferred embodiment, the PCB board 1 further includes a connecting through hole, in which a second conductive material is plated, and the connecting through hole vertically penetrates from the top layer to the bottom layer;

[0063] The connecting through hole is used to electrically connect the first power port of the first BGA chip 2 with the second power port of the second BGA chip 3 which is placed in a one-to-one correspondence.

[0064] In this embodiment, considering that the first BGA chip 2 includes the routing of power signals, i.e., the first power port, in addition to the routing of UPI signals, and the second BGA chip 3 also includes the routing of power signals (i.e., the second power port), the present application provides a routing method for power signals. It can be understood that, since the pins of the first BGA chip 2 and the pins of the second BGA chip 3 are arranged one by one, the position of the first power port on the top layer corresponds to the position of the second power port on the bottom layer, and therefore, the connection between the first power port and the second power port at the corresponding position can be realized by setting a connecting through hole that vertically penetrates from the top layer to the bottom layer.

[0065] It should be noted that the second conductive material includes but is not limited to copper, and the thickness of the second conductive material can be set as thick as possible according to actual needs to ensure sufficient current carrying capacity, such as 2 mils; in addition, according to actual needs, the total number of the first power ports can be multiple, and the corresponding total number of the second power ports is the same as the total number of the first power ports, that is, the multiple; and it can be understood that the connecting through hole used for electrical connection of a group of power ports (i.e., a first power port and a correspondingly placed second power port) is not the same as the connecting through hole used for electrical connection of another group of power ports (i.e., another first power port and a correspondingly placed second power port).

[0066] It should also be noted that the method for actually operating the connecting through hole can be: first determine the position of the first power port on the top layer and the position of the second power port on the bottom layer, and then, drill holes with a certain diameter directly near these two positions. However, it has been explained above that, due to the limitations of the current drilling process (such as the minimum aperture limit), in actual operation, drilling holes of relatively small sizes may not be easy or even impossible to achieve, that is, the drilling results obtained in this way may not be able to meet the routing requirements of the PCB board 1. Therefore, the present application also provides a method for opening a connecting through hole, which is specifically described in the following embodiments.

[0067] It can be seen that through the above settings, the routing of the power signal in the BGA group under the double-sided layout is realized to realize the power supply of the BGA chip.

[0068] As a preferred embodiment, it further comprises a top heat dissipation module arranged on the top layer and a bottom heat dissipation module arranged on the bottom layer;

[0069] The top heat dissipation module is used to dissipate heat for the first BGA chip 2;

[0070] The bottom heat dissipation module is used to dissipate heat for the second BGA chip 3 .

[0071] In this embodiment, since a double-sided layout is adopted, a top-level heat dissipation module can be set on the top layer to achieve heat dissipation of the first BGA chip 2 (and other functional devices on the top layer); a bottom-level heat dissipation module is set on the bottom layer to achieve heat dissipation of the second BGA chip 3 (and other functional devices on the bottom layer) to ensure the normal and safe operation of the chips.

[0072] As a preferred embodiment, the top heat dissipation module and the bottom heat dissipation module are air-cooled radiators or liquid-cooled radiators.

[0073] In this embodiment, the inventors further considered that since the size of the heat dissipation module is usually large, when the size requirements for the mainboard are relatively loose, the top heat dissipation module and the bottom heat dissipation module can be set as air-cooled radiators with a relatively high height; when the size requirements for the mainboard are relatively strict, the top heat dissipation module and the bottom heat dissipation module can be set as liquid-cooled radiators with a relatively low height (the working principle of which is to cover the top and bottom layers of the PCB board 1 with a liquid, and to carry away heat through the circulation of the liquid to achieve cooling), which can greatly reduce the size of the mainboard and is convenient for use in electronic equipment with limited height.

[0074] Specifically, the motherboard can be applied to a server chassis. When the server chassis is a 4U server chassis (1U=4.445 cm) in height, the top heat dissipation module and the bottom heat dissipation module can be set as a higher air-cooled radiator; when the server chassis is a 1U or 2U server chassis, the top heat dissipation module and the bottom heat dissipation module can be set as a lower liquid-cooled radiator to enhance the applicability of the motherboard.

[0075] As a preferred embodiment, the first BGA chip 2 further includes a first routing end to be fanned out; the second BGA chip 3 further includes a second routing end to be fanned out;

[0076] The PCB board 1 also includes a plurality of first recessed grooves spaced apart from each other, wherein the first recessed grooves near the edge of the first BGA chip 2 are shallower, and the first recessed grooves near the center of the first BGA chip 2 are deeper;

[0077] The first sink groove is plated with a third conductive material having the same thickness as the inner copper foil, and is used to fan out each first to-be-fanned wiring end of the first BGA chip 2 through the corresponding first sink groove;

[0078] The PCB board 1 also includes a plurality of second recessed grooves spaced apart from each other, wherein the second recessed grooves near the edge of the second BGA chip 3 are shallower, and the second recessed grooves near the center of the second BGA chip 3 are deeper, and the first recessed grooves are not connected to the second recessed grooves;

[0079] The second sink groove is plated with a third conductive material having the same thickness as the inner copper foil, and is used to fan out each second to-be-fanned wiring end of the second BGA chip 3 through the corresponding second sink groove.

[0080] In this embodiment, the inventor further considers that the first BGA chip 2 has other signals to be fanned out. These signals to be fanned out are different from UPI signals. These signals are not interconnected between the first BGA chip 2 and the second BGA chip 3, but need to be fanned out by the first BGA chip 2 and the second BGA chip 3 respectively, and then connected to other connectors or small chips, etc. Therefore, the present application also provides a specific fan-out method for these signals to be fanned out.

[0081] Specifically, the first sink groove used for fanning out a first routing end to be fanned out is not the same as the first sink groove used for fanning out another first routing end to be fanned out and is spaced from each other, and the same is true for the second routing end to be fanned out. Secondly, the above-mentioned setting mechanism of: the first sink groove near the edge of the first BGA chip 2 is shallower, the first sink groove near the center of the first BGA chip 2 is deeper, and the second sink groove near the edge of the second BGA chip 3 is shallower, and the second sink groove near the center of the second BGA chip 3 is deeper is explained as follows:

[0082] First, please refer to Figure 4 , Figure 4 A schematic diagram of another mainboard structure provided by the present invention, limited by Figure 4 The focus of the display is to temporarily omit the internal multi-layer structure of the PCB board 1, the conductive through hole 4 and the display schematic of the connecting through hole, and instead explain the first to-be-fanned-out wiring end and the second to-be-fanned-out wiring end. Taking the first to-be-fanned-out wiring end as an example, Figure 4 The first fan-out wiring ends 22, 23, 24 and 25 are shown in FIG. 1 , and the center position of the first BGA chip 2 can be as follows: Figure 4 The dotted line 21 shown in FIG is located at the position, so for the fan-out of each first fan-out routing end (it can be seen that, Figure 4 In the figure, all of them are on the left side of the first BGA chip 2), assuming that the fan-out direction of each first fan-out trace end currently located on the left side of the first BGA chip 2 is: vertically downward from the top layer to the first target layer, and then fan out to the left after reaching the first target layer, so it can be understood that if we follow Figure 4, the left view can be obtained by looking at the arrows indicated in the figure, then the projections of the first routing end 22 to be fanned out and the first routing end 23 to be fanned out on the left view do not overlap, so the first sinks corresponding to the two can be opened to the same first target layer, and it is only necessary to satisfy that the two sinks are spaced apart from each other so that the routings do not overlap or intersect; however, still from the perspective of the left view, the projections of the first routing end 23 to be fanned out, the first routing end 24 to be fanned out, and the first routing end 25 to be fanned out on the left view will overlap on the same straight line, therefore, if the first sink corresponding to the first routing end 25 to be fanned out is opened wider than the first routing end 23 to be fanned out If the corresponding first groove is deep, then when the first routing end 23 to be fanned out fans out to the left, there will be an overlapping part with the path when the first routing end 25 to be fanned out fans out to the left, which obviously does not meet the requirements. Therefore, the first groove corresponding to the first routing end 23 to be fanned out should be set to the deepest, and the first groove corresponding to the first routing end 24 to be fanned out should be the second deepest, and the first groove corresponding to the first routing end 23 to be fanned out should be set to the shallowest. That is to say, when the routings are all fanned out to the left, the distance between the overlapping first routing ends to be fanned out and the center position of the first BGA chip 2 in the left view is inversely proportional to the depth of the first groove. The closer the distance, the deeper the depth. Figure 4 In the figure, second fan-out wiring ends 32, 33, 34 and 35 are also provided. The center position of the second BGA chip 3 can be as follows: Figure 4 The position of the dotted line 31 shown in the figure is the same as the analysis of the first fan-out routing ends 22, 23, 24 and 25, and will not be repeated here. Therefore, the reliability of the depth setting method of the first sink groove and the second sink groove described in the present application is proved. By setting a plurality of mutually spaced first sink grooves and a plurality of mutually spaced second sink grooves, and each of the first sink grooves is not connected to each of the second sink grooves, all PCB board layers can be used for wiring to the greatest extent, and the mutual crosstalk between the signals to be fanned out can be avoided, thereby improving the integrity of the signal.

[0083] It should also be noted that, since the pins of the first BGA chip 2 and the second BGA chip 3 are the same, the routing layer resources of the multi-layer PCB board 1 for the signal routing to be fanned out can be evenly divided; in addition, please refer to Figure 5 , Figure 5 A schematic diagram of another mainboard structure provided by the present invention, wherein the Figure 5The focus of the display is only to give a schematic diagram of the multi-layer structure of the PCB board 1 (the board layer structure is from layer L01 to layer L12, and adhesive materials are included between layers) and the structure of the first sink groove and the second sink groove opened thereon, wherein the center position of the first BGA chip 2 is given in the form of a first circle 26, and the center position of the second BGA chip 3 is given in the form of a second circle 36. It can be seen that the first sink groove corresponding to the first wiring end G1 to be fanned out near the edge of the first BGA chip 2 is shallower, and the first sink groove corresponding to the first wiring end G2 to be fanned out near the center position of the first BGA chip 2 is deeper; the second sink groove corresponding to the second wiring end J1 to be fanned out near the edge of the second BGA chip 3 is shallower, and the second sink groove corresponding to the second wiring end J2 to be fanned out near the center position of the second BGA chip 3 is deeper. Figure 6 A schematic diagram of another mainboard structure provided by the present invention, wherein the Figure 6 The key points of the display are only for demonstration and the specific settings of the board layers of the PCB board 1 are ignored for the time being. It can be seen that the first routing end to be fanned out can be fanned out to the left and right respectively, and the closer to the center position of the BGA chip (that is, the center position of the first BGA chip 2 is given in the form of a first circle 26, and the center position of the second BGA chip 3 is given in the form of a second circle 36), the deeper the groove depth is, and the same is true for the second routing end to be fanned out.

[0084] The third conductive material includes but is not limited to copper, and the thickness of the third conductive material includes but is not limited to 1.2 mils.

[0085] As a preferred embodiment, a plurality of function module groups are further arranged on the PCB board 1, each function module group includes a first function module arranged on the top layer and a second function module arranged on the bottom layer, and each pin of the first function module is arranged in a one-to-one correspondence with each pin of the second function module;

[0086] The PCB board 1 also includes a plurality of third sink grooves spaced apart from each other, the third sink grooves are connected to each functional sink groove one by one, and the third sink grooves are plated with a third conductive material having the same thickness as the inner copper foil; the third sink grooves are used to electrically connect the functional fan-out routing end with the target functional end of the corresponding target functional module in combination with the functional sink grooves;

[0087] Among them, the functional sink is the first sink or the second sink, and when the functional sink is the first sink, the functional routing end to be fanned out is the first routing end to be fanned out and the target functional module is the first functional module; when the functional sink is the second sink, the functional routing end to be fanned out is the second routing end to be fanned out and the target functional module is the second functional module.

[0088] In this embodiment, a plurality of functional module groups can be arranged on the PCB board 1, and each pin of the first functional module on the top layer is arranged in one-to-one correspondence with each pin of the second functional module on the bottom layer to realize a double-sided layout. The first functional module can be a first DIMM (Dual Inline Memory Modules) and the corresponding second functional module is a second DIMM; the first functional module can also be a first patch connector and the corresponding second functional module is a second patch connector. The patch connector can be used to plug in other devices, such as PCIE devices, to realize the connection after the PCIE signal is fanned out, which is not particularly limited here. For details, please refer to Figure 7 , Figure 7 A schematic diagram of a double-sided layout structure of a functional module group on a mainboard provided by the present invention, Figure 7 In the figure, only as a schematic diagram, the functional module group is specifically set as follows: the first functional module is the first DIMM strip 5, and the second functional module is the second DIMM strip 6.

[0089] It can be understood that since the third trough is connected to each functional trough one by one, the functional fan-out wiring end passes through the third conductive material in the functional trough, and then passes through the third conductive material in the connected third trough, and can be connected to the target functional end to be connected of the target functional module, and the trough components (including the functional trough and the subsequently connected third trough) passed by different functional fan-out wiring ends are different to avoid mutual interference between signals.

[0090] It can be seen that the double-sided layout of multiple functional module groups and the corresponding sink routing method are beneficial to improving the space utilization of PCB boards and increasing the layout density of PCB boards.

[0091] As a preferred embodiment, the first routing end to be fanned out is a first PCIE routing end or a first CLK routing end or a first storage signal end or a first DDR signal end;

[0092] Correspondingly, the second routing end to be fanned out is the second PCIE routing end or the second CLK routing end or the second storage signal end or the second DDR signal end.

[0093] In this embodiment, it can be understood that whether it is PCIE signal routing, CLK clock signal routing, or DDR signal routing, it can be implemented under the provided double-sided layout structure, relying on the opening of sink grooves to achieve signal fan-out, which is beneficial to improving the space utilization of PCB boards and increasing the layout density of PCB boards.

[0094] The present invention also provides a method for forming a conductive through hole, which is used to form a conductive through hole on the above-mentioned PCB board. The method for forming a conductive through hole comprises:

[0095] Acquire a first target position of a first UPI port to be installed and a second target position of a second UPI port to be installed;

[0096] Based on the first target position and the second target position, N first preset through holes whose central axes coincide and are at first preset angles to each other are drilled, the first preset through holes vertically penetrating from the top layer to the bottom layer, where N is an integer not less than 2;

[0097] Electroplating a first conductive material having the same thickness as the inner copper foil in each first preset through hole;

[0098] With the central axis as the center axis, a second preset through hole with a diameter smaller than the length of the first preset through hole is drilled, and the second preset through hole vertically penetrates from the top layer to the bottom layer, so as to cut the through hole structure composed of the first preset through holes into 2N conductive through holes, and the width of the first conductive material electroplated in each conductive through hole is the preset UPI routing width, and the edges of each conductive through hole do not overlap, so that the first UPI port and the corresponding second UPI port are electrically connected through the first conductive material in the corresponding conductive through hole.

[0099] In this embodiment, taking into account what is described in the above embodiments, and limited by the actual aperture requirements of the current drilling process, a method for opening a conductive through hole is provided. Compared with directly drilling through holes with a certain diameter around the locations of each first UPI port, it is easier to operate and can drill through holes of smaller specifications, thereby optimizing the routing hole design of the UPI signal.

[0100] Specifically, the method includes but is not limited to being applied to a processor, and then the processor controls the drilling equipment to perform the drilling action to realize automated drilling, that is, first obtaining a first target position of a first UPI port to be installed on the top layer and a second target position of a second UPI port to be installed on the bottom layer, and pre-designing and calculating a preset UPI routing width, then, based on the first target position and the second target position, drilling N first preset through holes whose central axes coincide and are at a first preset angle to each other, wherein the first preset angle can be set to 30 degrees or 90 degrees according to actual needs, and is not particularly limited here; a first conductive material having the same thickness as that of the inner copper foil is electroplated in each first preset through hole, and then, The central axis is the central axis, and a second preset through hole with a diameter smaller than the length of the first preset through hole is drilled (the diameter is set according to actual needs, smaller than the first preset through hole within a certain range, and the certain range needs to ensure the routing, and cannot be too small), and the second preset through hole is still vertically penetrated from the top layer to the bottom layer, so as to cut the through hole structure composed of the first preset through holes into a total of 2*N conductive through holes and the width of the first conductive material plated in each conductive through hole is the preset UPI routing width (the thickness is still the original thickness of the inner copper foil unchanged), and the edges of each conductive through hole do not overlap, so that the first UPI port and the corresponding second UPI port are electrically connected through the first conductive material in the corresponding conductive through hole.

[0101] For details, please refer to Figure 8 , Figure 8 A schematic diagram of the structure of a conductive through hole provided by the present invention, wherein only the top PCB board layer is used as a structural display reference surface, and only the two-dimensional schematic diagram of the structure of the conductive through hole under the reference surface is displayed, and for the convenience of display and explanation, Figure 8 All the traces of the drilling process are displayed. It can be seen that assuming the first target position is determined to be Figure 8 , the four circular structures shown in FIG. 1 (the second target position is located directly below the three-dimensional structure diagram, and the size of the circular structure here is only for display and does not represent the actual size relationship), then N=2, first drill two first preset through holes (in the first preset angle) with a 90-degree angle (first preset angle) to each other, with the central axis coinciding and the same size Figure 8 A1 and A2 are respectively represented in the figure), then, a first conductive material, such as copper, is plated in the first preset through hole A1 and the first preset through hole A2; finally, a second preset through hole with a diameter smaller than the length of the first preset through hole is drilled with the central axis as the central axis, that is, Figure 8 The second preset through hole B in the through hole structure composed of the first preset through hole A1 and the first preset through hole A2 is drilled out, that is, the copper plated in the overlapping part will be drilled out, and four conductive through holes whose edges do not overlap are obtained. For more details, please refer to Fig. 9 As shown, Fig. 9 A schematic diagram of the structure of another conductive through hole provided by the present invention, Fig. 9 Shown in Figure 8 On the basis of, after actually completing the above steps, there are still 4 conductive through-hole parts left, among which, Fig. 9 The solid lines in the figure represent the copper-plated conductive vias that still exist, and the dotted lines represent the areas that have been drilled out and there is no conductive copper at the edges of the dotted lines. And because the UPI signal traces are matched in pairs, Fig. 9 It is shown in the figure that two of the conductive through holes are used for UPI signal transmission, namely, signal transmission holes for UPI_DP0 and UPI_DN0, respectively, and the other two conductive through holes are used as accompanying ground holes for the above-mentioned UPI_DP0 and UPI_DN0, respectively. Please refer to Fig.10 , Fig.10 A schematic diagram of another conductive through hole structure provided by the present invention, corresponding to Fig. 9 , further taking one of the conductive vias as an example, a certain degree of magnification is performed to reflect the details in order to illustrate the width and thickness of the first conductive material in the conductive via: First of all, it should be explained that, Fig.10 The gray part inside the middle ring area is the area where the first conductive material is plated. This is only a simple illustration (i.e., it does not represent the actual structure. The proportion of the conductive through hole between the plated part and the non-plated part must be Fig.10 As shown in ); it can be seen that the thickness of the first conductive material is Fig.10 As shown in the above mark, the thickness will not be changed when cutting with the second preset through hole; the width of the first conductive material refers to the circumference of the annular area, which can be understood as Fig.10 Point P1 in the figure moves along the dotted line (the dotted line may be parallel to the outer contour of the annular part) to Fig.10 The length of point P2 in the figure is equal to the preset UPI line width. It can be understood that since the conductive via is a very small structure in the actual figure, it can be approximately understood as selecting Fig.10 Any point on the straight line where P1 is located (of course it can be the midpoint), along the dotted line, go to Fig.10 The length traveled by any point on the straight line where P2 is located (of course it can be the midpoint) is the circumference of the first conductive material.

[0102] It should be noted that, precisely because the UPI signal routing is matched in pairs, when N=2 and the first preset angle is 90 degrees, a pair of UPI signal routing can be realized; when N=3 and the first preset angle is 60 degrees, only a pair of UPI signal routing can be realized (two conductive through holes are used as signal transmission holes, and the other four conductive through holes are used as accompanying ground holes, which can better ensure the transmission efficiency of the UPI signal); when N=4 and the first preset angle is 30 degrees, two pairs of UPI signal routing can be realized. It can be seen that the value of N can be set according to actual needs.

[0103] The present invention also provides a method for opening a connecting through hole, which is used to open a connecting through hole on the above-mentioned PCB board. The method for opening a connecting through hole comprises:

[0104] Acquire a third target position of the first power port to be installed and a fourth target position of the second power port to be installed;

[0105] Based on the third target position and the fourth target position, M third preset through holes whose central axes coincide with each other and are at a second preset angle to each other are drilled, the third preset through holes vertically penetrate from the top layer to the bottom layer, and M is a positive integer;

[0106] After the second conductive material is electroplated in each third preset through hole, a connecting through hole is obtained, so that the first power port and the corresponding second power port are electrically connected through the second conductive material in the corresponding connecting through hole.

[0107] In the present embodiment, taking into account what is described in the above embodiments and limited by the actual aperture requirements of the current drilling process, a method for opening connecting through holes is provided. Compared with directly drilling through holes with a certain diameter around each first power port, it is easier to operate and can drill through holes of smaller specifications, thereby optimizing the routing hole design of the power signal.

[0108] Specifically, the method also includes but is not limited to being applied to a processor, and then the processor controls the drilling equipment to perform the drilling action to achieve automated drilling, that is, first obtaining the third target position of the first power port to be installed on the top layer, and the fourth target position of the second power port to be installed on the bottom layer, then, based on the third target position and the fourth target position, drill M third preset through holes whose central axes coincide and are at a second preset angle to each other, and the third preset through holes vertically penetrate from the top layer to the bottom layer, and the second preset angle includes but is not limited to 90 degrees and 60 degrees, which are not specifically limited here; after electroplating the second conductive material in each third preset through hole, a connecting through hole is obtained, so that the first power port and the corresponding second power port are electrically connected through the second conductive material in the corresponding connecting through hole.

[0109] For details, please refer to Fig.11 , Fig.11 A schematic diagram of the structure of a connecting through hole provided by the present invention, wherein only the top PCB board layer is used as the structural display reference surface, and only the two-dimensional structural schematic diagram of the connecting through hole under the reference surface is displayed, and for the convenience of display and explanation, Fig.11 All the traces of the drilling process are displayed. It can be seen that assuming the third target position is determined to be Fig.11 , the two circular structures shown in FIG. 1 (the fourth target position is located directly below the three-dimensional structure schematic diagram, and the size of the circular structure here is only for display and does not represent the actual size relationship), then M=2, first drill two third preset through holes (in the middle) that are 90 degrees (the second preset angle) to each other, have the same central axis and are equal in size. Fig.11 Then, the second conductive material, such as copper, is plated in the third preset through hole X1 and the third preset through hole X2. Therefore, since the power signals corresponding to the first power ports at different positions are essentially the same, it is only limited by the packaging of the PCB board that the first power port needs to be led out at different positions. Therefore, the third preset through hole does not need to be cut like the second preset through hole in the conductive through hole, ensuring that there is enough conductive material in the connecting through hole to maximize the flow capacity of the connecting through hole. In addition, please refer to Fig.12 , Fig.12 A schematic diagram of another structure of a connecting through hole provided by the present invention, Fig.12 and Fig.11 Similarly, only the top PCB layer is used as the structural display reference surface, and only the two-dimensional structural schematic diagram of the connecting through holes under the reference surface is displayed. Assuming that the third target position is determined to be Fig.12 As shown in the figure, the three circular structures (the fourth target position is located directly below the three-dimensional structure diagram, and the size of the circular structure here is only for display and does not represent the actual size relationship), it can be seen that M=3, the second preset angle is 60 degrees, Fig.12 The third through hole X3, the third through hole X4 and the third through hole X5 are all snowflake-shaped, and copper is plated in them to obtain connecting through holes.

[0110] The present invention also provides an electronic device, comprising the mainboard as described above.

[0111] For the introduction of the electronic device provided in the present invention, please refer to the above-mentioned embodiment of the main board, which will not be described in detail here.

[0112] It should be noted that the electronic device includes but is not limited to a server, and is not particularly limited here.

[0113] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the embodiments can be referred to each other. Relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements that are not clearly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements limited by the sentence "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.

[0114] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to the function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention. The above description of the disclosed embodiments enables professional and technical personnel in this field to implement or use the present invention. Various modifications to these embodiments will be obvious to professional and technical personnel in this field, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but will conform to the widest range consistent with the principles and novel features disclosed herein.

Claims

1. A motherboard, characterized in that: A multi-layer PCB board and a BGA group, wherein the BGA group includes a first BGA chip arranged on the top layer of the PCB board and a second BGA chip arranged on the bottom layer of the PCB board, and each pin of the first BGA chip and each pin of the second BGA chip are arranged in a one-to-one correspondence; The PCB board includes a plurality of conductive through holes which are spaced apart from each other and vertically penetrate from the top layer to the bottom layer, wherein the conductive through holes are plated with a first conductive material having a thickness equal to that of the inner copper foil of the PCB board and a width equal to a preset UPI trace width; The conductive through hole is used to electrically connect the first UPI port of the first BGA chip and the second UPI port of the second BGA chip placed in a one-to-one correspondence; The first BGA chip also includes a first routing end to be fanned out; the second BGA chip also includes a second routing end to be fanned out; the PCB board also includes a plurality of first sunken grooves spaced apart from each other, the first sunken grooves close to the edge of the first BGA chip are shallower, and the first sunken grooves close to the center of the first BGA chip are deeper; the first sunken grooves are plated with a third conductive material having a thickness equal to that of the inner copper foil, and are used to fan out each of the first routing ends to be fanned out of the first BGA chip through the corresponding first sunken grooves; the PCB board also includes a plurality of second sunken grooves spaced apart from each other, the second sunken grooves close to the edge of the second BGA chip are shallower, and the second sunken grooves close to the center of the second BGA chip are deeper, and the first sunken grooves are not connected to the second sunken grooves; the second sunken grooves are plated with a third conductive material having a thickness equal to that of the inner copper foil, and are used to fan out each of the second routing ends to be fanned out of the second BGA chip through the corresponding second sunken grooves.

2. The mainboard according to claim 1, wherein: The PCB board also includes a connecting through hole, in which a second conductive material is plated, and the connecting through hole vertically penetrates from the top layer to the bottom layer; The connecting through hole is used to electrically connect the first power port of the first BGA chip and the second power port of the second BGA chip which are placed in a one-to-one correspondence.

3. The mainboard according to claim 1, wherein: It also includes a top heat dissipation module arranged on the top layer and a bottom heat dissipation module arranged on the bottom layer; The top-layer heat dissipation module is used to dissipate heat for the first BGA chip; The bottom heat dissipation module is used to dissipate heat for the second BGA chip.

4. The mainboard according to claim 3, characterized in that: The top heat dissipation module and the bottom heat dissipation module are air-cooled radiators or liquid-cooled radiators.

5. The mainboard according to claim 1, wherein: The PCB board is also provided with a plurality of function module groups, each of which includes a first function module provided on the top layer and a second function module provided on the bottom layer, and each pin of the first function module is provided in a one-to-one correspondence with each pin of the second function module; The PCB board also includes a plurality of third sink grooves spaced apart from each other, the third sink grooves are connected to each functional sink groove one by one, and the third sink grooves are plated with the third conductive material having the same thickness as the inner copper foil; the third sink grooves are used to electrically connect the functional fan-out routing end with the target functional end of the corresponding target functional module in combination with the functional sink grooves; Among them, the functional sink is the first sink or the second sink, and when the functional sink is the first sink, the functional routing end to be fanned out is the first routing end to be fanned out and the target functional module is the first functional module; when the functional sink is the second sink, the functional routing end to be fanned out is the second routing end to be fanned out and the target functional module is the second functional module.

6. The mainboard according to claim 1, wherein: The first routing end to be fanned out is a first PCIE routing end or a first CLK routing end or a first storage signal end or a first DDR signal end; Correspondingly, the second routing end to be fanned out is a second PCIE routing end or a second CLK routing end or a second storage signal end or a second DDR signal end.

7. A method for forming a conductive through hole, characterized in that: Used to open the conductive through hole on the PCB board card described in any one of claims 1 to 6, the method for opening the conductive through hole comprises: Acquire a first target position of the first UPI port to be installed and a second target position of the second UPI port to be installed; Based on the first target position and the second target position, drilling N first preset through holes whose central axes coincide with each other and are at first preset angles to each other, wherein the first preset through holes vertically penetrate from the top layer to the bottom layer, and N is an integer not less than 2; Electroplating the first conductive material in each of the first preset through holes with a thickness equal to that of the inner copper foil; With the central axis as the center axis, a second preset through hole with a diameter smaller than the length of the first preset through hole is drilled, and the second preset through hole vertically penetrates from the top layer to the bottom layer, so as to cut the through hole structure composed of the first preset through holes into 2N conductive through holes, and the width of the first conductive material electroplated in each of the conductive through holes is the preset UPI routing width, and the edges of each of the conductive through holes do not overlap, so that the first UPI port and the corresponding second UPI port are electrically connected through the first conductive material in the corresponding conductive through hole.

8. A method for opening a connecting through hole, characterized in that: The method for opening the connecting through hole on the PCB board in claim 2 comprises: Acquire a third target position of the first power port to be installed and a fourth target position of the second power port to be installed; Based on the third target position and the fourth target position, M third preset through holes whose central axes coincide with each other and are at a second preset angle to each other are drilled, wherein the third preset through holes vertically penetrate from the top layer to the bottom layer, and M is a positive integer; The connecting through holes are obtained after the second conductive material is electroplated in each of the third preset through holes, so that the first power port is electrically connected to the corresponding second power port through the second conductive material in the corresponding connecting through holes.

9. An electronic device, characterized in that: Comprising the mainboard as claimed in any one of claims 1 to 6.

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