A programmable logic unit structure

Abstract

The present application discloses a programmable logic unit structure, including: a first lookup table, including a first output terminal; a second lookup table, including a second output terminal; a first multiplexer, whose two input terminals are respectively coupled to the first output terminal and the second output terminal; a second multiplexer, whose two input terminals are respectively coupled to the first output terminal and the output terminal of the first multiplexer; a third multiplexer, whose two input terminals are respectively coupled to the second output terminal and the output terminal of the first multiplexer; a first trigger, whose input terminal is coupled to a fourth multiplexer, whose output terminal is coupled to an input terminal of the third multiplexer; a second trigger, whose input terminal is coupled to a fifth multiplexer, whose output terminal is coupled to an input terminal of the second multiplexer. The present application improves the utilization rate of programmable interconnection resources, and effectively reduces the area occupied by programmable interconnection resources in FPGA chips and the manufacturing cost of FPGAs.

Description

Technical Field

[0001] The present application belongs to the field of programmable logic technology and relates to a programmable logic unit structure. Background Art

[0002] FPGA (Field Programmable Gate Array) is a general-purpose logic circuit, which consists of a programmable logic module (CLM), a programmable interconnect resource (programmable interconnect) and an input / output block (IOB). The programmable interconnect resource is also called a programmable routing network, which occupies most of the area of ​​the FPGA chip and is used to connect several programmable logic modules. The programmable logic module consists of one or more programmable logic units, which are composed of registers and lookup tables (LUTs). The programmable logic unit receives input signals from the programmable routing network and generates output signals to the programmable routing network.

[0003] In traditional FPGA architectures, in order to improve the configuration flexibility between programmable logic units, sufficient interconnection resources are provided between each output port of each programmable logic unit and other programmable logic units. However, in actual operation, the interconnection resources applied to each output port of each programmable logic unit are only a part of the arranged interconnection resources, and most of the interconnection line resources are idle, resulting in a certain amount of waste. In addition, too many interconnection line resources will also affect the signal transmission speed and the power consumption of the FPGA. Summary of the invention

[0004] The purpose of the present application is to provide a programmable logic unit structure to solve the technical problems of low utilization rate of programmable interconnection resources in the existing FPGA architecture and large area occupied in the FPGA.

[0005] To solve the above technical problems, the technical solution of this application is as follows:

[0006] The present application provides a programmable logic unit structure, including:

[0007] a first lookup table including a first plurality of input terminals coupled to the programmable routing network, and a first output terminal;

[0008] a second lookup table comprising a second plurality of input terminals coupled to the programmable routing network, and a second output terminal;

[0009] a first multiplexer, wherein a first input terminal and a second input terminal of the first multiplexer are respectively coupled to the first output terminal and the second output terminal, and a selection terminal of the first multiplexer is coupled to the programmable routing network;

[0010] a second multiplexer, wherein a first input terminal and a second input terminal of the second multiplexer are respectively coupled to the first output terminal and an output terminal of the first multiplexer, and an output terminal of the second multiplexer is a first output terminal of the programmable logic unit structure;

[0011] a third multiplexer, wherein a first input terminal and a second input terminal of the third multiplexer are respectively coupled to the second output terminal and the output terminal of the first multiplexer, and the output terminal of the third multiplexer is a second output terminal of the programmable logic unit structure;

[0012] a first trigger, wherein an input terminal of the first trigger is coupled to an output terminal of a fourth multiplexer, and an output terminal of the first trigger is coupled to a third input terminal of the third multiplexer;

[0013] A first input terminal of the fourth multiplexer is coupled to the programmable routing network;

[0014] a second trigger, wherein an input terminal of the second trigger is coupled to an output terminal of the fifth multiplexer, and an output terminal of the second trigger is coupled to a third input terminal of the second multiplexer;

[0015] A first input terminal of the fifth multiplexer is coupled to the programmable routing network.

[0016] Further, the second input terminal of the fourth multiplexer is coupled to the output terminal of the second multiplexer.

[0017] Furthermore, the programmable logic unit structure also includes that the fifth multiplexer also includes a second input terminal coupled to the output terminal of the third multiplexer.

[0018] Furthermore, the programmable logic unit structure also includes:

[0019] A sixth multiplexer, wherein a first input terminal of the sixth multiplexer is coupled to an output terminal of the fourth multiplexer, and an output terminal of the sixth multiplexer is a third output terminal of the programmable logic unit structure.

[0020] Furthermore, the sixth multiplexer also includes a second input terminal coupled to the output terminal of the first trigger.

[0021] Furthermore, the programmable logic unit structure also includes:

[0022] A seventh multiplexer, wherein a first input terminal of the seventh multiplexer is coupled to an output terminal of the fifth multiplexer, and an output terminal of the seventh multiplexer is a fourth output terminal of the programmable logic unit structure.

[0023] Furthermore, the seventh multiplexer also includes a second input terminal coupled to the output terminal of the second trigger.

[0024] Furthermore, the programmable logic unit structure also includes:

[0025] An eighth multiplexer, wherein the first input terminal and the second input terminal of the eighth multiplexer are both coupled to the programmable routing network, and the second input terminal of the eighth multiplexer is also coupled to the first input terminal of the fourth multiplexer, and the output terminal of the eighth multiplexer is coupled to one input terminal of the first plurality of input terminals.

[0026] Furthermore, the programmable logic unit structure also includes:

[0027] A ninth multiplexer, wherein the first input terminal and the second input terminal of the ninth multiplexer are both coupled to the programmable routing network, and the second input terminal of the ninth multiplexer is also coupled to the selection terminal of the first multiplexer, and the output terminal of the ninth multiplexer is coupled to one of the first plurality of input terminals.

[0028] Furthermore, the programmable logic unit structure also includes:

[0029] A tenth multiplexer, wherein both input terminals of the tenth multiplexer are coupled to the programmable routing network, and the second input terminal of the tenth multiplexer is also coupled to the first input terminal of the fifth multiplexer, and the output terminal of the tenth multiplexer is coupled to one of the second plurality of input terminals.

[0030] Compared with the prior art, the beneficial effects of this application are:

[0031] The present application provides a programmable logic unit structure, which only needs to provide less programmable interconnection resources for each output port of the programmable logic unit to meet the interconnection requirements between the programmable logic units, thereby improving the utilization rate of the programmable interconnection resources and effectively reducing the area occupied by the programmable interconnection resources in the FPGA chip, thereby effectively reducing the cost. Moreover, due to the reduction of programmable interconnection resources, the programmable logic unit structure provided in the embodiment of the present application can also effectively reduce the load of the interconnection line, improve the signal transmission speed of the programmable interconnection resources, and reduce the leakage and power consumption of the FPGA. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 A schematic diagram of a programmable logic unit structure provided in an embodiment of the present application.

[0034] Figure 2 Another schematic diagram of a programmable logic unit structure provided in an embodiment of the present application.

[0035] Figure 3 Another schematic diagram of a programmable logic unit structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] The following is a clear and complete description of the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. It should be clear that the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0037] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein.

[0038] FPGA includes: several programmable logic modules, programmable routing networks (i.e., programmable interconnection line resources), and several input and output modules connected to the programmable routing networks. The programmable logic modules are composed of several programmable logic unit structures and are connected to the programmable routing networks. Among them, the programmable routing network provides input signals to the programmable logic modules. Specifically, the programmable routing network can receive the outputs of some programmable logic modules as inputs of other programmable logic units, or receive the outputs of programmable logic modules as input signals of the programmable logic modules, or receive signals as input signals of the programmable logic modules in other ways. It should be clear that the programmable logic module is composed of several programmable logic units, so the above-mentioned programmable logic module receiving input signals from the programmable routing network means that the programmable logic units in the programmable logic module receive input signals from the programmable routing network.

[0039] The programmable routing network determines the flexibility of configuration between programmable logic units. Therefore, in the traditional FPGA architecture, in order to improve the flexibility of configuration between programmable logic units, sufficient interconnection resources are provided between each output port of each programmable logic unit and other programmable logic units. However, in actual operation, the interconnection resources applied to each output port of each programmable logic unit are only a part of the arranged interconnection resources, and most of the interconnection line resources are idle, resulting in a great waste. In addition, too many interconnection line resources also occupy more FPGA chip area, which will affect the signal transmission speed and FPGA power consumption.

[0040] In order to solve this problem, an embodiment of the present application provides a programmable logic unit structure. Figure 1 - Figure 3 A schematic diagram of a programmable logic unit structure provided in an embodiment of the present application, such as Figure 1 - Figure 3 As shown, the programmable logic unit structure provided in the embodiment of the present application includes two lookup tables, two triggers and multiple multiplexers, specifically including:

[0041] The first lookup table 201 includes a first plurality of input terminals ( I0_0 - I4_0 ) coupled to the programmable routing network, and a first output terminal L5_0 , and the first output terminal L5_0 provides an input signal to the first multiplexer 301 and the second multiplexer 302 , respectively.

[0042] The second lookup table 202 includes a second plurality of input terminals ( I0_1 - I4_1 ) coupled to the programmable routing network, and a second output terminal L5_1 . The first output terminal L5_1 provides an input signal to the first multiplexer 301 and the third multiplexer 303 , respectively.

[0043] It should be clear that in the programmable logic unit structure provided in the embodiment of the present application, the first lookup table 201 and the second lookup table 202 both include five input ports. In fact, if necessary, the lookup table in the embodiment of the present application can also be replaced by a lookup table with other numbers of input ports.

[0044] A first multiplexer 301, wherein the first input terminal and the second input terminal of the first multiplexer 301 are respectively coupled to the first output terminal L5_0 and the second output terminal L5_1, the selection terminal of the first multiplexer 301 is coupled to a programmable routing network to receive a selection signal input by the programmable routing network, and the output terminal of the first multiplexer 301 provides an input signal for the second multiplexer 302 and the third multiplexer 303 respectively.

[0045] The second multiplexer 302, the first input terminal and the second input terminal of the second multiplexer 302 are respectively coupled to the first output terminal L5_0 and the output terminal of the first multiplexer 301, and the output terminal of the second multiplexer 302 is the first output terminal Y0 of the programmable logic unit structure, that is, the output terminal of the second multiplexer 302 provides an output signal for the programmable logic unit structure.

[0046] The third multiplexer 303, the first input terminal and the second input terminal of the third multiplexer 303 are respectively coupled to the second output terminal L5_1 and the output terminal of the first multiplexer 301, and the output terminal of the third multiplexer 303 is the second output terminal Y1 of the programmable logic unit structure, that is, the output terminal of the third multiplexer 303 provides an output signal for the programmable logic unit structure.

[0047] The first trigger 401 has a D input terminal coupled to the output terminal of the fourth multiplexer 304 to receive the input signal provided by the fourth multiplexer 304 , and a Q output terminal of the first trigger 401 is coupled to the third input terminal of the third multiplexer 303 to provide an input signal for the third multiplexer 303 .

[0048] The second flip-flop 402 has a D input terminal coupled to the output terminal of the fifth multiplexer 305 to receive the input signal provided by the fifth multiplexer 305 , and a Q output terminal of the second flip-flop 402 coupled to the third input terminal of the second multiplexer 302 to provide an input signal for the second multiplexer 302 .

[0049] The first input terminal of the fourth multiplexer 304 is coupled to the programmable routing network for directly receiving an input signal provided by the programmable routing network.

[0050] In the programmable logic unit structure provided in the embodiment of the present application, the signal output from the Q output terminal of the first trigger 401 can be used as an input signal of the third multiplexer 303, and is output from the second output terminal Y1 of the programmable logic unit structure after being selected for output by the third multiplexer 303. Similarly, the signal output from the Q output terminal of the second trigger 402 can be used as an input signal of the second multiplexer 302, and is output from the second output terminal Y0 of the programmable logic unit structure after being selected for output by the second multiplexer 302. By realizing flexible configuration of the same output signal inside the programmable logic unit, such as the signal output from the Q output terminal of the first trigger 401 can be configured to be directly output or to be output through the output terminal Y1, part of the functions that require programmable interconnection resources to be realized are replaced by the circuit structure inside the programmable logic unit, thereby saving this part of the programmable interconnection resources.

[0051] In some embodiments, Figure 2 - Figure 3 As shown, in the programmable logic unit structure provided by the embodiment of the present application, the fourth multiplexer 304 also includes a second input terminal coupled to the output terminal of the second multiplexer 302, that is, the first input terminal and the second input terminal of the fourth multiplexer 304 are respectively coupled to the programmable routing network and the output terminal of the second multiplexer 302, the output terminal of the programmable routing network and the output terminal of the second multiplexer 302 respectively provide an input signal for the fourth multiplexer 304 to select the output, and the output terminal of the fourth multiplexer 304 is coupled to the D input terminal of the first trigger 401 so that the first trigger 401 is coupled to the output terminal of the programmable routing network or the second multiplexer 302 via the fourth multiplexer 304.

[0052] It should be clear that when the first trigger 401 is only used to receive the input signal provided by the programmable routing network, the programmable routing network can also be directly coupled to the D input terminal of the first trigger 401. However, when the first trigger 401 can be used to receive the signal output from the output terminal of the second multiplexer 302 in addition to receiving the input signal provided by the programmable routing network, a multiplexer such as the fourth multiplexer 304 can be set to enable the first trigger 401 to select to receive the input signal provided by the programmable routing network or to select to receive the signal output from the output terminal of the second multiplexer 302 according to the selection signal.

[0053] In some embodiments, Figure 2 - Figure 3 As shown, the programmable logic unit structure provided by the embodiment of the present application, the fifth multiplexer 305 also includes a second input terminal coupled to the output terminal of the third multiplexer 303, that is, the first input terminal and the second input terminal of the fifth multiplexer 305 are respectively coupled to the programmable routing network and the output terminal of the third multiplexer 303, the programmable routing network and the output terminal of the third multiplexer 303 respectively provide an input signal for the fifth multiplexer 305 to select the output, and the output terminal of the fifth multiplexer 305 is coupled to the D input terminal of the second trigger 402 so that the second trigger 402 is coupled to the output terminal of the programmable routing network or the third multiplexer 303 via the fifth multiplexer 305.

[0054] It should be clear that when the second trigger 402 is only used to receive the input signal provided by the programmable routing network, the programmable routing network can also be directly coupled to the D input terminal of the second trigger 402. However, when the second trigger 402 can be used to receive the signal output from the output terminal of the third multiplexer 303 in addition to receiving the input signal provided by the programmable routing network, a multiplexer such as the fifth multiplexer 305 can be set to enable the second trigger 402 to select to receive the input signal provided by the programmable routing network or to select to receive the signal output from the output terminal of the third multiplexer 303 according to the selection signal.

[0055] In the programmable logic unit structure provided in the embodiment of the present application, the output signal of the Q output terminal of the first trigger 401 can also be output to the D input terminal of the second trigger 402 through the third multiplexer 303 and the fifth multiplexer 305. Similarly, the output signal of the Q output terminal of the second trigger 402 can also be output to the D input terminal of the first trigger 401 through the second multiplexer 302 and the fourth multiplexer 304, thereby realizing the cascade input from the first trigger 401 to the second trigger 402 and the cascade input from the second trigger 402 to the first trigger 401, further reducing the interconnection resources occupied by each output terminal of the programmable logic unit structure.

[0056] In some embodiments, Figure 3 As shown, the programmable logic unit structure provided in the embodiment of the present application also includes:

[0057] A sixth multiplexer 306, wherein a first input terminal of the sixth multiplexer 306 is coupled to an output terminal of the fourth multiplexer 304, so that an input signal provided by the programmable routing network can also be output to the sixth multiplexer 306 through the fourth multiplexer 304 for direct output, thereby realizing the shortest delay output of the input signal provided by the programmable routing network, and an output terminal of the sixth multiplexer 306 is a third output terminal of the programmable logic unit structure.

[0058] In other embodiments, the sixth multiplexer 306 also includes a second input terminal coupled to the output terminal of the first trigger 401, that is, the first input terminal and the second input terminal of the sixth multiplexer 306 are respectively coupled to the output terminal of the fourth multiplexer 304 and the Q output terminal of the first trigger 401, the output terminal of the fourth multiplexer 304 and the Q output terminal of the first trigger 401 respectively provide an input signal for the sixth multiplexer 306, and the output terminal of the sixth multiplexer 306 is the third output terminal of the programmable logic unit structure and provides an output signal for the programmable logic unit structure.

[0059] In some embodiments, Figure 3As shown, the programmable logic unit structure provided in the embodiment of the present application also includes:

[0060] The seventh multiplexer 307, the first input end of the seventh multiplexer 307 is coupled to the output end of the fifth multiplexer 305, so that the input signal provided by the programmable routing network can also be output to the seventh multiplexer 307 directly through the fifth multiplexer 305, thereby realizing the shortest delay output of the input signal provided by the programmable routing network, and the output end of the seventh multiplexer 307 is the third output end of the programmable logic unit structure.

[0061] In other embodiments, the seventh multiplexer 307 also includes a second input terminal coupled to the output terminal of the second trigger 402, that is, the first input terminal and the second input terminal of the seventh multiplexer 307 are respectively coupled to the output terminal of the fifth multiplexer 305 and the Q output terminal of the second trigger 402, the output terminal of the fifth multiplexer 305 and the Q output terminal of the first trigger 402 respectively provide an input signal for the seventh multiplexer 307, and the output terminal of the seventh multiplexer 307 is the fourth output terminal of the programmable logic unit structure, which provides an output signal for the programmable logic unit structure.

[0062] In the programmable logic unit structure provided in the embodiment of the present application, the input signal provided by the programmable routing network can be directly output through the sixth multiplexer 306 in addition to being output through the first trigger 401, and the output signal of the Q output terminal of the first trigger 401 can be further output from the output terminal Q1 through the third multiplexer 303, the fifth multiplexer 305 and the seventh multiplexer 307. In addition to being output through the second trigger 402, another input signal provided by the programmable routing network can be directly output through the seventh multiplexer, and the output signal of the Q output terminal of the second trigger 402 can be further output from the output terminal Q0 through the second multiplexer 302, the fourth multiplexer 304 and the sixth multiplexer 306, which further reduces the interconnection resources occupied by each output terminal of the programmable logic unit structure.

[0063] In some embodiments, Figure 1 - Figure 3 As shown, the programmable logic unit structure provided in the embodiment of the present application also includes:

[0064] The eighth multiplexer 308, the first input terminal and the second input terminal of the eighth multiplexer 308 are both coupled to the programmable routing network, and the second input terminal of the eighth multiplexer 308 is also coupled to the first input terminal of the fourth multiplexer 304, and the output terminal of the eighth multiplexer 308 is coupled to one of the first multiple input terminals, providing an input signal for the first lookup table 201.

[0065] In some embodiments, Figure 1 - Figure 3 As shown, the programmable logic unit structure provided in the embodiment of the present application also includes:

[0066] The ninth multiplexer 309, the first input terminal and the second input terminal of the ninth multiplexer 309 are both coupled to the programmable routing network, and the second input terminal of the ninth multiplexer 309 is also coupled to the selection terminal of the first multiplexer 301, and the output terminal of the ninth multiplexer 309 is coupled to one of the first multiple input terminals, providing an input signal for the first lookup table 201.

[0067] In some embodiments, Figure 1 - Figure 3 As shown, the programmable logic unit structure provided in the embodiment of the present application also includes:

[0068] The tenth multiplexer 310, both input terminals of the tenth multiplexer 310 are coupled to the programmable routing network, and the second input terminal of the tenth multiplexer 310 is also coupled to the first input terminal of the fifth multiplexer 305, and the output terminal of the tenth multiplexer 309 is coupled to one of the second plurality of input terminals, providing an input signal for the second lookup table 202.

[0069] In the embodiment of the present application, the input signals of the first lookup table 201 and the second lookup table 202 are obtained from the programmable routing network. Furthermore, the input signals of the first lookup table 201 and the second lookup table 202 are expanded by setting the eighth multiplexer, the ninth multiplexer and the tenth multiplexer, that is, the input signals of the programmable logic unit are further expanded. Figure 1 - Figure 3 The provided programmable logic unit structure is taken as an example to provide up to eight input signals for a six-input lookup table.

[0070] It should be clear that the second multiplexer 302 and the third multiplexer 303 of the programmable logic unit structure provided in the embodiment of the present application include at least three input terminals, and the fourth multiplexer 303 and the fifth multiplexer 305 include at least two input terminals. In fact, the multiplexers appearing in the programmable logic unit structure provided in the embodiment of the present application include but are not limited to the second multiplexer 302, the third multiplexer 303, the fourth multiplexer 304 and the fifth multiplexer 305. The selection of a three-to-one multiplexer and a two-to-one multiplexer is only used to illustrate the connection relationship of the programmable logic unit. As long as the input and output logic functions are consistent with the programmable logic unit structure provided in the embodiment of the present application, they all belong to the programmable logic unit provided in the embodiment of the present application.

[0071] In addition, if Figure 1 - Figure 3 As shown, the programmable logic unit structure provided in the embodiment of the present application does not illustrate the selection end of the second to tenth multiplexers. In fact, the selection ends of the second to tenth multiplexers provided in the embodiment of the present application are coupled to the configuration memory of the FPGA. The configuration memory is used to provide selection signals for the selection ends of the second multiplexer and the third multiplexer. In fact, it is well known that the multiplexers appear in the circuit principles in the field of integrated circuits. If the connection relationship of the selection end of the multiplexer is not directly indicated, it means that the multiplexer is a configuration multiplexer, and the selection signal received by the selection end is a constant stored in the configuration memory. The configuration memory loads configuration data from the ROM when the FPGA is powered on. The configuration memory is usually not displayed in the circuit principle, that is, except for the first multiplexer 301 in the embodiment of the present application, the selection end of each multiplexer is coupled to the configuration memory.

[0072] The programmable logic unit structure provided in the embodiment of the present application only needs to provide less programmable interconnection resources for each output port to meet the interconnection requirements between programmable logic units, thereby improving the utilization rate of programmable interconnection resources and effectively reducing the area occupied by programmable interconnection resources in the FPGA chip, thereby effectively reducing the cost. Moreover, due to the reduction of programmable interconnection resources, the programmable logic unit structure provided in the embodiment of the present application can also effectively reduce the load of the interconnection line, improve the signal transmission speed of the programmable interconnection resources, and reduce the leakage and power consumption of the FPGA.

[0073] For example, the configurable functions of the programmable logic unit structure provided in the embodiment of the present application are as follows:

[0074] Function 1: When the output signal of the first lookup table 201 and the second lookup table 202 is output through the output end of the first multiplexer 301, the configurable output ports of the output signal include output port Y0, output port Y1, output port Q0, and output port Q1;

[0075] When the output port Y0 is configured, the output signal is output through the output terminal of the second multiplexer 302;

[0076] When the output port Q0 is configured, the output signal is output to the fourth multiplexer 304 through the second multiplexer 302 , and the first trigger 401 is ignored. Then, the output signal is further output to the sixth multiplexer 306 and output through the output terminal of the sixth multiplexer 306 .

[0077] Similar to configuring the output port Y0, when configuring the output port Y1, the output signal is output through the output terminal of the third multiplexer 303;

[0078] When the output port Q1 is configured, the output signal is output to the fifth multiplexer 305 through the third multiplexer 303 , and the first trigger 402 is ignored. Then, the output signal is further output to the seventh multiplexer 307 and output through the output terminal of the seventh multiplexer 307 .

[0079] Function 2: When the output signals of the first lookup table 201 and the second lookup table 202 are output through the first output terminal and the second output terminal respectively, each output signal can realize flexible configuration output of two ports.

[0080] The output signal of the first lookup table 201 can be configured to be output at the output terminal Q0 and the output terminal Y0. Specifically,

[0081] The output signal of the first lookup table 201 is directly outputted through the output terminal of the second multiplexer 302 or is outputted to the fourth multiplexer 304 through the second multiplexer 302 , ignoring the first trigger 401 , and is further outputted to the sixth multiplexer 306 and outputted through the output terminal of the sixth multiplexer 306 .

[0082] The output signal of the second lookup table 202 can be configured to be output at the output terminal Q1 and the output terminal Y1. Specifically,

[0083] The output signal of the second lookup table 202 is directly outputted through the output terminal of the third multiplexer 303 or is outputted to the fifth multiplexer 305 through the third multiplexer 303 , ignoring the second trigger 402 , and is further outputted to the seventh multiplexer 307 through the output terminal of the seventh multiplexer 307 .

[0084] Function 3: Both the first trigger 401 and the second trigger 402 can realize flexible configuration output of two ports. The first trigger 401 outputs configurable output terminals Q0 and Y1. Specifically:

[0085] The output signal of the first flip-flop 401 is directly output through the sixth multiplexer 306;

[0086] Or the output signal of the first trigger 401 is output to the third multiplexer 303 and output through the output terminal of the third multiplexer 303;

[0087] Furthermore, the output signal of the first trigger 401 can also be configured as output Q1, specifically:

[0088] The output signal of the first trigger 401 is output to the third multiplexer 303 , further output to the fifth multiplexer 305 via the third multiplexer 303 , and finally output through the output terminal of the seventh multiplexer 307 .

[0089] The output of the second trigger 402 can be configured with output terminal Q1, output terminal Y0 and output terminal Q0 in the same way. The specific process is mirrored with the first trigger 401. The output signal of the second trigger 402 is output to the second multiplexer 302, further output to the fourth multiplexer 304 through the second multiplexer 302, and finally output through the output terminal of the sixth multiplexer 306.

[0090] Function 4: Implement flexible trigger cascading function inside the programmable logic unit to further reduce the use of external interconnection resources;

[0091] When the first flip-flop 401 and the second flip-flop 402 are cascaded: the output signal of the first flip-flop 401 is output to the second flip-flop 402 through the third multiplexer 303 and the fifth multiplexer 305;

[0092] When the second flip-flop 402 and the first flip-flop 401 are cascaded, the output signal of the second flip-flop 402 is output to the first flip-flop 401 through the second multiplexer 302 and the fourth multiplexer 304 .

[0093] The above contents are further detailed descriptions of the present application in combination with specific implementation methods, and it cannot be determined that the specific implementation of the present application is limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, several simple deductions or substitutions can be made without departing from the concept of the present application, which should be regarded as the protection scope of the present application.

Claims

1. A programmable logic unit structure, characterized in that: include: a first lookup table including a first plurality of input terminals coupled to the programmable routing network, and a first output terminal; a second lookup table comprising a second plurality of input terminals coupled to the programmable routing network, and a second output terminal; a first multiplexer, wherein a first input terminal and a second input terminal of the first multiplexer are respectively coupled to the first output terminal and the second output terminal, and a selection terminal of the first multiplexer is coupled to the programmable routing network; a second multiplexer, wherein a first input terminal and a second input terminal of the second multiplexer are respectively coupled to the first output terminal and an output terminal of the first multiplexer, and an output terminal of the second multiplexer is a first output terminal of the programmable logic unit structure; a third multiplexer, wherein a first input terminal and a second input terminal of the third multiplexer are respectively coupled to the second output terminal and the output terminal of the first multiplexer, and the output terminal of the third multiplexer is a second output terminal of the programmable logic unit structure; a first trigger, wherein an input terminal of the first trigger is coupled to an output terminal of a fourth multiplexer, and an output terminal of the first trigger is coupled to a third input terminal of the third multiplexer, and is used for directly outputting an output signal from the fourth multiplexer, or allowing the output signal from the fourth multiplexer to be output via the third multiplexer; A first input terminal of the fourth multiplexer is coupled to the programmable routing network; a second trigger, wherein an input terminal of the second trigger is coupled to an output terminal of the fifth multiplexer, and an output terminal of the second trigger is coupled to a third input terminal of the second multiplexer, and is used for directly outputting an output signal from the fifth multiplexer, or allowing the output signal from the fifth multiplexer to be output via the second multiplexer; A first input terminal of the fifth multiplexer is coupled to the programmable routing network.

2. The programmable logic unit structure according to claim 1, characterized in that: The fourth multiplexer also includes a second input terminal coupled to the output terminal of the second multiplexer.

3. The programmable logic unit structure according to claim 1, characterized in that: The fifth multiplexer also includes a second input terminal coupled to the output terminal of the third multiplexer.

4. The programmable logic unit structure according to claim 1, characterized in that: Also includes: A sixth multiplexer, wherein a first input terminal of the sixth multiplexer is coupled to an output terminal of the fourth multiplexer, and an output terminal of the sixth multiplexer is a third output terminal of the programmable logic unit structure.

5. The programmable logic unit structure according to claim 4, characterized in that: The sixth multiplexer also includes a second input terminal coupled to the output terminal of the first flip-flop.

6. The programmable logic unit structure according to claim 1, characterized in that: Also includes: A seventh multiplexer, wherein a first input terminal of the seventh multiplexer is coupled to an output terminal of the fifth multiplexer, and an output terminal of the seventh multiplexer is a fourth output terminal of the programmable logic unit structure.

7. The programmable logic unit structure according to claim 6, characterized in that: The seventh multiplexer also includes a second input terminal coupled to the output terminal of the second flip-flop.

8. The programmable logic unit structure according to claim 1, characterized in that: Also includes: An eighth multiplexer, wherein the first input terminal and the second input terminal of the eighth multiplexer are both coupled to the programmable routing network, and the second input terminal of the eighth multiplexer is also coupled to the first input terminal of the fourth multiplexer, and the output terminal of the eighth multiplexer is coupled to one input terminal of the first plurality of input terminals.

9. The programmable logic unit structure according to claim 1, characterized in that: Also includes: A ninth multiplexer, wherein the first input terminal and the second input terminal of the ninth multiplexer are both coupled to the programmable routing network, and the second input terminal of the ninth multiplexer is also coupled to the selection terminal of the first multiplexer, and the output terminal of the ninth multiplexer is coupled to one of the first plurality of input terminals.

10. The programmable logic unit structure according to claim 1, characterized in that: Also includes: A tenth multiplexer, wherein both input terminals of the tenth multiplexer are coupled to the programmable routing network, and the second input terminal of the tenth multiplexer is also coupled to the first input terminal of the fifth multiplexer, and the output terminal of the tenth multiplexer is coupled to one of the second plurality of input terminals.

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