Embedded software models for devices, battery management system controllers and vehicles

Abstract

The present disclosure relates to an embedded software model device, a battery management system controller and a vehicle, and relates to the technical field of software model design. The model architecture includes: a signal filtering unit and at least one functional unit connected to the signal filtering unit; the signal filtering unit is used to receive an input signal, detect the validity of the input signal, and output validity flag information based on each input signal; the functional unit is used to execute a preset calculation logic according to the validity flag information and the input signal.

Description

Technical Field

[0001] The present application relates to the technical field of software model design, and more specifically, to an embedded software model architecture, a battery management system controller and a vehicle. Background Art

[0002] The embedded software model architecture is used in many scenarios because of its strong model visualization, easy maintenance, automatic code generation, and suitability for writing complex logic.

[0003] The current embedded software model architecture mainly includes several units, each unit is connected to the outside through signals, and each unit executes different logics. When each unit receives an input signal, it directly uses the value of the input signal for logical judgment and numerical calculation, without the function of abnormal identification and processing of the input signal. However, the validity of the input signal plays an important role in the correctness and stability of the implementation of each functional logic of the model architecture. Directly using the input signal for logical judgment and numerical calculation will lead to abnormal logic and numerical output, which will directly affect the quality of the software. Summary of the invention

[0004] One purpose of the present application is to provide a new technical solution for an embedded software model architecture, a battery management system controller and a vehicle.

[0005] According to a first aspect of the present disclosure, there is provided an embedded software model architecture, characterized in that the model architecture comprises: a signal filtering unit and at least one functional unit connected to the signal filtering unit;

[0006] The signal filtering unit is used to receive input signals, detect the validity of the input signals, and output validity flag information based on each input signal;

[0007] The functional unit is used to execute a preset calculation logic according to the validity mark information and the input signal.

[0008] Optionally, the signal filtering unit detects the validity of the input signal and outputs validity flag information based on each input signal, including:

[0009] Detecting whether the value of the input signal is a valid value;

[0010] Detecting whether the value range of the input signal is within a first preset range;

[0011] Detecting whether the value change of the input signal is within a second preset range;

[0012] According to at least one of the above detection methods, validity flag information based on each input signal is output.

[0013] Optionally, the detecting whether the value of the input signal is a valid value and outputting validity flag information based on each input signal includes:

[0014] Detecting whether the value of the input signal is a valid value according to the value attribute of the input signal;

[0015] When the value of the input signal is a valid value, outputting validity flag information indicating that the input signal is valid;

[0016] When the value of the input signal is invalid, validity flag information indicating that the input signal is invalid is output.

[0017] Optionally, the detecting whether the numerical range of the input signal is within a first preset range and outputting validity flag information based on each input signal includes:

[0018] When the value range of the input signal is within a first preset range, outputting validity mark information indicating that the input signal is valid;

[0019] When the value range of the input signal is not within the first preset range, validity flag information indicating that the input signal is invalid is output.

[0020] Optionally, the detecting whether the value variation of the input signal is within a second preset range and outputting validity flag information based on each input signal includes:

[0021] When the value variation of the input signal is within a second preset range, outputting validity mark information indicating that the input signal is valid;

[0022] When the value variation of the input signal is not within the second preset range, validity flag information indicating that the input signal is invalid is output.

[0023] Optionally, the functional unit includes at least one group of a trigger unit and a logic unit, and the trigger unit is connected to the logic unit;

[0024] The trigger unit is used to receive the validity flag information output by the signal filtering unit, and output the enable flag information according to the validity flag information;

[0025] The logic unit is used to execute preset calculation logic according to the enable flag information and / or the input signal and its validity flag information.

[0026] Optionally, the trigger unit outputs enable flag information according to the validity flag information, including:

[0027] When the validity flag information of all the input signals is valid, the output enable flag information is the first signal;

[0028] In the case that the validity flag information of any of the input signals is invalid, the output enable flag information is the second signal.

[0029] Optionally, the logic unit is used to execute a preset calculation logic according to the enable flag information and / or the input signal and its validity flag information, including:

[0030] In the case where the calculation logic preset by the logic unit is numerical calculation, the preset calculation logic is executed according to the input signal and its validity flag information;

[0031] In the case where the calculation logic preset by the logic unit is non-numerical calculation, the preset calculation logic is executed according to the enable flag information, the input signal and its validity flag information.

[0032] Optionally, when the calculation logic preset by the logic unit is numerical calculation, executing the preset calculation logic according to the input signal and its validity flag information includes:

[0033] When the validity flag information of the input signal is valid, executing a preset calculation logic according to the current value of the input signal;

[0034] In the case that the validity flag information of the input signal is invalid, the preset calculation logic is executed according to the historical valid value of the input signal instead of the current value.

[0035] Optionally, when the calculation logic preset by the logic unit is non-numerical calculation, executing the preset calculation logic according to the enable flag information, the input signal and its validity flag information includes:

[0036] When the enable flag information is a first signal, the logic unit is in a trigger state and executes a preset calculation logic according to a current value of the input signal;

[0037] When the enable flag information is a second signal, the logic unit is in a non-trigger state.

[0038] According to the second aspect of the present disclosure, a battery management system controller is also provided, which includes a control chip and an embedded software model architecture set on the control chip, and the embedded software model architecture is any embedded software model architecture described in the first aspect.

[0039] According to a third aspect of the present disclosure, a vehicle is also provided, comprising the battery management system controller described in the second aspect.

[0040] One beneficial effect of the present application is that the model architecture of the present embodiment includes a signal filtering unit and at least one functional unit connected to the signal filtering unit; the signal filtering unit receives the input signal, detects the validity of the input signal, and outputs validity flag information based on each input signal, thereby identifying abnormalities for each numerical input signal, providing a data validity source for subsequent functional units to perform logical calculations, and then the functional units execute preset calculation logic according to the validity flag information and the input signal, thereby improving the robustness of the model and software and ensuring the quality of the model and software.

[0041] Other features and advantages of the embodiments of the present disclosure will become apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the embodiments of the present disclosure.

[0043] Figure 1 is an architecture diagram of an embedded software model architecture provided by this embodiment;

[0044] Figure 2 is a logic flow chart of the signal filtering unit provided in this embodiment;

[0045] Figure 3 is an architectural diagram of the functional units provided in this embodiment;

[0046] Figure 4 is a logic flow chart of a trigger unit provided in an embodiment;

[0047] Figure 5 is a logic block diagram of the operation when the logic unit provided in this embodiment performs numerical operations;

[0048] Figure 6 is a logic block diagram of the operation when the logic unit provided in this embodiment performs non-numerical operations;

[0049] Figure 7 is a schematic block diagram of the structure of the battery management system controller provided in this embodiment;

[0050] Figure 8 It is a schematic structural block diagram of the vehicle provided in this embodiment. DETAILED DESCRIPTION

[0051] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless otherwise specifically stated.

[0052] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

[0053] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0054] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0055] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0056] It should be noted that all actions of acquiring signals, information or data in this application are carried out in compliance with the relevant data protection laws and policies of the country where they are located, and with the authorization given by the owner of the corresponding device.

[0057] One application scenario of the embodiments of the present disclosure is the scenario of software model development.

[0058] Embedded software model development in the automotive field increasingly adopts model design to meet the growing functional requirements. Compared with handwritten code, the model has strong visualization, easy maintenance, and can automatically generate code, which is suitable for writing complex logic.

[0059] The model architecture divides different functions by setting up different areas and sections, and then builds logical models and fills in codes in different areas, ultimately achieving the effective operation of the entire model function. Subsequent model maintenance, migration and expansion can be completed according to the clear instructions of the architecture. A good model architecture can make maintenance work more efficient.

[0060] The existing model architecture is generally divided into several units, which are connected to each other and to the outside through signals. The functions of the units are independent, and each unit executes different calculation logic. The input signal received by the model is used to implement the functional logic of the model, and its effectiveness plays an important role in the correctness and stability of the function. If the input signal is valid, it is considered normal and can directly participate in the subsequent logic implementation; otherwise, if the invalid signal participates in the logic implementation, it will cause deviations in the output results, thereby affecting the overall function of the model. However, the existing model architecture does not have the function of identifying and processing abnormal input signals.

[0061] Based on this, this embodiment proposes an embedded software model architecture, adds a signal filtering unit in the model to detect the valid rows of the input signal, and outputs validity flag information based on each input signal to facilitate the logical calculation of the functional unit, and adds a trigger unit and a logic unit inside the functional unit to handle abnormal situations of the input signal, complete the logical error correction of the entire model, and improve the robustness and stability of the model and software.

[0062] Figure 1 For an architecture diagram of an embedded software model architecture provided in this embodiment, refer to Figure 1 The model architecture includes: a signal filtering unit 101 and at least one functional unit 102 connected to the signal filtering unit 101. Each functional unit can communicate with each other to complete the mixed logic calculation of the model architecture.

[0063] In this embodiment, the signal filtering unit 101 is used to receive input signals, detect the validity of the input signals, and output validity flag information based on each input signal.

[0064] In one example, the input signal of the embedded software model may include an environmental sampling signal, a single-chip sampling signal, and the output value of other model algorithms. Among them, the environmental sampling signal may be a signal value such as temperature, voltage, current, communication value, etc. collected by the controller; the single-chip sampling signal may be a signal value such as the clock and storage signal of the controller sampling its own circuit. In other words, the input signal of this embodiment is a numerical signal with an accurate numerical value.

[0065] In this embodiment, the output value of the embedded software model is a logic value or a signal value obtained by the functional unit according to the input signal and the preset calculation logic of the functional unit.

[0066] In this embodiment, the signal filtering unit may detect the validity of the input signal by at least one of the following three methods:

[0067] A. Detect whether the value of the input signal is a valid value;

[0068] B. Detecting whether the numerical range of the input signal is within a first preset range;

[0069] C. Detect whether the value change of the input signal is within a second preset range.

[0070] Specifically, one or any two of the detection modes A, B, and C, or a combination of the three detection modes may be selected according to the type of the input signal.

[0071] The signal filtering unit of this embodiment outputs validity flag information based on each input signal by detecting whether the value of the input signal is a valid value, including: detecting whether the value of the input signal is a valid value according to the numerical attribute of the input signal; when the value of the input signal is a valid value, outputting validity flag information indicating that the input signal is valid; when the value of the input signal is invalid, outputting validity flag information indicating that the input signal is invalid.

[0072] Figure 2 For the logic flow chart of the signal filtering unit, refer to Figure 2 The signal filtering unit detects whether the input signal is valid. When the value of the input signal is a valid value, the output validity flag information representing the validity of the input signal is True; when the value of the input signal is invalid, the output validity flag information representing the invalidity of the input signal is False.

[0073] It can be understood that when the input signal is an environmental sampling signal and a single-chip microcomputer sampling signal, it is collected through a sampling chip and will have its own valid value, that is, the numerical attribute of the input signal has its own validity. Therefore, for this type of signal, the numerical attribute of the input signal can be used to detect whether the numerical value of the input signal is a valid value. For example, when the input signal is 1, it means that the input signal is valid, and the validity flag information True is output, indicating that the input signal is valid. If the input signal is 0, the validity flag False is output, indicating that the input signal is invalid.

[0074] In this embodiment, the signal filtering unit detects whether the numerical range of the input signal is within a first preset range, and outputs validity flag information based on each input signal, including: when the numerical range of the input signal is within the first preset range, outputting validity flag information indicating that the input signal is valid; when the numerical range of the input signal is not within the first preset range, outputting validity flag information indicating that the input signal is invalid.

[0075] In this embodiment, the signal filtering unit detects whether the numerical change of the input signal is within a second preset range, and outputs validity flag information based on each input signal, including: when the numerical change of the input signal is within the second preset range, outputting validity flag information indicating that the input signal is valid; when the numerical change of the input signal is not within the second preset range, outputting validity flag information indicating that the input signal is invalid.

[0076] In this embodiment, the validity flag information indicating that the input signal is valid may be True or 1, and the validity flag information indicating that the input signal is invalid may be False or 0.

[0077] The signal filtering unit of this embodiment receives input signals, performs validity detection on the numerical signals, uses an exception recognition processing algorithm to determine whether the signal is valid, generates validity flag information, and outputs it to the functional unit. In this way, each numerical input signal can be processed through exception recognition to provide a data validity source for subsequent functional units to perform logical calculations.

[0078] The functional unit of this embodiment is used to execute the preset calculation logic according to the validity mark information and the input signal. In this embodiment, the functional unit includes multiple functional units, each of which has its own preset calculation logic, and can realize the user preset function.

[0079] Figure 3 This is the architecture diagram of the functional unit in this embodiment, refer to Figure 3 Each functional unit 102 includes at least one group of trigger units 1021 and logic units 1022. The trigger unit 1021 is connected to the logic unit 1022. The trigger unit 1021 is used to trigger the logic unit 1022 to execute the preset calculation logic to achieve the preset function. Each logic unit has its own preset calculation logic.

[0080] In this embodiment, the trigger unit 1021 is used to receive the validity flag information output by the signal filtering unit, and output the enable flag information according to the validity flag information.

[0081] Specifically, refer to Figure 4 The trigger unit outputs the enable flag information according to the validity flag information, including: when the validity flag information of all input signals is valid, the output enable flag information is a first signal, and the first signal represents an enable signal trigger signal, for example, the enable signal is 1.

[0082] When the validity flag information of any input signal is invalid, the output enable flag information is a second signal, and the second signal indicates that the enable signal does not trigger the signal, for example, the enable signal is 0.

[0083] That is to say, the trigger signal generates the first signal only when all input signals are valid, and the trigger signal generates the second signal when the validity flag information of any input signal indicates that the input signal is invalid.

[0084] The logic unit of this embodiment has two calculation modes, one is pure numerical calculation, that is, the calculation logic preset by the logic unit is numerical calculation, and the other is non-numerical calculation, that is, the calculation logic preset by the logic unit is non-numerical calculation, and the non-numerical calculation can be conditional judgment, for example, a is greater than b.

[0085] The logic unit 1022 of this embodiment may be configured to execute a preset calculation logic according to the enable flag information and / or the input signal and its validity flag information.

[0086] It is understandable that when the logic unit performs different types of operations, its triggering logic is different. Therefore, this embodiment divides the operation of the logic unit into two cases.

[0087] Figure 5 For the logic block diagram of the logic unit performing numerical operations, refer to Figure 5 In this embodiment, when the calculation logic preset by the logic unit is numerical calculation, the preset calculation logic is executed according to the input signal and its validity flag information.

[0088] It should be noted that the logic unit of this embodiment has an error correction function, and can obtain a valid value when the validity flag information of the input signal indicates that the input signal is invalid, and execute a preset calculation logic according to the valid value.

[0089] Specifically, when the validity flag information of the input signal is valid, the preset calculation logic is executed according to the current value of the input signal, that is, the current input signal is a valid value, and calculation can be performed directly based on the input signal.

[0090] When the validity flag information of the input signal is invalid, the preset calculation logic is executed according to the historical valid value of the input signal instead of the current value.

[0091] It can be understood that the input signal of the embedded model can be periodic, that is, the same type of input signal can be transmitted to the embedded model in cycles, and the deviation of the numerical value is generally not large. Therefore, when the input signal in the current cycle is invalid, the historical valid value of the previous cycle of the input signal of this type can be used to replace the current value. Since the historical valid value of the previous cycle is valid, the error rate of the output value calculated by the logic unit can be reduced, thereby achieving the effect of logic error correction.

[0092] Figure 6For the logic block diagram of the logic unit performing non-numeric operations, refer to Figure 6 In this embodiment, when the calculation logic preset by the logic unit is non-numerical calculation, the preset calculation logic is executed according to the enable flag information, the input signal and its validity flag information.

[0093] Specifically, when the enable flag information is the first signal, that is, when all input signals are valid, the logic unit is in a triggered state, and the logic unit executes the preset calculation logic according to the current value of the input signal, that is, the logic unit operates normally.

[0094] Since the logic unit performs non-numeric operations which have a greater impact on the model, when the enable flag information is the second signal, the logic unit is in a non-triggered state. That is to say, when the logic unit performs non-numeric operations, if the enable flag information is the second signal, for example, the enable flag signal is 0, the logic unit is not triggered and the logic unit does not execute the preset calculation logic.

[0095] In this embodiment, a trigger unit is matched for each logic unit, enable flag information is generated by the trigger unit, and the preset calculation logic is executed according to the enable flag information, the input signal and the validity flag information of the input signal. The logic unit can replace the numerical value of the input signal when the validity flag information of the input signal is invalid, or is in a non-trigger state, which can achieve the effect of logical error correction, thereby improving the robustness of the model and software and ensuring the quality of the model and software.

[0096] Figure 7 The battery management system controller 700 is a schematic block diagram of the structure of a battery management system controller provided in this embodiment. The battery management system controller 700 includes a control chip 701 and an embedded software model architecture 702 arranged on the control chip. The embedded software model architecture 702 is Figure 1 or Figure 3 The embedded software model architecture shown in the figure. The specific structure and function of each module are described in the above embodiments, and will not be repeated here to avoid repetition.

[0097] A battery management system controller provided in this embodiment can generate enable flag information through a trigger unit, and execute preset calculation logic according to the enable flag information, the input signal and the validity flag information of the input signal. The logic unit can replace the numerical value of the input signal when the validity flag information of the input signal is invalid, or is in a non-trigger state, which can achieve the effect of logical error correction, thereby improving the control effect of the battery management system controller.

[0098] Figure 8This is a schematic block diagram of the structure of a vehicle provided in this embodiment. The vehicle 800 includes the battery management system controller 700 of the above embodiment.

[0099] The battery management system controller 700 includes a control chip 701 and an embedded software model architecture 702 arranged on the control chip. The embedded software model architecture 702 is Figure 1 or Figure 3 The embedded software model architecture is shown.

[0100] Embedded software development in the vehicle field is increasingly using model design to meet the growing functional requirements. It can be seen that the vehicle 700 using the battery management system controller 700 of this embodiment can receive input signals through the signal filtering unit due to the embedded software model architecture 702 in the battery management system controller 700, and perform validity detection on the numerical signals therein, and use an abnormality recognition processing algorithm to determine whether the signal is valid, and generate validity flag information, output to the functional unit, and then execute the preset calculation logic according to the validity flag information and the input signal through the functional unit. In this way, each numerical input signal can be processed through abnormality recognition to achieve the effect of logical error correction, thereby improving the safety of the vehicle.

[0101] The present invention may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present invention.

[0102] A computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above. More specific examples (a non-exhaustive list) of computer-readable storage media include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove on which instructions are stored, and any suitable combination of the above. The computer-readable storage medium used herein is not to be interpreted as a transient signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through a wire.

[0103] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0104] The computer program instructions for performing the operation of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer, partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect through the Internet). In some embodiments, by using the state information of the computer-readable program instructions to personalize an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), the electronic circuit may execute the computer-readable program instructions, thereby implementing various aspects of the present invention.

[0105] Various aspects of the present invention are described herein with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to embodiments of the present invention. It should be understood that each box of the flowchart and / or block diagram and the combination of the boxes in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0106] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0107] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0108] The flow charts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the systems, methods and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flow chart or block diagram can represent a part of a module, a program segment or an instruction, and a part of the module, a program segment or an instruction contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions. It is well known to those skilled in the art that it is equivalent to implement it by hardware, implement it by software, and implement it by combining software and hardware.

[0109] Embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the marketplace, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein. The scope of the present invention is defined by the appended claims.

Claims

1. An embedded software model device, characterized in that: The model device comprises: a signal filtering unit and at least one functional unit connected to the signal filtering unit; The signal filtering unit is used to receive input signals, detect the validity of the input signals, and output validity flag information based on each input signal. The input signals include environmental sampling signals, single-chip microcomputer adopted signals and output values ​​of other model algorithms. The input signals are numerical signals with accurate numerical values. The functional unit is used to execute a preset calculation logic according to the validity flag information and the input signal, Wherein, the functional unit includes at least one group of trigger units and logic units, and the trigger units are connected to the logic units; The trigger unit is used to receive the validity flag information output by the signal filtering unit, and when the validity flag information of all the input signals is valid, the output enable flag information is a first signal; when the validity flag information of any input signal is invalid, the output enable flag information is a second signal; In the case where the calculation logic preset by the logic unit is numerical calculation, the preset calculation logic is executed according to the input signal and its validity flag information; In the case where the calculation logic preset by the logic unit is non-numerical calculation, when the enable flag information is a first signal, the logic unit is in a triggered state, and executes the preset calculation logic according to the current value of the input signal; when the enable flag information is a second signal, the logic unit is in a non-triggered state, The signal filtering unit detects the validity of the input signal and outputs validity flag information based on each input signal, including: Detecting whether the value of the input signal is a valid value; Detecting whether the value range of the input signal is within a first preset range; Detecting whether the value change of the input signal is within a second preset range; According to at least one of the above detection methods, validity flag information based on each input signal is output.

2. The model device according to claim 1, characterized in that: The detecting whether the value of the input signal is a valid value and outputting validity flag information based on each input signal includes: Detecting whether the value of the input signal is a valid value according to the value attribute of the input signal; When the value of the input signal is a valid value, outputting validity flag information indicating that the input signal is valid; When the value of the input signal is invalid, validity flag information indicating that the input signal is invalid is output.

3. The model device according to claim 1, characterized in that: The detecting whether the value range of the input signal is within a first preset range and outputting validity mark information based on each input signal includes: When the value range of the input signal is within a first preset range, outputting validity mark information indicating that the input signal is valid; When the value range of the input signal is not within the first preset range, validity flag information indicating that the input signal is invalid is output.

4. The model device according to claim 1, characterized in that: The detecting whether the value change of the input signal is within a second preset range and outputting validity mark information based on each input signal includes: When the value variation of the input signal is within a second preset range, outputting validity mark information indicating that the input signal is valid; When the value variation of the input signal is not within the second preset range, validity flag information indicating that the input signal is invalid is output.

5. The model device according to claim 1, characterized in that: In the case where the calculation logic preset by the logic unit is numerical calculation, executing the preset calculation logic according to the input signal and its validity flag information includes: When the validity flag information of the input signal is valid, executing a preset calculation logic according to the current value of the input signal; In the case that the validity flag information of the input signal is invalid, the preset calculation logic is executed according to the historical valid value of the input signal instead of the current value.

6. A battery management system controller, characterized in that: The battery management system controller includes a control chip and an embedded software model device arranged on the control chip, and the embedded software model device is the embedded software model device described in any one of claims 1-5.

7. A vehicle, characterized in that: The vehicle includes the battery management system controller of claim 6.

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