A zero power consumption trimming circuit

Abstract

The present invention discloses a zero-power trimming circuit, including a bias current circuit and a trimming circuit connected thereto, wherein the output end of the trimming circuit is connected to a latch circuit, wherein the latch circuit locks the trimming result output by the trimming circuit when an enable signal jumps from low to high, and simultaneously turns off the bias current of the trimming circuit; the latch circuit is implemented by a gate circuit or a D flip-flop. The present invention achieves the purpose of ensuring zero power consumption of the trimming circuit while the trimming circuit outputs the trimming control bit normally by latching the trimming result and then turning off the trimming circuit.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor design, and in particular relates to a specific implementation method of a zero-power consumption trimming circuit, specifically a zero-power consumption trimming circuit. Background Art

[0002] At present, many applications have an increasingly urgent demand for low power consumption of chips. For applications that require multi-bit trimming, the power consumption of the total trimming circuit is becoming more and more obvious. However, in actual design, the power consumption allocated to each trimming circuit cannot be low, otherwise it will affect the recognition of the trimming results. Therefore, for low-power applications, the use of classic trimming circuit power consumption is necessary, but there is a requirement for low power consumption, which is a contradiction. Summary of the invention

[0003] In order to overcome the deficiencies of the above-mentioned prior art, the present invention provides a zero-power adjustment circuit, which achieves the purpose of ensuring zero power consumption of the adjustment circuit while achieving normal output of the adjustment control bit of the adjustment circuit by latching the adjustment result and then shutting down the adjustment circuit.

[0004] The present invention is achieved through the following technical solutions:

[0005] A zero-power trimming circuit comprises a bias current circuit and a trimming circuit connected thereto, wherein the output end of the trimming circuit is connected to a latch circuit, and when an enable signal jumps from low to high, the latch circuit locks the trimming result output by the trimming circuit and simultaneously turns off the bias current of the trimming circuit; the latch circuit is implemented by a gate circuit or a D flip-flop.

[0006] As a further technical solution, the latch circuit implemented by the gate circuit includes a first NOR gate, a second NOR gate, an RS trigger and several NOR gates. The input end of the first NOR gate is respectively connected to the adjustment result and the ENP signal, and the output end is sent to the RS trigger via multiple NOR gates; the input end of the second NOR gate is respectively connected to the adjustment result and the ENP signal after the NOR processing, and the output end is sent to the RS trigger via multiple NOR gates; the output end of the RS trigger sends the output result of the latch circuit via the NOR gate.

[0007] As a further technical solution, the latch circuit implemented by the gate circuit includes a first NAND gate, a second NAND gate, an RS trigger and several NOT gates, the input end of the first NAND gate is respectively connected to the adjustment result and the ENN signal after the NOT processing, and the output end is sent to the RS trigger via multiple NOT gates; the input end of the second NAND gate is respectively connected to the adjustment result and the ENN signal, and the output end is sent to the RS trigger via multiple NOT gates; the output end of the RS trigger sends the output result of the latch circuit via the NOT gate.

[0008] As a further technical solution, in a latch circuit implemented by a D flip-flop, the CK terminal of the D flip-flop is connected to the output terminal of an OR gate, and the input terminal of the OR gate is respectively connected to an enable signal and an enable delay signal; the enable terminal of the D flip-flop is connected to a VCC signal, and the output terminal sends out the output result of the latch circuit via a NOT gate.

[0009] As a further technical solution, the enable signal is provided by a reference circuit of the chip, and the output end of the reference circuit is connected in series with two NOT gates in sequence, wherein the output end of the first NOT gate outputs an ENN signal, and the output end of the second NOT gate outputs an ENP signal.

[0010] As a further technical solution, the output end of the second NOT gate is connected to a filter circuit for outputting an enable delay signal.

[0011] As a further technical solution, after the reference circuit jumps from low to high for a preset time, the trigger enable signal jumps from low to high.

[0012] As a further technical solution, the bias current provided by the bias current circuit is on the order of 10 microamperes.

[0013] As a further technical solution, the latch circuit further includes a plurality of MOS tubes for locking the state of the latch circuit.

[0014] Compared with the prior art, the present invention has the following beneficial effects:

[0015] The present invention combines the trimming circuit with the latch circuit to latch the trimming result and then close the trimming circuit, thereby realizing the normal output of the trimming control bit by the trimming circuit under the premise of zero power consumption of the trimming circuit.

[0016] The present invention can utilize gate circuits to realize latch circuits, and the circuit is simple to realize and has low cost, and has good practical significance for applications that require extremely low power consumption chips and require multi-bit adjustment.

[0017] The present invention can utilize a D flip-flop to realize a latch circuit, can effectively avoid the enabling error problem caused by the enabling signal burr phenomenon, and has a strong anti-interference ability. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Schematic diagram of a zero-power adjustment circuit according to an embodiment of the present invention.

[0019] Figure 2 FIG. 4 is a schematic diagram of a zero-power consumption trimming circuit according to another embodiment of the present invention.

[0020] Figure 3 FIG. 4 is a schematic diagram of a zero-power adjustment circuit according to another embodiment of the present invention. DETAILED DESCRIPTION

[0021] For applications that require extremely low power chips and multi-bit trimming, the power consumption of using a classic trimming circuit is too large or even unacceptable. To this end, the present invention provides a zero-power trimming circuit that latches the trimming result through a simple circuit structure and turns off the trimming circuit after latching, meeting the application scenario that requires extremely low power consumption but has multi-bit trimming requirements.

[0022] The following will clearly and completely describe the technical solutions of various embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0023] In the description of the present invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0024] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "connected" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be directly connected, or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0025] The present invention provides a zero-power consumption trimming circuit, comprising a bias current circuit and a trimming circuit connected thereto, wherein the output end of the trimming circuit is connected to a latch circuit, and when an enable signal jumps from low to high, the latch circuit locks the trimming result output by the trimming circuit and simultaneously turns off the bias current of the trimming circuit; the latch circuit is implemented by a gate circuit or a D flip-flop.

[0026] Example 1

[0027] This embodiment introduces a zero-power trimming circuit, including a bias current circuit, a trimming circuit and a latch circuit, wherein the bias circuit and the trimming circuit are of a classic trimming circuit structure.

[0028] like Figure 1As shown, the latch circuit is implemented by a gate circuit, including a first NOR gate, a second NOR gate, an RS trigger and a plurality of NOR gates.

[0029] Specifically, the trimming result out output by the trimming circuit is sent to the first input end of the first NOR gate, the second input end of the first NOR gate is connected to the ENP signal, and the output end is connected to the RS trigger after two NOR gates are connected in series.

[0030] The trimming result output by the trimming circuit is sent to the first input terminal of the second NOR gate after being processed by the NOT gate, the second input terminal of the second NOR gate is connected to the ENP signal, and the output terminal is connected to the RS trigger after two NOT gates are connected in series.

[0031] The RS trigger is composed of two NOR gates, and the specific circuit is implemented according to existing principles and will not be described in detail.

[0032] The output end of the RS trigger is connected to the MOS circuit through a NOT gate.

[0033] The MOS circuit includes two PMOS tubes and two NMOS tubes, wherein the gate of the first PMOS tube is connected to the ENN signal, the source is connected to the power supply, and the drain is connected to the source of the second PMOS tube. The gate of the second PMOS tube is connected in parallel with the gate of the first NMOS tube and connected to the output of the NOT gate, and the drain is connected in parallel with the drain of the first NMOS tube and connected to the output of the latch circuit. The source of the first NMOS tube is connected to the drain of the second NMOS tube, the gate of the second NMOS tube is connected to the ENP signal, and the source is grounded.

[0034] The enable signal is generated by a reference circuit of the chip, and the output end of the reference circuit is sequentially connected in series with two NOT gates, wherein the output end of the first NOT gate outputs an ENN signal, and the output end of the second NOT gate outputs an ENP signal.

[0035] It should be noted that, in order to ensure that the bias current has been fully established in the trimming circuit and the trimming state of Fuse1 has been read before the enable signal BG_OK jumps high, this embodiment delays the BG signal of the reference circuit after it jumps high before the enable signal BG_OK jumps high. The delay time here can preferably be tens of microseconds.

[0036] The working process of this embodiment is as follows (hereinafter 0 represents low level and 1 represents high level), initially BG_OK is 0, ENN is 1, and ENP is 0:

[0037] (1) The circuit is not adjusted and Fuse1 is not burned. out is 0, out1 is 1, and out2 is 0. The latch circuit output is 0. When BG_OK jumps from 0 to 1, the latch circuit is locked, and the value of out will no longer affect the output result TP of the latch circuit.

[0038] (2) The circuit has been adjusted and Fuse1 has burned. out is 1, out1 is 0, out2 is 1, and the latch circuit output is 1. When BG_OK jumps from 0 to 1, the latch circuit is locked, and the value of out will no longer affect the output result TP of the latch circuit.

[0039] In this embodiment, the trimming result out is sent to the latch circuit. When BG_OK jumps from low to high, the latch circuit completely locks the out result (the latch circuit is locked when ENP is high), and the bias current is completely turned off, and the circuit will be in a zero power consumption state. The enable signal BG_OK of the latch circuit must jump high to latch the output result of the trimming circuit and lock the latch circuit after the trimming circuit is established in a steady state and correctly outputs out.

[0040] It is worth noting that the bias of the bias circuit is preferably a larger bias, preferably in the order of 10uA, so that the trimming circuit can establish a steady state faster and the state of Fuse1 can be better identified.

[0041] Example 2

[0042] Different from Example 1, Figure 2 As shown, the latch circuit of this embodiment includes a first NAND gate, a second NAND gate, an RS trigger and a plurality of NOT gates.

[0043] Specifically, the adjustment result output by the adjustment circuit is sent to the first input end of the first NAND gate after being processed by the NOT gate, the second input end of the first NAND gate is connected to the ENN signal, and the output end is connected to the RS trigger after two NOT gates are connected in series.

[0044] The trimming result out output by the trimming circuit is sent to the first input terminal of the second NAND gate, the second input terminal of the second NAND gate is connected to the ENN signal, and the output terminal is connected to the RS trigger after two NAND gates are connected in series.

[0045] The RS trigger is composed of two NAND gates, and the specific circuit is implemented according to existing principles and will not be described in detail.

[0046] The output end of the RS trigger is connected to the MOS circuit through a NOT gate. The connection relationship of the MOS circuit is the same as that of the first embodiment.

[0047] The working process of this embodiment is as follows (hereinafter 0 represents low level and 1 represents high level), initially BG_OK is 0, ENN is 1, and ENP is 0:

[0048] (1) The circuit is not adjusted, and Fuse1 is not burned. out is 0, out1 is 0, and out2 is 1. The latch circuit output is 0. When BG_OK jumps from 0 to 1, the latch circuit is locked, and the value of out will no longer affect the output result TP of the latch circuit.

[0049] (2) The circuit has been adjusted and Fuse1 has burned. out is 1, out1 is 1, out2 is 0, and the latch circuit output is 1. When BG_OK jumps from 0 to 1, the latch circuit is locked, and the value of out will no longer affect the output result TP of the latch circuit.

[0050] Example 3

[0051] Different from the above-mentioned embodiment, this embodiment adopts a D flip-flop to realize the latch circuit.

[0052] like Figure 3 As shown, the CK terminal of the D flip-flop is connected to the output terminal of the OR gate, and the input terminal of the OR gate is connected to the enable signal and the enable delay signal respectively. In this embodiment, the CK input signal of the D flip-flop is set to the OR of BG_OK and BG_OK_DEY, which can make the locking state of the circuit more stable.

[0053] The enable terminal of the D flip-flop is connected to the VCC signal, the input terminal is connected to the adjustment signal out, the output terminal is connected to the MOS circuit via the NOT gate, and is connected to the output terminal TP via the MOS circuit.

[0054] It should be noted that it is difficult to find a suitable signal for the enable end of the D flip-flop, and the common practice is to connect it directly to VCC.

[0055] The enable signal is provided by a reference circuit of the chip, and the output end of the reference circuit is sequentially connected in series with two NOT gates, wherein the output end of the first NOT gate outputs an ENN signal, and the output end of the second NOT gate outputs an ENP signal.

[0056] Furthermore, the output end of the second NOT gate is connected to a filter circuit for outputting an enable delay signal.

[0057] The working process of this embodiment is as follows (hereinafter 0 represents low level and 1 represents high level), initially BG_OK is 0, ENN is 1, and ENP is 0:

[0058] (1) The circuit is not adjusted, and Fuse1 is not burned. out is 0. When BG_OK changes from 0 to 1, that is, when a rising edge comes, the D trigger collects the 0 of out into the output of the D flip-flop. After that, BG_OK and BG_OK_DEY are both high, and there will be no more rising edges. The circuit state is locked, and the value of out will no longer affect the output result TP of the latch circuit.

[0059] (2) The circuit is not adjusted, and Fuse1 has burned. out is 1. When BG_OK changes from 0 to 1, that is, when a rising edge comes, the D trigger collects the 1 of out into the output of the D flip-flop. After that, BG_OK and BG_OK_DEY are both high, and there will be no more rising edges. The circuit state is locked. The value of out will no longer affect the output result TP of the latch circuit.

[0060] In summary, the present invention combines the trimming circuit with the latch circuit to latch the trimming result and then turn off the trimming circuit, thereby realizing the normal output of the trimming control bit by the trimming circuit under the premise of zero power consumption of the trimming circuit.

[0061] It should be noted that the latching method using gate circuits is more reliable, because the state of out has been read into the latch before BG_OK jumps high, and BG_OK jumps high only locks the state of the latch circuit, and the gate circuits used are relatively few and simpler to implement. The latch circuit composed of D flip-flops completes latch reading and locking almost at the same time, but it has strong anti-interference ability, can effectively solve the problem caused by enable signal glitches, and its locked state is relatively more stable.

[0062] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the technical solutions of the embodiments of the present invention.

Claims

1. A zero-power trimming circuit, characterized in that: It includes a bias current circuit and a trimming circuit connected thereto, wherein the output end of the trimming circuit is connected to a latch circuit, and the latch circuit locks the trimming result output by the trimming circuit when an enable signal jumps from low to high, and at the same time turns off the bias current of the trimming circuit, the enable signal is generated by a reference circuit of the chip, and the enable signal jumps high for a preset time before the enable delay signal jumps high; the latch circuit is implemented by a gate circuit or a D flip-flop; the CK end of the D flip-flop is connected to the output end of an OR gate, and the input end of the OR gate is respectively connected to the enable signal and the enable delay signal; the enable end of the D flip-flop is connected to a VCC signal, and the output end sends out the output result of the latch circuit via a NOT gate; the enable signal is provided by the reference circuit of the chip, and the The output end of the reference circuit is connected in series with two NOT gates in sequence, wherein the output end of the first NOT gate outputs an ENN signal, and the output end of the second NOT gate outputs an ENP signal; the output end of the second NOT gate is connected to a filter circuit for outputting an enable delay signal; wherein the latch circuit implemented by the gate circuit comprises a first NOR gate, a second NOR gate, an RS trigger and a plurality of NOR gates, the input end of the first NOR gate is respectively connected to the adjustment result and the ENP signal, and the output end is sent to the RS trigger via a plurality of NOR gates; the input end of the second NOR gate is respectively connected to the adjustment result and the ENP signal after the NOT processing, and the output end is sent to the RS trigger via a plurality of NOR gates; the output end of the RS trigger sends out the output result of the latch circuit via the NOR gate.

2. A zero-power consumption trimming circuit according to claim 1, characterized in that: The latch circuit implemented by the gate circuit may include a first NAND gate, a second NAND gate, an RS trigger and several NOT gates, wherein the input end of the first NAND gate is respectively connected to the adjustment result and the ENN signal after the negation processing, and the output end is sent to the RS trigger via multiple NOT gates; the input end of the second NAND gate is respectively connected to the adjustment result and the ENN signal, and the output end is sent to the RS trigger via multiple NOT gates; the output end of the RS trigger sends the output result of the latch circuit via the NOT gate.

3. A zero-power consumption trimming circuit according to claim 1, characterized in that: After the reference circuit jumps from low to high for a preset time, the trigger enable signal jumps from low to high.

4. A zero-power consumption trimming circuit according to claim 1, characterized in that: The bias current provided by the bias current circuit is on the order of 10 microamperes.

5. A zero-power consumption trimming circuit according to any one of claims 1 to 2, characterized in that: The latch circuit also includes a plurality of MOS tubes for locking the state of the latch circuit.

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