Method for forming deep silicon through-hole via in stacked wafer and semiconductor device

Abstract

The present invention relates to the field of semiconductor manufacturing, and in particular to a method for forming a stacked wafer deep silicon through hole and a semiconductor device. The method comprises: depositing a dielectric film layer on a substrate, transferring an etching pattern to the dielectric film layer through a photolithography process as a hard mask layer; etching the hard mask layer on the first wafer substrate according to the etching pattern, thereby forming a silicon through hole TSV and a TSV blind hole; depositing a linear oxide layer inside the TSV through an oxidation deposition process, filling and forming a support layer on the linear oxide layer whose surface is flat and consistent with the surface of the dielectric film layer; interconnecting metal wires, and making blind holes and / or pads for hybrid bonding to form a first wafer; hybrid bonding the first wafer with a second wafer other than the first wafer to form a stacked wafer; performing a Cu CMP process to form a TSV for deriving electrical signals from the stacked wafer. By utilizing the present invention, the process window for manufacturing semiconductor devices is significantly increased, and the process difficulty is significantly reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular, to a method for forming a stacked wafer deep silicon through via (TSV) and a semiconductor device. Background Art

[0002] In the manufacturing process of stacked wafers, the traditional deep silicon via formation method is very difficult to etch due to the high aspect ratio of silicon vias on wafers. There are several main problems: the top forms a bell mouth, the heat conduction is uneven, and during the etching process of Through-Silicon Via Bosch (TSV Bosch), the etching rate and morphology are inconsistent at different locations on the same wafer. Summary of the invention

[0003] In view of the above technical problems, the present invention provides a method for forming deep silicon vias of stacked wafers, comprising the following steps: step S1, depositing a dielectric film layer on a substrate, and transferring an etching pattern to the dielectric film layer through a photolithography process as a hard mask layer; step S2, etching the hard mask layer on the first wafer substrate according to the etching pattern, thereby forming a through silicon via TSV and a TSV blind hole; step S3, depositing a linear oxide layer inside the TSV through an oxidation deposition process, and filling and forming a support layer on the linear oxide layer whose surface is kept flat and consistent with the surface of the dielectric film layer; step S4, interconnecting metal wires, and making blind holes and / or pads for hybrid bonding to form a first wafer; step S5, hybrid bonding the first wafer with a second wafer other than the first wafer to form a stacked wafer; step S6, performing a Cu chemical mechanical polishing (CMP) process to form a TSV for exporting electrical signals of the stacked wafers.

[0004] In addition, preferably, the present invention provides a stacked wafer deep silicon via formation method, in the step S1, the thickness of the dielectric film layer is determined according to the thickness of silicon to be etched and the thickness of the dielectric layer between the first wafer and the second wafer.

[0005] In addition, preferably, the present invention provides a stacked wafer deep silicon via formation method, in the step S1, the thickness of the dielectric film layer is in the range of 1um-10um. In addition, the thickness of the dielectric film layer can be determined within the above range according to the required thickness of the etched silicon and the thickness of the dielectric layer between the wafers.

[0006] In addition, preferably, the present invention provides a stacked wafer deep silicon via formation method, in step S6, before the Cu CMP process, it also includes: step S61, exposing the TSV blind hole through a BVR process, removing the filling material inside the TSV through an ashing process, and annealing and reducing the metallic copper using a reducing gas, thereby removing the copper oxide on the surface.

[0007] In addition, preferably, the present invention provides a stacked wafer deep silicon via formation method, in step S61, the annealing reduction treatment temperature range is 200 ° C-350 ° C.

[0008] In addition, preferably, the present invention provides a stacked wafer deep silicon via formation method, in step S61, the annealing reduction treatment temperature range is 315°C-340°C.

[0009] In addition, preferably, the present invention provides a method for forming deep silicon vias in stacked wafers. In the step S6, after step S61, it also includes: step S62, performing a through silicon via barrier layer & seed layer electrochemical plating process (TSV B&S ECP, also known as TSV Barrier&Seed Electrochemical Plating) on ​​the stacked wafers to complete the metal copper filling in the TSV, wherein ECP refers to electrochemical plating.

[0010] In addition, preferably, the present invention provides a stacked wafer deep silicon via formation method, in the step S62, in the TSV B&S ECP operation method, B&S is implemented at least to the extent that the deposited film layer occurs continuously so that the subsequent ECP can be powered on normally, ECP is implemented at least to the extent that it can ensure that there are no holes inside, and Cu CMP is implemented at least to the extent that the surface copper is completely removed and there is no copper residue on the surface.

[0011] In addition, preferably, the present invention provides a stacked wafer deep silicon via formation method, in the step S3, the thickness of the linear oxide layer is the thickness of the dielectric film layer less than or equal to the thickness of the support layer.

[0012] Furthermore, preferably, the present invention provides a semiconductor device, which is a hybrid bonded stacked wafer having TSVs obtained by any stacked wafer deep through silicon via formation method described in the present invention.

[0013] The stacked wafer deep silicon through hole formation method of the present invention has the following technical effects. First, because only Si needs to be etched in the process, the use of a hard mask layer made of the original dielectric layer material can avoid the trumpet-mouth morphology. Second, TSV etching can be completed on a single wafer. Third, the TSV etching process is completed first, blind hole etching is performed, and then thinning is performed from the back of the wafer, thereby completing the TSV etching process of the stacked wafer.

[0014] Because the process method of the present invention does not require high uniformity of etching depth of TSV blind hole etching, TSV can be exposed by BVR in the later stage. Compared with the process integration solution of silicon thinning + TSV etching with stop layer, the process window of overall TSV blind hole etching + hole internal filling (detailed description later) + BVR TSV exposure is significantly increased and the process difficulty is significantly reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work, among which:

[0016] Figure 1 A schematic diagram showing a TSVSi Bosch etching process flow used in a stacked wafer deep through silicon via formation method according to an embodiment of the present invention.

[0017] Figure 2 A schematic diagram showing a TSVloop etching process flow used in a stacked wafer deep through silicon via formation method according to an embodiment of the present invention.

[0018] Figure 3 A schematic diagram showing a mechanism of forming a top bell mouth in a stacked wafer deep through silicon via formation method according to an embodiment of the present invention.

[0019] Figure 4 A schematic diagram illustrating a mechanism in which a TSV top flare causes a TSV short circuit in a stacked wafer deep through silicon via formation method according to an embodiment of the present invention.

[0020] Figure 5 A schematic diagram showing a mechanism in which the liner oxide layer is consumed due to the TSV top flare used in a stacked wafer deep through silicon via formation method according to an embodiment of the present invention.

[0021] Figure 6 A schematic diagram showing the formation mechanism of the TSV Si ET bottom Notching morphology in a stacked wafer deep through silicon via formation method according to an embodiment of the present invention.

[0022] Figure 7 A schematic diagram showing a preferred process flow of a stacked wafer deep through silicon via formation method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Other embodiments or variations obtained based on the embodiments in the present application by ordinary technicians in this field without creative work are all within the scope of protection of this application.

[0024] See also Figure 1 , Figure 1 FIG. 4 is a schematic diagram of a TSVSi Bosch etching process flow used in a stacked wafer deep silicon via formation method according to an embodiment of the present invention.

[0025] Among them, the Si part usually adopts the ICP Bosch etching process. This process first uses fluorine-based active groups to etch silicon, and then passivates the side walls. The two-step process of etching and protection is performed alternately. It realizes etching and side wall passivation by alternating the etching gas and the passivation gas. The etching gas is SF6 and the passivation gas is C4F8. C4F8 can form fluorinated carbon polymers in plasma. It is deposited on the silicon surface to prevent the reaction between fluoride ions and silicon. Etching and passivation are constantly switched to form a cycle.

[0026] After a short period of isotropic etching, the silicon surface that has just been etched is passivated. Due to the physical sputtering bombardment of ions in the depth direction, the passivation film can be retained, so that the next cycle of etching will not cause lateral etching. Through this periodic "etching-passivation-etching", etching is only carried out along the depth direction.

[0027] In the process of through silicon via, the dielectric layer material needs to be etched. At this time, it needs to be combined with capacitively coupled plasma dielectric film etching (CCP dielectric etch) to complete all the etching processes of the through silicon via.

[0028] After in-depth research on the technical issues involved in the present invention, the inventors of the present invention have also found that there are at least the following problems in the process of through silicon via etching:

[0029] 1. Top horn problem: The structure etched at the bottom of the stacked wafer usually has a dielectric layer of several microns, so a certain dielectric layer needs to be deposited on the top as a hard mask layer, which serves as a hard mask layer for etching silicon and the bottom dielectric layer. The overall etching process diagram is as follows: Figure 2As shown, first deposit the surface dielectric layer, then perform photolithography and etching of the top dielectric layer in sequence, at this time the top dielectric layer uses photoresist as a mask layer. After etching is completed, remove the remaining photoresist. Then perform Bosch silicon etching, bottom dielectric layer etching, atomic layer deposition (ALD) liner oxide layer deposition, and bottom ALD liner oxide layer etching, thereby completing the entire through silicon via etching process.

[0030] After silicon etching is completed, the surface of the top dielectric layer will become uneven due to the bombardment of etching ions. Then the CCP etching of the bottom dielectric layer will be performed. Since the bottom and top materials are similar, the consumption of the top dielectric layer hard mask is also large. At the same time, due to the characteristics of etching, the raised part of the edge near the top silicon through hole will be consumed first. Finally, after the bottom dielectric layer and thermal oxide layer are etched, a trumpet-shaped morphology will appear on the top. The schematic diagram is as follows Figure 3 shown.

[0031] The following problems may occur when a bell mouth appears on the top:

[0032] ① The overall morphology of TSV will change. At the same time, the distance between TSVs will be shortened, and the electrical performance will be different from the original design;

[0033] ② When the TSV distance is designed to be close enough and the bell mouth is expanded to a certain extent, the two hole interfaces contact each other, and eventually the TSV short circuit phenomenon will occur, such as Figure 4 shown.

[0034] ③ Due to the inclined morphology of the bell mouth, the subsequent linear insulating oxide layer is etched away during the etching process, and eventually a considerable part of the side wall is not protected by the insulating layer, especially the silicon part. The copper in the TSV diffuses in the silicon, and the electrical performance is affected, which may seriously cause the TSV to short-circuit, such as Figure 5 shown.

[0035] To this end, the structure of the surface dielectric layer hard mask is adjusted: the top bell-mouth morphology is adjusted by inserting SiN into SiO2. Because the etching rate of SiN is lower than that of SiO2 in the usual etching process, the bell-mouth morphology of the etching can be reduced to a certain extent, but the bell-mouth still exists. If most of the top dielectric layer is replaced with SiN, the bell-mouth will be significantly reduced, but in the process of etching SiN, more by-products are generated, which accumulate in the holes and cavities and are difficult to remove.

[0036] In addition, there will be problems with thermal conductivity uniformity: TSV Bosch process etching is a low-temperature process, and the wafer temperature is a critical parameter. At this time, the electrostatic chuck at the bottom of the wafer cools down and transfers the low temperature to the wafer to control the temperature of the wafer. Since 3DIC performs TSV etching on the upper wafer of the stacked wafers, the bonding quality of the bonding interface will affect the temperature conduction, which will increase the difficulty of temperature control of the upper wafer. It is difficult to control its temperature within the predetermined range, resulting in deviations in the TSV etching process. At the same time, the bonding quality of different positions on the same wafer is also different, so the temperature of different positions on a wafer is also different, which leads to phenomena such as etching rate and inconsistent morphology at different positions on the same wafer in TSV Bosch etching.

[0037] To this end, the temperature of the bottom electrostatic chuck is set in advance through experiments, and the temperature of the top wafer is measured with a temperature detector to obtain the temperature difference between them, which provides a basis for later process adjustments. At the same time, in order to solve the problem of different temperatures at different radii of the same wafer, the multi-zone temperature-controlled electrostatic chuck is upgraded to adjust the temperature of different areas separately. Combined with the previously measured temperature difference between the chuck and the stacked wafer, the temperature of different areas of the top wafer can be kept consistent, thereby ensuring the uniformity of the TSV Bosch process. However, the electrostatic chuck of an ordinary etching machine is a single-zone temperature control system, which requires the hardware of the machine to be modified and the cooperation of the manufacturer is required.

[0038] When adjusting the process, the temperature of the electrostatic chuck needs to be precisely controlled in different areas, which is quite difficult. When there are more wafer stacking layers, the heat conduction loss is greater, and the temperature of the electrostatic chuck may reach the lowest temperature but still cannot drop the temperature of the top wafer to the preset temperature.

[0039] In addition, there is the problem of uniformity of silicon thinning thickness: the thinning thickness of the top wafer is the etching depth of TSV. When TSVSi etching is completed, if etching continues, due to the poor conductivity of the dielectric layer below, ions will gather and the bottom side will be hollowed out, such as Figure 6 shown.

[0040] This will result in: 1. The subsequent etching rate of the bottom dielectric layer is slow, resulting in an electrical open circuit; 2. The B&S electrochemical plating film cannot be filled normally after side excavation, etc.

[0041] Therefore, in addition to controlling the uniformity of TSV Si etching rate in different areas, it is also necessary to strictly control the uniformity of Si thinning thickness. However, since the overall TSV Si ET process window is very narrow, the process requirements for silicon thinning are very high. Usually, 50um TSV Si ET requires control at the level of 50um±0.5um. Wafer thinning needs to be thinned from 775um to 50um, and the process difficulty is very high. When the thickness of silicon thinning cannot meet the requirements, TSV Si ET is required to cover the process window, which is extremely difficult.

[0042] The present invention optimizes the process flow of overall wafer-level stacking, adopts a TSV etching process first, and then performs wafer stacking, thereby avoiding the problems of the TSV etching process caused by the top trumpet morphology, stacking heat conductivity, and uniformity of thinned wafer thickness during the TSV etching process. At the same time, a filling material is added to the hole after TSV etching, and the internal filling material is removed after the subsequent process flow, that is, the copper conductive column exposure process in the back TSV hole (also known as BVR, backside via reveal) process, and the subsequent Cu B&S ECP process is continued, which solves the problem of TSV Cu internal cracking caused by excessive BVR Si thinning stress, so as to complete the derivation of the final stacked wafer electrical signal.

[0043] In addition, preferably, BVR ashing is a conventional process, BVR only needs to expose the copper completely, and ashing only needs to remove the internal filling material. H2 reduction can be controlled between 200-350°C (because 350°C is the highest temperature that DRAM wafers can withstand), and the time can be unlimited.

[0044] The technical solution of the present invention greatly reduces the process difficulty of TSV etching of stacked wafers in 3DIC by optimizing the process flow, optimizes the structural morphology of TSV, and reduces the process difficulty of BVR Si thinning, greatly optimizes the final physical structure of TSV, and improves the electrical performance of 3DIC advanced packaging stacked wafers.

[0045] Based on the three problems of through silicon via etching caused by TSV etching mentioned above: top bell-mouth morphology, uneven thermal conductivity of stacked wafers, and uniformity of silicon thinning thickness, the inventors of the present invention have made the following considerations:

[0046] 1. The top bell-mouth morphology is caused by the similar materials of the top hard mask layer and the bottom dielectric layer. If only Si is etched, the bell-mouth morphology can be avoided by using a hard mask layer made of the original dielectric layer material.

[0047] 2. The bonding interface in the middle of the stacked wafers affects the thermal conductivity of the wafers, thereby affecting the TSV etching process. Therefore, if TSV etching is completed on a single wafer, this problem will not occur.

[0048] 3. The thickness uniformity of silicon thinning directly affects the TSV etching process. If the TSV etching process is completed first, blind hole etching is performed. Then thinning is performed from the back of the wafer to complete the TSV etching process of the stacked wafer. Because the etching depth uniformity of TSV blind hole etching is not required to be high, BVR can be used to expose TSV in the later stage. The overall TSV blind hole etching + hole internal filling (detailed description later) + BVR TSV exposure significantly increases the process window and significantly reduces the process difficulty compared to the process integration solution of silicon thinning + TSV etching with a stop layer.

[0049] Based on the above considerations, as a preferred embodiment of the present invention, Figure 7 As shown, the specific process can also be as follows:

[0050] 1. Initial wafers are brought in. Since silicon has a certain thickness, the thickness of the photoresist alone cannot meet the requirements during the etching process. Therefore, a dielectric film layer of a certain thickness needs to be deposited as a hard mask layer.

[0051] 2. Perform TSV lithography process;

[0052] 3. Perform TSV etching process to etch the hard mask layer and its own dielectric layer;

[0053] 4. Perform TSV blind hole etching

[0054] 5. Perform linear oxide layer deposition;

[0055] 6. Materials are deposited inside the TSV to provide support;

[0056] 7. Grind to make the surface smooth;

[0057] 8. Carry out subsequent metal wire interconnection and make hybrid bonded Via / Pad;

[0058] 9. Wafer 1 is manufactured by conventional process, and wafer 1 and wafer 2 are hybrid bonded;

[0059] 10. Perform BVR process to expose TSV blind holes;

[0060] 11. Use the ashing process to remove the filling material inside the TSV;

[0061] 12. Use reducing gas (H2, etc.) to anneal and reduce the metallic copper to remove the copper oxide on the surface;

[0062] 13. Perform TSV B&S ECP process;

[0063] 14. Perform Cu CMP to remove surface copper, complete the TSV process, and export the electrical signals of the stacked wafers.

[0064] In addition, in the technical solution of the preferred embodiment of the present invention, TSV etching is performed first and then wafer stacking is performed, which has the following advantages.

[0065] ① There is no dielectric layer structure at the bottom, so there will be no defects in the top bell-mouth morphology;

[0066] ② Since it is TSV etching of a single wafer, there is no problem of heat transfer uniformity caused by the bonding interface. Therefore, the wafer temperature can be controlled more accurately through the electrostatic chuck, which reduces the difficulty of TSV Si Bosch etching;

[0067] ③At this time, the TSV Si Bosch etching is a blind hole structure, and the thickness requirement is not strict. After the Si etching in the stacked wafer is completed, the side digging phenomenon will not occur when it touches the bottom dielectric layer. The current process only needs to use silicon thinning to expose the TSV blind hole from the back. The uniformity of the thickness of the silicon thinning of the same wafer can be compensated by subsequent dielectric layer deposition, CMP and other processes to smooth the wafer surface.

[0068] In addition, due to the problem of depth uniformity of TSV blind hole etching, when the subsequent BVR silicon thinning process is performed, the deep etched part of the blind hole in the same wafer will be exposed first, and the Cu that has been filled inside will continue to be ground for a period of time. Since the hardness of silicon is much greater than that of copper, the stress on copper during the silicon thinning process is very large. The internal Cu of TSV will be torn due to excessive internal stress during this process. Therefore, we innovatively perform a liner oxide layer process after the TSV etching to isolate the diffusion of Cu in Si, and deposit a barrier layer to play a certain role in blocking and subsequent ECP conductivity. The internal filling material plays a supporting role. In the subsequent BVR process, due to the support inside the TSV, the TSV morphology does not change. The filling material can be a common organic polymer in Fab, which is solidified by light and has a certain mechanical strength. It can be removed by ashing process later. It can also be a reducing material such as carbon powder. Carbon powder can directly react with CuO through the furnace tube to reduce the oxide on the copper surface to a certain extent. At the same time, the generated CO2 gas is pumped away and will not remain inside the hole. After completion, we use a H2 furnace tube annealing to completely remove the oxide on the copper surface to ensure the subsequent electrical connection effect.

[0069] In the technical solution of the preferred embodiment of the present invention, by optimizing the process flow of overall wafer-level stacking, a TSV etching process is first performed, followed by wafer stacking. This avoids the problems of the TSV etching process caused by the top bell-mouth morphology, stacking heat conductivity, and uniformity of thinned wafer thickness during the TSV etching process. At the same time, a filling material is innovatively added to the holes after TSV etching, and the internal filler is removed after the BVR process in the subsequent process flow, and the subsequent Cu ECP process is continued, which solves the problems of TSV Cu ECP filling Seam defects and TSV Cu internal cracking caused by excessive BVR Si thinning stress, so as to complete the final stacked wafer electrical signal export.

[0070] In addition, in the technical solution of the preferred embodiment of the present invention, the process sequence is to first perform TSV blind hole etching and then perform wafer stacking, so as to ensure that TSV etching is performed on a single wafer.

[0071] In addition, in the technical solution of the preferred embodiment of the present invention, the process flow is as follows: TSV blind hole etching, TSV internal filling support material, wafer bonding, BVR, removal of TSV internal support material, reducing atmosphere annealing, B&SECP, CuCMP. In addition, preferably, B&S only needs to ensure the continuity of the deposited film layer, and the subsequent ECP can be powered on normally. ECP ensures that there are no holes inside. Cu CMP must ensure that the surface copper is completely removed and there is no copper residue on the surface.

[0072] In addition, in the technical solution of the preferred embodiment of the present invention, the material filled inside the TSV can be a common organic substance in the Fab, such as Barc, photoresist and other materials. This material can be denatured by light of a certain wavelength, and the hardness is greatly improved, playing a supporting role, and can be easily removed later without residue. It can also be a non-metallic material with reducing properties such as carbon, which has a certain strength itself and can be easily removed later, and can also play a certain role in reducing CuO; in summary, it needs to ensure a certain strength, easy to remove later, and not react with copper. It is better if it can have a certain role in reducing CuO.

[0073] In addition, this case details the process flow for connecting TSV to the metal layer of the upper wafer, and it can also be connected to the metal layer of the lower wafer. At this time, both sides of the TSV through hole need to be filled with material, and exposed through BVR after alignment and bonding. The subsequent process flow is similar to that described in this case, and the filler is removed, annealed and reduced, unidirectional Cu ECP, and surface Cu CMP processes are performed in sequence, and finally TSV is used to electrically connect the lower wafer; annealing and reducing CuO can be done with reducing gases such as H2 CO; what is the final thickness of silicon, how deep the Si through hole should be at the beginning, the final thinning thickness of silicon is 3-70um, the depth of the Si through hole should be 5%-10% of the thickness to play a supporting role, how much hardness should be achieved, and details are supplemented, and different parameters need to be limited to use photosensitive Barc, photoresist and other organic materials. UV curing is a photochemical reaction, which is different from the principle of the traditional drying and curing process. Traditional drying and curing generally forms hardening with the help of the volatilization of solvents in the coating material, while UV curing does not evaporate solvents. UV curing is a type of radiation curing. It is a chemical process that uses ultraviolet light UV to produce photochemical reactions such as radiation polymerization and radiation cross-linking in a very short time to quickly convert low molecular weight substances into high molecular weight products. The system contains no solvent or very little solvent. After irradiation, the liquid film is almost 100% cured, so the VOC (volatile organic compound) emissions are very low.

[0074] In addition, the UV curing time is between 5s-60s, which is determined by the diameter and depth of the hole. The light wave is a short-wave ultraviolet light source: Ultraviolet C. UV-C, wavelength 100nm-280nm, photon energy 4.43-12.4eV / 0.710-1.987aJ, light intensity 50-250mW / cm 2 , the Shore hardness can reach D42.

[0075] In addition, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0076] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0077] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

[0078] The above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A method for forming deep silicon vias in stacked wafers, characterized in that: The following steps are involved: Step S1, depositing a dielectric film layer on a substrate, and transferring an etching pattern to the dielectric film layer as a hard mask layer through a photolithography process; Step S2, etching the hard mask layer on the substrate according to the etching pattern, so as to form through silicon vias TSV and TSV blind holes; Step S3, depositing a linear oxide layer inside the TSV by an oxidation deposition process, and filling and forming a support layer on the linear oxide layer whose surface is flat and consistent with the surface of the dielectric film layer; Step S4, interconnecting metal wires and making blind vias and / or pads for hybrid bonding to form a first wafer; Step S5, hybrid bonding the first wafer with a second wafer other than the first wafer, thereby forming a stacked wafer; Step S6, exposing the TSV blind hole through a BVR process, removing the filling material inside the TSV through an ashing process, and annealing and reducing the metal copper using a reducing gas to remove copper oxide on the surface; Step S7 , performing a Cu CMP process to form TSVs for conducting electrical signals of the stacked wafers.

2. The stacked wafer deep silicon via forming method according to claim 1, characterized in that: In the step S1 , the thickness of the dielectric film layer is determined according to the thickness of silicon to be etched and the thickness of the dielectric layer between the first wafer and the second wafer.

3. The stacked wafer deep silicon via forming method according to claim 2, characterized in that: In the step S1, the thickness of the dielectric film layer is in the range of 1 um to 10 um.

4. The stacked wafer deep through silicon via forming method according to claim 1, characterized in that: In step S6, the annealing reduction treatment temperature ranges from 200°C to 350°C.

5. The stacked wafer deep silicon via forming method according to claim 1, characterized in that: In step S6, the annealing reduction treatment temperature range is 315°C-340°C.

6. The stacked wafer deep through silicon via forming method according to claim 1, characterized in that: After step S6 and before step S7, the method further includes: Step S61 , performing TSV B&S electrochemical plating on the stacked wafer to complete the metal copper filling in the TSV.

7. The stacked wafer deep silicon via forming method according to claim 6, characterized in that: In step S61, in the operation method of TSV B&S electrochemical plating, B&S is implemented at least to the extent that the deposited film layer is continuous so that the subsequent electrochemical plating can be powered on normally, the electrochemical plating is implemented at least to the extent that it can ensure that there are no holes inside, and the Cu CMP is implemented at least to the extent that the surface copper is completely removed and there is no copper residue on the surface.

8. A semiconductor device, characterized in that: The semiconductor device is a hybrid bonded stacked wafer having TSVs obtained by the stacked wafer deep through silicon via formation method according to any one of claims 1 to 7.

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