A fully vertical gallium nitride accumulation-type power device and a method for preparing the same

Abstract

The present invention discloses a fully vertical gallium nitride accumulation power device and a preparation method thereof, and belongs to the technical field of semiconductor devices. The key innovation of the fully vertical gallium nitride accumulation power device is that an edge electric field optimization structure is constructed separately on both sides of the gate electrode, and the drain electrode is arranged on the lower surface of the substrate layer corresponding to the source electrode. Based on the mutual cooperation of the key innovation points, on the one hand, the present invention can not only effectively alleviate the edge peak electric field formed by the corners of the gate trench at both ends, but also greatly shorten the current passage path, thereby achieving the purpose of reducing the specific on-resistance while increasing the breakdown voltage. On the other hand, the present invention can avoid the current edge collection effect at the edge of the drain electrode, so that the power device is not easily thermally broken down. On the other hand, the present invention can also increase the density of cells in the chip, thereby increasing the area utilization of the entire chip, and correspondingly achieving the purpose of increasing the total current density.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a full vertical gallium nitride accumulation-type power device and a preparation method thereof. Background Art

[0002] As power electronics continues to develop, first-generation semiconductor devices such as silicon germanium are beginning to be unable to adapt to the current high-frequency and high-voltage application environment. It is a general trend to actively explore more suitable wide-bandgap semiconductor materials with better properties. Gallium nitride (GaN), as a third-generation semiconductor, is widely used in high-frequency scenarios because of its large bandgap width (~3.4eV), high electron saturation velocity and good high-temperature resistance.

[0003] At present, there are many power devices based on gallium nitride. For example, the patent document with the publication number CN117219672A discloses a quasi-vertical gallium nitride accumulation power device, which includes a silicon substrate, a buffer layer, a second heavily doped gallium nitride conductive layer, a lightly doped gallium nitride conductive layer, a first heavily doped gallium nitride conductive layer and a source electrode arranged in sequence from bottom to top. A transverse groove is provided at the upper end of the lightly doped gallium nitride conductive layer, and a gate electrode wrapped with an oxide layer is provided in the transverse groove. The first heavily doped gallium nitride conductive layer is arranged between the gate electrodes; vertical grooves are provided at both ends of the lightly doped gallium nitride conductive layer, and a drain electrode is fixed in the vertical groove. The lower end of the drain electrode forms an ohmic contact with the second heavily doped gallium nitride conductive layer, and the upper end is located at the same horizontal plane as the source electrode; a semi-insulating polysilicon layer is provided between the two ends of the source electrode and the upper end of the drain electrode, and an insulating dielectric layer is provided above and below the semi-insulating polysilicon layer. However, after careful analysis, it is found that it still has the following technical problems:

[0004] 1. When the power device is in use, a fringe electric field peak is likely to appear at the corners of the gate trench near the withstand voltage terminal, but the power device cannot alleviate and optimize the fringe electric field peak, which affects the breakdown characteristics of the power device and results in low withstand voltage.

[0005] 2. Compared with the full vertical structure power device of the same size, the drain electrode and source electrode of this power device are both concentrated on the upper surface of the power device. Therefore, when the power device is turned on, the current will have an additional current path in the horizontal direction when it passes through the second heavily doped gallium nitride conductive layer. That is, the current needs to flow vertically first and then horizontally to reach the drain electrode. On the one hand, this not only makes the current path of the power device longer, but also makes it have a larger specific on-resistance; on the other hand, if Fig.18As shown, when the applied voltage is large and the current passing through is large, the current edge gathering effect is likely to occur at the edge of the drain electrode, which in turn causes high heat in the current close contact area, making the power device susceptible to thermal breakdown.

[0006] 3. When the power device is used in a chip, since the drain electrode is arranged on both sides of the gate electrode, a terminal structure (protective layer) of corresponding length must be set between each cell structure, which greatly reduces the density of the cell, not only reducing the area utilization of the entire chip, but also causing the total current density to still be relatively small.

[0007] It should also be noted that, from the specification of the above power device, although it has the function of increasing the breakdown voltage and reducing the specific on-resistance, the specific on-resistance will also be increased simultaneously when the breakdown voltage is increased, so its comprehensive performance still needs to be improved. For this reason, it is necessary to provide a new full vertical gallium nitride accumulation power device to solve the above technical problems. Summary of the invention

[0008] The first aspect of the present invention provides a fully vertical gallium nitride accumulation-type power device, the key innovation of which is that an edge electric field optimization structure is constructed separately on both sides of the gate electrode, and the drain electrode is arranged on the lower surface of the substrate layer corresponding to the source electrode. Based on the mutual cooperation of the key innovation points, on the one hand, the present invention can not only effectively alleviate the edge spike electric field formed by the corners of the gate trench at both ends, but also greatly shorten the current passage path, thereby achieving the purpose of reducing the specific on-resistance while increasing the breakdown voltage. On the other hand, the present invention can avoid the current edge collection effect at the edge of the drain electrode, making the power device not easily thermally broken down. On the other hand, the present invention can also increase the density of cells in the chip, thereby increasing the area utilization of the entire chip, and correspondingly achieving the purpose of increasing the total current density.

[0009] The second aspect of the present invention provides a method for preparing a fully vertical gallium nitride accumulation-mode power device. The process of the preparation method is relatively simple and easy to implement, and the prepared product can achieve the above-mentioned purpose.

[0010] To achieve the above purpose, the technical solution adopted by the present invention is as follows:

[0011] The first aspect of the present invention provides a fully vertical gallium nitride accumulation-mode power device, comprising a drain electrode, a substrate layer, a buffer layer, a heavily doped GaN lower transmission layer and a lightly doped GaN drift layer arranged in sequence from bottom to top, characterized in that:

[0012] The upper surface of the lightly doped GaN drift layer is respectively provided with a heavily doped GaN upper transmission layer, a termination ring and a protective layer, the heavily doped GaN upper transmission layer is located in the middle of the lightly doped GaN drift layer, the termination ring is symmetrically arranged at both ends of the lightly doped GaN drift layer, and the protective layer is symmetrically arranged between the termination ring and the heavily doped GaN upper transmission layer; and a plurality of grooves extending to the lightly doped GaN drift layer are uniformly opened downward from the upper surface of the heavily doped GaN upper transmission layer, the width and depth of all the grooves are the same, and the spacing between adjacent grooves is the same; the grooves include gate grooves, source grooves and electric field optimization grooves, the gate grooves are all located between the source grooves, and the source grooves are all located between the electric field optimization grooves; a gate electrode is wrapped in the gate groove by an oxide layer, an oxide layer covering the groove bottom and the groove wall is provided in the source groove, and the electric field optimization groove is completely filled with an electric field optimization layer;

[0013] A source electrode is provided above the heavily doped GaN upper transmission layer, the source electrode comprises a source plate and a source electrode head extending into the source trench, the source plate forms an ohmic contact with the heavily doped GaN upper transmission layer, and is connected to the termination ring through a protective layer, the lower part of the source plate covers the heavily doped GaN upper transmission layer, the electric field optimization layer and the oxide layer at the same time, and the upper part of the source plate extends to both sides respectively and forms a field plate structure that partially covers the protective layer;

[0014] The drain electrode includes a drain plate and a drain electrode head arranged on the drain plate. The drain plate is fixed on the substrate layer. The electrode drain head passes through the substrate layer and the buffer layer upward to form an ohmic contact with the lower surface of the heavily doped GaN lower transmission layer.

[0015] The cross section of the groove is a right-angled U-shaped structure or a rounded U-shaped structure.

[0016] The number of the electric field optimization grooves is an even number, and the electric field optimization grooves are symmetrically arranged on both sides of the source groove. The number of the source grooves is 2, and the number of the gate grooves is 4-20.

[0017] The width of the grooves is 0.5-2um, the depth is 0.5-2um, and the spacing between adjacent grooves is 0.5-1.5um.

[0018] The drain plate is a flat plate covering the lower surface of the substrate layer, and the drain electrode head is integrally formed on the upper surface of the drain plate.

[0019] The number of the drain electrode heads is one or more, and the drain electrode heads can be circular, square or polygonal.

[0020] Holes matching the drain electrode head are provided on the substrate layer and the buffer layer, and the drain electrode head forms an ohmic contact with the heavily doped GaN lower transmission layer through the hole.

[0021] The substrate layer is a Si substrate, a SiC substrate or a sapphire substrate. When the substrate layer is a Si substrate, the thickness of the substrate layer is 600-1000um; when the substrate layer is a SiC substrate, the thickness of the substrate layer is 350-600um; when the substrate layer is a sapphire substrate, the thickness of the substrate layer is 550-1000um.

[0022] The conductivity types of the heavily doped GaN upper transmission layer and the heavily doped GaN lower transmission layer are both N-type, and the doping concentrations of the heavily doped GaN upper transmission layer and the heavily doped GaN lower transmission layer are both 6 to 12×10 18 cm -3 , the doping concentration of the lightly doped GaN drift layer is 1~10×10 15 cm -3 .

[0023] A second aspect of the present invention provides a method for preparing a fully vertical gallium nitride accumulation-mode power device, which comprises the following steps:

[0024] S1: sequentially preparing a buffer layer, a heavily doped GaN lower transmission layer, a lightly doped GaN drift layer and a heavily doped GaN upper transmission layer on the substrate layer to obtain a device frame;

[0025] S2: Apply glue on the upper surface of the device frame of S1, remove the two side areas of the upper surface of the heavily doped GaN upper transmission layer by photolithography, retain the heavily doped GaN upper transmission layer in the middle, and retain the heavily doped GaN upper transmission layer at both ends as termination rings;

[0026] S3: A lower insulating dielectric layer and a semi-insulating polysilicon layer are sequentially grown on the upper surface of the device frame of S2; then, glue is applied on the semi-insulating polysilicon layer, and the heavily doped GaN upper transmission layer and the lower insulating dielectric layer and the semi-insulating polysilicon layer directly above the termination ring are removed by photolithography;

[0027] S4: depositing a mask layer on the upper surface of the device frame of S3, applying glue on the mask layer, and evenly forming a plurality of groove etching windows just above the heavily doped GaN upper transmission layer by photolithography, and sequentially etching the mask layer, the heavily doped GaN upper transmission layer, and part of the lightly doped GaN drift layer by using the groove etching windows, and obtaining grooves extending downward from the upper surface of the heavily doped GaN upper transmission layer to the lightly doped GaN drift layer after etching; the width and depth of all the grooves are the same, and the spacing between adjacent grooves is the same; the grooves include gate grooves, source grooves, and electric field optimization grooves, the gate grooves are all located between the source grooves, and the source grooves are all located between the electric field optimization grooves;

[0028] S5: depositing an oxide layer on the upper surface of the device frame of S4, the oxide layer also covers the exposed area of ​​the device frame, and then growing a filling dielectric layer on the oxide layer, the filling dielectric layer completely fills the gate trench, the source trench and the electric field optimization trench, and then applying glue on the filling dielectric layer, and removing the filling dielectric layer in the gate trench and the source trench by photolithography and etching, after which the oxide layer on the semi-insulating polysilicon layer and the filling dielectric layer jointly form an upper insulating dielectric layer, and the oxide layer in the electric field optimization trench and the filling dielectric layer jointly form an electric field optimization layer;

[0029] S6: depositing metal in the gate trench to prepare a gate electrode, depositing metal in the source trench to prepare a source electrode head, etching away all the metal outside the trench by applying glue and photolithography, and depositing an oxide layer to wrap the gate electrode and the source electrode head; applying glue on the oxide layer, and etching away the oxide layer except for the area above the gate electrode and the electric field optimization layer outside the electric field optimization trench by photolithography; then depositing a source plate connected to the source electrode head in the middle of the upper surface of the device frame to form a source electrode, annealing, and forming an ohmic contact between the source electrode and the heavily doped GaN upper transmission layer;

[0030] S7: Holes are etched on the substrate layer and the buffer layer of the device frame of S6 by photolithography, a drain electrode head is deposited in the hole to form an ohmic contact with the heavily doped GaN lower transmission layer, and a drain plate is deposited on the lower surface of the substrate layer to form a drain electrode. After completion, a fully vertical gallium nitride accumulation-type power device is obtained.

[0031] In the above S7, the substrate layer needs to be thinned before etching the holes. The thickness of the substrate layer before thinning is 1000 um, and the thickness of the substrate layer after thinning is 550-650 um.

[0032] The advantages of adopting the present invention are:

[0033] 1. The fully vertical GaN accumulation-type power device provided by the present invention has two key innovations, among which:

[0034] The first innovation is that an edge electric field optimization structure is constructed separately on the left and right sides of the gate electrode. The edge electric field optimization structure includes a source trench and an electric field optimization trench with the same width, depth and adjacent spacing as the gate trench, as well as a source electrode head arranged in the source trench and an electric field optimization layer completely filled in the electric field optimization trench. According to this specific edge electric field optimization structure, when in use, it can effectively alleviate the peak electric field formed by the corners of the gate trench on the left and right sides, and can effectively reduce the positive charge generated by the depletion of the drift region, thereby reducing the extended electric field lines, and then reducing the overall electric field, which not only avoids electric field concentration, but also effectively optimizes the edge electric field peak and improves the withstand voltage.

[0035] It should be noted that when a large reverse voltage is applied between the source and drain of the device, the voltage spikes are mostly concentrated at the corners of the gate grooves at the left and right ends (such as the left corner of the leftmost gate groove and the right corner of the rightmost gate groove), and such current spikes will cause the electric field to be concentrated in a certain area, causing the device to break down. Since the gate groove is surrounded by a lightly doped GaN drift layer, positive charges will be generated after the drift layer is exhausted, thereby having more current lines, making the concentrated electric field higher. The present invention can reduce the generation of positive charges and effectively share the electric field of the edge gate groove by cooperating with the source grooves and corresponding source electrode heads and electric field optimization grooves and corresponding electric field optimization layers that are separately set on both sides of the gate groove, so that the voltage at the electric field concentration point is diluted, and the electric field concentration is effectively alleviated, thereby achieving the effect of increasing the breakdown voltage.

[0036] It should also be noted that if the width, depth and adjacent spacing of the trenches are not the same, the peak electric field at the corners of the corner gate trenches cannot be effectively alleviated, thereby affecting the voltage resistance of the device.

[0037] The second innovation is to set the drain electrode on the lower surface of the substrate layer corresponding to the source electrode. This structure makes the drain electrode and the source electrode respectively located on the two corresponding sides of the power device, and the drain is mainly composed of a structure of a drain plate and a drain electrode head. On the one hand, it makes the power device have only a longitudinal current path but no lateral current path, so it can effectively shorten the current path and increase the current density. Correspondingly, the power device can have a smaller on-resistance, and there will be no warping or cracking problems, which is more conducive to improving the quality and performance of the product. On the other hand, even if the applied voltage is large and the current passing through is large, the current edge collection effect is not easy to occur at the edge of the drain electrode, and accordingly, the power device is not easy to be thermally broken down. On the other hand, when the power device is used in a chip, it is also necessary to set a terminal structure (protective layer) of corresponding length between each cell structure, which also correspondingly increases the density of the cell, not only improving the area utilization of the entire chip, but also improving the total current density of the chip.

[0038] In summary, the present invention combines the above two key innovative points, which not only enables the power device to have the excellent effect of increasing the breakdown voltage while reducing the specific on-resistance, but also can reduce heat and avoid thermal breakdown of the power device, while also having excellent blocking characteristics.

[0039] 2. The process of the preparation method of the present invention is relatively simple and easy to implement, and the prepared product can achieve the advantages of the above-mentioned full vertical gallium nitride accumulation-type power device, which will not be elaborated.

[0040] 3. The cross section of the groove in the present invention can be a right-angled U-shaped structure or a rounded U-shaped structure, which has the advantage of a wide range of applications.

[0041] 4. The present invention limits the number of electric field optimization grooves, source grooves and gate grooves. By configuring different grooves and corresponding electric field optimization layers and source electrode head structures, the present invention can achieve the best electric field optimization effect for power devices with different current specifications.

[0042] 5. The present invention defines the electric field optimization layer and the source electrode head through grooves, which is not only conducive to further improving the electric field optimization effect, but also conducive to improving the gate control capability of the device.

[0043] 6. The present invention adopts a drain structure formed by combining a drain plate and a drain electrode head. On the one hand, it has the advantages of being easy to implement and reducing the difficulty of preparation. On the other hand, it is helpful to prevent the power device from warping and cracking, thereby ensuring better quality and performance of the power device.

[0044] 7. The drain electrode of the present invention may adopt one or more drain electrode heads of different shapes, which is beneficial to ensure better conductive effect in specific application scenarios.

[0045] 8. The present invention realizes ohmic contact between the drain electrode head and the heavily doped GaN lower transmission layer through the hole, which can not only use the drain electrode head to fill the hole, but also help to improve the reliability of the device, and at the same time can prevent the device from warping and cracking.

[0046] 9. The present invention can select Si substrates, SiC substrates or sapphire substrates of different thicknesses according to working conditions, which is beneficial to reducing device costs and improving device performance.

[0047] 10. The present invention uses N-type heavily doped GaN upper transmission layer and heavily doped GaN lower transmission layer, which is conducive to further reducing the process difficulty. In addition, the doping concentration of the heavily doped GaN upper transmission layer and the heavily doped GaN lower transmission layer is set to 6-12×10 18 cm -3 , which can ensure that the current density is large enough to form a current path; the doping concentration of the lightly doped GaN drift layer is set to 1~10×10 15 cm -3 , which helps the device achieve a balance between on-resistance and breakdown voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 It is a schematic diagram of the planar structure of the present invention;

[0049] Figure 2 It is a structural schematic diagram of step S1;

[0050] Figure 3 It is a schematic diagram of the structure after gluing in step S2;

[0051] Figure 4 A schematic diagram of the structure of etching away the heavily doped GaN upper transmission layer on both sides and retaining the termination ring in step S2;

[0052] Figure 5 It is a structural diagram of step S3;

[0053] Figure 6 It is a schematic diagram of the structure before the photolithography in step S4;

[0054] Figure 7 It is a schematic diagram of the structure after photolithography in step S4;

[0055] Figure 8 It is a schematic diagram of the structure after the isolation layer is deposited in step S5;

[0056] Fig. 9 It is a schematic diagram of the structure after depositing a filling dielectric layer in step S5;

[0057] Fig.10 A schematic diagram of the structure of depositing source metal in step S6;

[0058] Fig.11 This is a simulation test diagram of the specific on-resistance of a power device with a breakdown voltage of 1.2K according to the present invention;

[0059] Fig.12 This is a simulation test diagram of the specific on-resistance of a power device with a breakdown voltage of 1.3K according to the present invention;

[0060] Fig.13 This is a simulation test diagram of the specific on-resistance of a power device with a breakdown voltage of 1.4K according to the present invention;

[0061] Fig.14 This is a simulation test diagram of the electric field distribution of a power device with a breakdown voltage of 1.2K at 1.2KV according to the present invention;

[0062] Fig.15 This is a simulation test diagram of the electric field distribution of a power device with a breakdown voltage of 1.3K at 1.3KV according to the present invention;

[0063] Fig.16 This is a simulation test diagram of the electric field distribution of a power device with a breakdown voltage of 1.4K at 1.4KV according to the present invention;

[0064] Fig.17 It is a simulation diagram of the drain electrode current edge collection effect of the power device of the present invention;

[0065] Fig.18This is a simulation diagram of the drain electrode current crowding effect of the existing quasi-vertical gallium nitride accumulation-type power device.

[0066] The markings in the figure are: 1-1, substrate layer, 1-2, buffer layer, 1-3, heavily doped GaN lower transmission layer, 1-4, lightly doped GaN drift layer, 1-5, lower insulating dielectric layer, 1-6, semi-insulating polysilicon layer, 1-7, upper insulating dielectric layer, 1-8, electric field optimization layer, 1-9, gate electrode, 1-10, heavily doped GaN upper transmission layer, 1-11, source electrode, 1-12, gate trench, 1-13, electric field optimization trench, 1-14, mask layer, 1-15, drain electrode, 1-16, isolation layer, 1-17, filling dielectric layer, 1-18, termination ring, 1-19, source trench, 1-20, source plate, 1-21, source electrode head, 1-22, drain plate, 1-23 drain electrode head.

[0067] 1.1, substrate layer, 1.2, buffer layer, 1.3, heavily doped GaN lower transmission layer, 1.4, lightly doped GaN drift layer, 1.5, lower insulating dielectric layer, 1.6, semi-insulating polysilicon layer, 1.7, upper insulating dielectric layer, 1.8, electric field optimization layer, 1.9, gate electrode, 1.10, heavily doped GaN upper transmission layer, 1.11, source electrode, 1.12, gate trench, 1.13, electric field optimization trench, 1.14, mask layer, 1.15, drain electrode, 1.16, isolation layer, 1.17, filling dielectric layer, 1.18, termination ring, 1.19, source trench, 1.20, source plate, 1.21, source electrode head, 1.22, drain plate, 1.23, drain electrode head. DETAILED DESCRIPTION

[0068] Example 1

[0069] This embodiment provides a full vertical GaN accumulation-type power device, such as Figure 1 As shown, the power device includes a drain electrode 1.15, a substrate layer 1.1, a buffer layer 1.2, a heavily doped GaN lower transmission layer 1.3 and a lightly doped GaN drift layer 1.4 arranged in sequence from bottom to top.

[0070] The upper surface of the lightly doped GaN drift layer 1.4 is provided with a heavily doped GaN upper transmission layer 1.10, a termination ring 1.18 and a protective layer. The heavily doped GaN upper transmission layer 1.10 is located in the middle of the lightly doped GaN drift layer 1.4. The termination rings 1.18 are symmetrically arranged at both ends of the lightly doped GaN drift layer 1.4. There is a gap between the heavily doped GaN upper transmission layer 1.10 and the termination rings 1.18 at both ends. The protective layer is symmetrically arranged between the termination rings 1.18 and the heavily doped GaN upper transmission layer 1.10. The protective layer includes a lower insulating dielectric layer 1.5, a semi-insulating polysilicon layer 1.6 and an upper insulating dielectric layer 1.7 which are sequentially fixed on the lightly doped GaN drift layer 1.4. The protective layer completely covers the gap between the heavily doped GaN upper transmission layer 1.10 and the termination ring 1.18. Among them,

[0071] The semi-insulating polysilicon layer 1.6 can optimize the surface electric field and make the electric field more uniform, which is beneficial to improving the stability of the power device and shortening the length of the withstand voltage region of the surface electric field, thereby effectively reducing the chip area and improving reliability. The upper insulating dielectric layer 1.7 can be made of Al 2 O 3 , SiN or SiO 2 The lower insulating dielectric layer 1.5 can be made of Al 2 O 3 , SiN or SiO 2 The upper insulating dielectric layer 1.7 and the lower insulating dielectric layer 1.5 can play the role of insulating protection and buffering for the semi-insulating polysilicon layer 1.6.

[0072] Furthermore, a plurality of grooves extending downward to the lightly doped GaN drift layer 1.4 are uniformly opened from the upper surface of the heavily doped GaN upper transport layer 1.10, the width and depth of all the grooves are the same, and the spacing between adjacent grooves is the same; the grooves include gate grooves 1.12, source grooves 1.19 and electric field optimization grooves 1.13, the gate grooves 1.12 are all located between the source grooves 1.19, and the source grooves 1.19 are all located between the electric field optimization grooves 1.13; the gate electrode 1.9 is wrapped in the gate groove 1.12 by an oxide layer, the source groove 1.19 is provided with an oxide layer covering the bottom and the wall of the groove, and the electric field optimization groove 1.13 is completely filled with the electric field optimization layer 1.8, that is, the electric field optimization layer 1.8 fills the electric field optimization groove 1.13. The height of the oxide layer wrapping the gate electrode 1.9 exceeds the upper surface of the heavily doped GaN upper transmission layer 1.10, while the height of the electric field optimization layer 1.8 filling the electric field optimization groove 1.13 is flush with the upper surface of the heavily doped GaN upper transmission layer 1.10.

[0073] A source electrode 1.11 is provided above the heavily doped GaN upper transport layer 1.10. The source electrode 1.11 includes a source plate 1.20 and a source electrode head 1.21 fixedly connected to the source plate 1.20 and extending into the source groove 1.19. The source plate 1.20 forms an ohmic contact with the heavily doped GaN upper transport layer 1.10 and is connected to the termination ring 1.18 through a protective layer. The lower part of the source plate 1.20 simultaneously covers the heavily doped GaN upper transport layer 1.10, the electric field optimization layer 1.8 and the oxide layer. The upper part of the source plate 1.20 extends to both sides respectively and forms a field plate structure that partially covers the protective layer.

[0074] Based on the above-mentioned specific structure of the source trench 1.19 and the electric field optimization trench 1.13, as well as the source electrode head 1.21 correspondingly arranged in the source trench 1.19 and the electric field optimization layer 1.8 in the electric field optimization trench 1.13, it is possible to effectively share the load. Figure 1 The electric field of the edge peaks generated by the left corner of the leftmost gate trench 1.12 and the right corner of the rightmost gate trench 1.12 dilutes the voltage at the electric field concentration point, thereby effectively alleviating the electric field concentration and achieving the effect of increasing the breakdown voltage.

[0075] The drain electrode 1.15 includes a drain plate 1.22 and a drain electrode head 1.23 disposed on the upper surface of the drain plate 1.22. The drain plate 1.22 is a flat plate fixedly covering the lower surface of the substrate layer 1.1. The area of ​​the drain plate 1.22 is preferably the same as the area of ​​the substrate layer 1.1, which is convenient for preparation, can effectively prevent warping and cracking, and is also convenient for heat dissipation. The electrode drain head is integrally formed on the upper surface of the drain plate 1.22, and the drain electrode head 1.23 passes through the substrate layer 1.1 and the buffer layer 1.2 upwards to form an ohmic contact with the lower surface of the heavily doped GaN lower transmission layer 1.3.

[0076] It should be noted that the above-mentioned termination ring 1.18 is formed by the heavily doped GaN upper transmission layer 1.10 disposed on the lightly doped GaN drift layer 1.4, and the portions retained at both ends after photolithography. The function of the termination ring 1.18 is to connect to the source electrode 1.11 through the semi-insulating polysilicon layer 1.6, and to the drain electrode 1.15 through the lightly doped GaN drift layer 1.4 and the heavily doped GaN lower transmission layer 1.3.

[0077] According to a preferred implementation of this embodiment, the cross-section of all grooves is a right-angled U-shaped structure or a rounded U-shaped structure, that is, the corners of the grooves are right-angled structures or rounded structures. However, the grooves can also be made into structures of other shapes as needed.

[0078] Further, the number of the electric field optimization grooves 1.13 is an even number, and the electric field optimization grooves 1.13 are symmetrically arranged on both sides of the source groove 1.19. The number of the electric field optimization grooves 1.13 can be optimized and adjusted according to the withstand voltage level. When the number of the electric field optimization grooves 1.13 is 2, the electric field optimization grooves 1.13 are located at the leftmost and rightmost ends of all the grooves; when the number of the electric field optimization grooves 1.13 is 4, 6 or more, each electric field optimization groove 1.13 is symmetrically arranged on both sides of all the source grooves 1.19. The number of source grooves 1.19 is 2, the number of gate grooves 1.12 is 4-10, and all gate grooves 1.12 are located between two source grooves 1.19. The specific number of gate trenches 1.12 can be optimized according to the current level, for example, it can be 4, 6, 8, 11, 13, 15, 20, etc., which is conducive to the preparation of power devices with different current requirements.

[0079] Furthermore, the width of all grooves is 0.5-2um, the depth is 0.5-2um, and the spacing between adjacent grooves is 0.5-1.5um. Preferably, the width of all grooves is 1.2um, the depth is 1.2um, and the spacing between adjacent grooves is 1um. This can enable the power device to have a better electric field optimization effect and better gate control capability.

[0080] According to another preferred implementation of this embodiment, Figure 1 As shown, the number of drain electrode heads 1.23 can be one or more (including two), and the drain electrode heads 1.23 can be circular, square or polygonal. Accordingly, holes matching the drain electrode heads 1.23 are provided on the substrate layer 1.1 and the buffer layer 1.2, and the drain electrode heads 1.23 form ohmic contact with the heavily doped GaN lower transmission layer 1.3 through the holes. When there is one drain electrode head 1.23, a hole can be directly punched between the substrate layer 1.1 and the buffer layer 1.2; when there are two drain electrode heads 1.23, the holes can be directly punched between the substrate layer 1.1 and the buffer layer 1.2. Figure 1 The structure shown has holes punched on the left and right sides of the substrate layer 1.1 and the buffer layer 1.2 so that the drain electrode heads 1.23 are distributed on the left and right; when there are multiple drain electrode heads 1.23, holes can be punched at equal intervals so that the drain electrode heads 1.23 are evenly arranged.

[0081] According to another preferred implementation of this embodiment, the substrate layer 1.1 may be a Si substrate, a SiC substrate or a sapphire substrate. Furthermore, when the substrate layer 1.1 is a Si substrate, the thickness of the substrate layer 1.1 is 600-1000um; when the substrate layer 1.1 is a SiC substrate, the thickness of the substrate layer 1.1 is 350-600um; when the substrate layer 1.1 is a sapphire substrate, the thickness of the substrate layer 1.1 is 550-1000um.

[0082] Further, when a SiC substrate is used, the thickness of the substrate layer 1.1 is preferably 500um, which can make the substrate layer 1.1 have higher thermal conductivity and thermal stability at a moderate cost. When a sapphire substrate is used, the thickness of the substrate layer 1.1 is preferably 750um, which can make the substrate layer 1.1 have higher thermal stability at a reduced cost. When a Si substrate is used, the thickness of the substrate layer 1.1 is preferably 800um, which can make the substrate layer 1.1 have higher thermal conductivity at a further reduced cost.

[0083] According to another preferred implementation of this embodiment, the conductivity type of the heavily doped GaN upper transmission layer 1.10 and the heavily doped GaN lower transmission layer 1.3 are both N-type, which is conducive to further reducing the difficulty of the process. The doping concentration of the heavily doped GaN upper transmission layer 1.10 and the heavily doped GaN lower transmission layer 1.3 is 6 to 12×10 18 cm -3 , the doping concentration of the lightly doped GaN drift layer 1.4 is 1~10×10 15 cm -3 Preferably, the doping concentration of the heavily doped GaN upper transmission layer 1.10 and the heavily doped GaN lower transmission layer 1.3 are both 9×10 18 cm -3 The doping concentration of the lightly doped GaN drift layer 1.4 is 5×10 15 cm -3 , which helps the device achieve the best balance between on-resistance and breakdown voltage.

[0084] The working principle of this embodiment is:

[0085] Because the gate trench 1.12 and the lightly doped GaN drift layer 1.4 have a work function difference, a depletion region is formed near the semiconductor side. Then, by adjusting the potential difference between the source electrode 1.11 and the gate electrode 1.9, the depletion region between the two gate trenches 1.12 can be controlled to determine whether the channel is turned off or on. By changing the depth, width, and spacing between adjacent gate trenches 1.12 of the gate trench 1.12, the threshold voltage of the device can be effectively changed, thereby realizing an enhancement-type device and a depletion-type device under different environments. When a voltage is applied and the potential difference between the gate trench 1.12 and the source electrode 1.11 is greater than the threshold voltage, the channel is opened, and electrons flow in from the source electrode 1.11, passing through the heavily doped GaN upper transmission layer 1.10, the lightly doped GaN drift layer 1.4, and the heavily doped GaN lower transmission layer 1.3 in turn, and finally being collected at the drain electrode 1.15, and finally flowing back to the surface of the power device, thereby forming a current path, and the entire device is turned on. When the potential difference between the gate trench 1.12 and the source electrode 1.11 is less than the turn-on voltage, the channel of the device is turned off and the entire device is in a closed state. When a reverse voltage is applied to the drain electrode 1.15, the semi-insulating polysilicon layer 1.6 is connected to the source electrode 1.11, introducing a uniform lateral electric field, thereby realizing the field plate effect and increasing the withstand voltage of the device. In addition, source trenches 1.19 and electric field optimization trenches 1.13 are configured on both sides of the gate trench 1.12, which can avoid the depletion of the lightly doped GaN drift region and generate excess positive charges, thereby reducing the extended electric lines, achieving the purpose of reducing the electric field and increasing the breakdown voltage. Under the condition of the same on-resistance, the breakdown voltage of this structure is significantly higher.

[0086] In summary, in the above process, the present invention cooperates with the edge electric field optimization structure independently constructed at the left and right ends of the gate electrode 1.9 and the structure in which the drain electrode 1.15 is set on the lower surface of the substrate layer 1.1, which not only enables the power device to have the excellent effect of reducing the specific on-resistance while increasing the breakdown voltage, but also can reduce heat and avoid thermal breakdown of the power device, while also having excellent blocking characteristics.

[0087] Example 2

[0088] This embodiment provides a method for preparing a fully vertical gallium nitride accumulation-mode power device, which comprises the following steps:

[0089] S1: First, a buffer layer 1.2 is deposited on the upper surface of the substrate layer 1.1, and then a heavily doped GaN lower transmission layer 1.3 is prepared on the upper surface of the buffer layer 1.2, and then a lightly doped GaN drift layer 1.4 and a heavily doped GaN upper transmission layer 1.10 are sequentially prepared on the upper surface of the heavily doped GaN lower transmission layer 1.3 by metal organic chemical vapor deposition, to obtain Figure 2 The device frame is shown.

[0090] S2: Figure 3 As shown, glue is applied on the upper surface of the heavily doped GaN upper transmission layer 1.10 of the device frame obtained by S1, and the two side regions of the upper surface of the heavily doped GaN upper transmission layer 1.10 are removed by photolithography, and the heavily doped GaN upper transmission layer 1.10 located in the middle is retained, and the partially heavily doped GaN upper transmission layer 1.10 located at both ends is retained to form a termination ring 1.18. The structure after photolithography is as shown Figure 4 As shown, at this time, bare areas are formed between the heavily doped GaN upper transmission layer 1.10 and the termination ring 1.18.

[0091] S3: On the upper surface of the device frame obtained by S2, a lower insulating dielectric layer 1.5 and a semi-insulating polysilicon layer 1.6 are sequentially grown; then, glue is applied on the semi-insulating polysilicon layer 1.6, and the lower insulating dielectric layer 1.5 and the semi-insulating polysilicon layer 1.6 directly above the heavily doped GaN upper transmission layer 1.10 and the termination ring 1.18 are removed by photolithography, and the following is obtained after photolithography: Figure 5 As shown, the device frame has only the insulating dielectric layer 1.5 and the semi-insulating polysilicon layer 1.6 retained directly above the exposed area.

[0092] S4: Figure 6 As shown, a mask layer 1.14 is deposited on the upper surface of the device frame obtained by S3, and then a glue is applied on the mask layer 1.14 and multiple groove etching windows are uniformly formed just above the heavily doped GaN upper transmission layer 1.10 by photolithography, and then the mask layer 1.14, the heavily doped GaN upper transmission layer 1.10 and part of the lightly doped GaN drift layer 1.4 are etched away in sequence by using the groove etching windows, and after etching, the following is obtained: Figure 7 The upper surface of the self-heavily doped GaN upper transport layer 1.10 is shown extending downward to the trench of the lightly doped GaN drift layer 1.4.

[0093] It should be noted that the width and depth of all the above-mentioned grooves are the same, and the spacing between adjacent grooves is the same; the above-mentioned grooves include gate grooves 1.12, source grooves 1.19 and electric field optimization grooves 1.13, and the gate grooves 1.12 are all located between the source grooves 1.19, and the source grooves 1.19 are all located between the electric field optimization grooves 1.13. In addition, the number of electric field optimization grooves 1.13 is preferably 2, the number of source grooves 1.19 is 2, and the number of gate grooves 1.12 is preferably 6.

[0094] S5: Figure 8As shown, an oxide layer is first deposited on the upper surface of the device frame obtained by S4, and the oxide layer also covers the exposed area on the upper surface of the device frame, specifically covers the upper surface of the termination ring 1.18, the heavily doped GaN upper transmission layer 1.10 and the semi-insulating polysilicon layer 1.6, and also covers the bottom and wall of all the grooves. Fig. 9 As shown, a filling dielectric layer 1.17 is grown on the oxide layer, and the filling dielectric layer 1.17 completely fills the gate trench 1.12, the source trench 1.19 and the electric field optimization trench 1.13. Then, glue is coated on the filling dielectric layer 1.17, and the filling dielectric layer 1.17 in the gate trench 1.12 and the source trench 1.19 is removed by photolithography. After photolithography, the oxide layer on the semi-insulating polysilicon layer 1.6 and the filling dielectric layer 1.17 jointly form an upper insulating dielectric layer 1.7, and the oxide layer in the electric field optimization trench 1.13 and the filling dielectric layer 1.17 jointly form an electric field optimization layer 1.8.

[0095] S6: Fig.10 As shown, metal is deposited in the gate groove 1.12 of the device frame obtained by S5 to prepare a gate electrode 1.9, and metal is deposited in the source groove 1.19 to prepare a source electrode head 1.21. The metal outside the groove is completely etched away by coating and photolithography, and an oxide layer is deposited to wrap the gate electrode 1.9 and the source electrode head 1.21; then, glue is coated on the top of the oxide layer, and the oxide layer except for the top of the gate electrode 1.9 and the electric field optimization layer 1.8 outside the electric field optimization groove 1.13 are etched away by photolithography; then, a source plate 1.20 connected to the source electrode head 1.21 is deposited in the middle of the upper surface of the device frame to form a source electrode 1.11, and annealing is performed to form an ohmic contact between the source electrode 1.11 and the heavily doped GaN upper transmission layer 1.10.

[0096] It should be noted that the above-mentioned source plate 1.20 forms an ohmic contact with the heavily doped GaN upper transmission layer 1.10, and is connected to the termination ring 1.18 through the semi-insulating polysilicon layer 1.6. The lower part of the source plate 1.20 covers the heavily doped GaN upper transmission layer 1.10, the electric field optimization layer 1.8 and the oxide layer at the same time, and the upper part of the source plate 1.20 extends to both sides respectively and forms a field plate structure that partially covers the protective layer.

[0097] S7: A hole matching the drain electrode head 1.23 is etched by photolithography on the substrate layer 1.1 and the buffer layer 1.2 of the device frame obtained by S6, and a drain electrode head 1.23 is deposited in the hole to form an ohmic contact with the heavily doped GaN lower transmission layer 1.3, and a drain plate 1.22 is deposited on the lower surface of the substrate layer 1.1 to form a drain electrode 1.15. After completion, the following is obtained: Figure 1 The fully vertical GaN accumulation-mode power device shown.

[0098] It should be noted that the thickness of the raw material substrate layer 1.1 is usually 1000um, which is relatively thick. Therefore, the substrate layer 1.1 needs to be thinned before etching the holes. The thickness of the substrate layer 1.1 after thinning is 550-650um, and preferably the thickness of the substrate layer 1.1 after thinning is 550um.

[0099] It should also be noted that the preparation method can prepare the full vertical gallium nitride accumulation-type power device of Example 1. Based on the same innovative concept, the relevant technical features and implementation methods involved in each step of this example can be referred to Example 1, and the repeated parts will not be repeated.

[0100] Comparative Experimental Example

[0101] The drain electrode 1.15 is arranged on the lower surface of the substrate layer 1.1, and the left and right sides of the gate trench 1.12 are only provided with an electric field optimization layer 1.8 through the electric field optimization trench 1.13, while a power device without a passive trench 1.19 and a corresponding source electrode head 1.21 is used as comparative experiment 1.

[0102] A power device in which the drain electrode 1.15 is arranged on the lower surface of the substrate layer 1.1, the left and right sides of the gate trench 1.12 are only provided with corresponding source electrode heads 1.21 through the source trench 1.19, and there is no electric field optimization trench 1.13 and electric field optimization layer 1.8 is used as comparative experiment 2.

[0103] A power device in which the drain electrode 1.15 is arranged on the lower surface of the substrate layer 1.1 and there is no source trench 1.19, source electrode head 1.21, electric field optimization trench 1.13 and electric field optimization layer 1.8 on both sides of the gate trench 1.12 is used as comparative experiment 3.

[0104] In this experimental test, the power device of Example 1 of the present invention and the power devices of Comparative Experiments 1-3 were subjected to simulation test of specific on-resistance and electric field distribution test at voltages of 1.2KV, 1.3KV and 1.4KV, respectively. Figure 12-14 The simulation diagrams of the breakdown voltage of the power device of Example 1 of the present invention at 1.2KV, 1.3KV and 1.4KV are respectively shown, Figure 15-17 The simulation diagrams of the electric field distribution of the power device of Example 1 of the present invention at 1.2KV, 1.3KV and 1.4KV are respectively shown. In addition, the corresponding breakdown voltage and specific on-resistance of the power devices of Comparative Experiments 1-3 at 1.2KV, 1.3KV and 1.4KV are also obtained through simulation. The specific simulation results are shown in Table 1 below:

[0105] Table 1

[0106]

[0107] Furthermore, the applicant also conducted a simulation test on the current edge collection effect of the power device of Example 1 of the present invention. The specific simulation diagram is as follows: Fig.17 shown.

[0108] It can be seen from the above experimental test results that the present invention, through the coordination of the edge electric field optimization structure independently constructed at the left and right ends of the gate electrode 1.9 and the structure in which the drain electrode 1.15 is set on the lower surface of the substrate layer 1.1, not only makes the power device have the excellent effect of reducing the specific on-resistance while increasing the breakdown voltage, but also can reduce heat and avoid thermal breakdown of the power device, and also has excellent blocking characteristics.

[0109] In addition, the quasi-vertical gallium nitride accumulation-type power device disclosed in the patent document with publication number CN117219672A discloses test data of the power device in Examples 1-5 of the specification, but it can be seen from the test data that while the breakdown voltage is increased, the specific on-resistance is also increased simultaneously, while the present invention can reduce the specific on-resistance while increasing the breakdown voltage, so the technical effect that can be achieved by the present invention is better.

[0110] The above description is only a specific implementation mode of the present invention. Any feature disclosed in this specification, unless otherwise stated, can be replaced by other equivalent or alternative features with similar purposes; all disclosed features, or all methods or steps in the process, except for mutually exclusive features and / or steps, can be combined in any way.

Claims

1. A fully vertical gallium nitride accumulation-type power device, comprising a drain electrode (1.15), a substrate layer (1.1), a buffer layer (1.2), a heavily doped GaN lower transmission layer (1.3) and a lightly doped GaN drift layer (1.4) arranged in sequence from bottom to top, characterized in that: The upper surface of the lightly doped GaN drift layer (1.4) is respectively provided with a heavily doped GaN upper transmission layer (1.10), a termination ring (1.18) and a protective layer; the heavily doped GaN upper transmission layer (1.10) is located in the middle of the lightly doped GaN drift layer (1.4); the termination ring (1.18) is symmetrically arranged at both ends of the lightly doped GaN drift layer (1.4); and the protective layer is symmetrically arranged between the termination ring (1.18) and the heavily doped GaN upper transmission layer (1.10); and a plurality of uniformly arranged downwardly extending from the upper surface of the heavily doped GaN upper transmission layer (1.10) to the lightly doped GaN drift layer (1.4) are provided. The grooves are all the same in width and depth, and the spacing between adjacent grooves is the same; the grooves include gate grooves (1.12), source grooves (1.19) and electric field optimization grooves (1.13); the gate grooves (1.12) are all located between the source grooves (1.19), and the source grooves (1.19) are all located between the electric field optimization grooves (1.13); the gate electrode (1.9) is wrapped in the gate groove (1.12) by an oxide layer, the source groove (1.19) is provided with an oxide layer covering the groove bottom and groove wall, and the electric field optimization groove (1.13) is completely filled with an electric field optimization layer (1.8); A source electrode (1.11) is provided above the heavily doped GaN upper transmission layer (1.10), the source electrode (1.11) comprising a source plate (1.20) and a source electrode head (1.21) extending into a source trench (1.19), the source plate (1.20) forming an ohmic contact with the heavily doped GaN upper transmission layer (1.10), and connected to a termination ring (1.18) via a protective layer, the lower portion of the source plate (1.20) simultaneously covering the heavily doped GaN upper transmission layer (1.10), the electric field optimization layer (1.8) and the oxide layer, the upper portion of the source plate (1.20) extending to both sides respectively and forming a field plate structure partially covering the protective layer; The drain electrode (1.15) comprises a drain plate (1.22) and a drain electrode head (1.23) arranged on the drain plate (1.22); the drain plate (1.22) is fixed on the substrate layer (1.1); the electrode drain head passes through the substrate layer (1.1) and the buffer layer (1.2) upwards to form an ohmic contact with the lower surface of the heavily doped GaN lower transmission layer (1.3).

2. The fully vertical GaN accumulation-mode power device according to claim 1, characterized in that: The cross section of the groove is a right-angled U-shaped structure or a rounded U-shaped structure.

3. A fully vertical gallium nitride accumulation-mode power device according to claim 1 or 2, characterized in that: The number of the electric field optimization grooves (1.13) is an even number, and the electric field optimization grooves (1.13) are symmetrically arranged on both sides of the source groove (1.19), the number of the source grooves (1.19) is 2, and the number of the gate grooves (1.12) is 4-20.

4. The fully vertical GaN accumulation-mode power device according to claim 3, characterized in that: The width of the grooves is 0.5-2um, the depth is 0.5-2um, and the spacing between adjacent grooves is 0.5-1.5um.

5. The fully vertical GaN accumulation-mode power device according to claim 1, characterized in that: The drain plate (1.22) is a flat plate covering the lower surface of the substrate layer (1.1), and the drain electrode head (1.23) is integrally formed on the upper surface of the drain plate (1.22).

6. The fully vertical GaN accumulation-mode power device according to claim 1, characterized in that: The number of the drain electrode heads (1.23) is one or more, and the drain electrode heads (1.23) can be circular, square or polygonal.

7. The fully vertical GaN accumulation-mode power device according to claim 6, characterized in that: Holes matching the drain electrode head (1.23) are provided on the substrate layer (1.1) and the buffer layer (1.2), and the drain electrode head (1.23) forms an ohmic contact with the heavily doped GaN lower transmission layer (1.3) through the hole.

8. The fully vertical GaN accumulation-mode power device according to claim 1, characterized in that: The substrate layer (1.1) is a Si substrate, a SiC substrate or a sapphire substrate. When the substrate layer (1.1) is a Si substrate, the thickness of the substrate layer (1.1) is 600-1000 um; when the substrate layer (1.1) is a SiC substrate, the thickness of the substrate layer (1.1) is 350-600 um; when the substrate layer (1.1) is a sapphire substrate, the thickness of the substrate layer (1.1) is 550-1000 um.

9. The fully vertical GaN accumulation-mode power device according to claim 1, characterized in that: The conductivity types of the heavily doped GaN upper transmission layer (1.10) and the heavily doped GaN lower transmission layer (1.3) are both N-type, and the doping concentrations of the heavily doped GaN upper transmission layer (1.10) and the heavily doped GaN lower transmission layer (1.3) are both 6 to 12×10 18 cm -3 , the doping concentration of the lightly doped GaN drift layer (1.4) is 1~10×10 15 cm -3 .

10. A method for preparing a fully vertical gallium nitride accumulation-mode power device, comprising the following steps: S1: sequentially preparing a buffer layer (1.2), a heavily doped GaN lower transmission layer (1.3), a lightly doped GaN drift layer (1.4) and a heavily doped GaN upper transmission layer (1.10) on a substrate layer (1.1) to obtain a device framework; S2: applying glue on the upper surface of the device frame of S1, removing the two side regions of the upper surface of the heavily doped GaN upper transmission layer (1.10) by photolithography, retaining the heavily doped GaN upper transmission layer (1.10) in the middle, and retaining the heavily doped GaN upper transmission layer (1.10) at both ends as termination rings (1.18); S3: growing a lower insulating dielectric layer (1.5) and a semi-insulating polysilicon layer (1.6) on the upper surface of the device frame of S2 in sequence; then applying glue on the semi-insulating polysilicon layer (1.6), and removing the heavily doped GaN upper transmission layer (1.10) and the lower insulating dielectric layer (1.5) and the semi-insulating polysilicon layer (1.6) directly above the termination ring (1.18) by photolithography; S4: a mask layer (1.14) is deposited on the upper surface of the device frame of S3, a glue is applied on the mask layer (1.14), and a plurality of groove etching windows are uniformly formed just above the heavily doped GaN upper transmission layer (1.10) by photolithography, and the mask layer (1.14), the heavily doped GaN upper transmission layer (1.10) and part of the lightly doped GaN drift layer (1.4) are etched away in sequence by using the groove etching windows, and a self-heavily doped GaN upper transmission layer ( 1.10) extends downward from the upper surface to the groove of the lightly doped GaN drift layer (1.4); the width and depth of all the grooves are the same, and the spacing between adjacent grooves is the same; the grooves include gate grooves (1.12), source grooves (1.19) and electric field optimization grooves (1.13), the gate grooves (1.12) are all located between the source grooves (1.19), and the source grooves (1.19) are all located between the electric field optimization grooves (1.13); S5: depositing an oxide layer on the upper surface of the device frame of S4, the oxide layer also covers the exposed area of ​​the device frame, then growing a filling dielectric layer (1.17) on the oxide layer, the filling dielectric layer (1.17) completely filling the gate trench (1.12), the source trench (1.19) and the electric field optimization trench (1.13), then applying glue on the filling dielectric layer (1.17), and removing the filling dielectric layer (1.17) in the gate trench (1.12) and the source trench (1.19) by photolithography, after which the oxide layer and the filling dielectric layer (1.17) on the semi-insulating polysilicon layer (1.6) together form an upper insulating dielectric layer (1.7), and the oxide layer and the filling dielectric layer (1.17) in the electric field optimization trench (1.13) together form an electric field optimization layer (1.8); S6: depositing metal in the gate groove (1.12) to prepare a gate electrode (1.9), depositing metal in the source groove (1.19) to prepare a source electrode head (1.21), etching away all the metal outside the groove by applying glue and photolithography, and depositing an oxide layer to wrap the gate electrode (1.9) and the source electrode head (1.21); applying glue on the oxide layer, and etching away the oxide layer except for the oxide layer above the gate electrode (1.9) and the electric field optimization groove (1.13) by photolithography; then depositing a source plate (1.20) connected to the source electrode head (1.21) in the middle of the upper surface of the device frame to form a source electrode (1.11), annealing, and forming an ohmic contact between the source electrode (1.11) and the heavily doped GaN upper transmission layer (1.10); S7: Holes are etched on the substrate layer (1.1) and the buffer layer (1.2) of the device frame of S6 by photolithography, a drain electrode head (1.23) is deposited in the hole to form an ohmic contact with the heavily doped GaN lower transmission layer (1.3), and a drain plate (1.22) is deposited on the lower surface of the substrate layer (1.1) to form a drain electrode (1.15). After completion, a fully vertical gallium nitride accumulation-type power device is obtained.

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