Semiconductor structure and method for manufacturing the same

Abstract

The present application relates to a semiconductor structure and a method for preparing the same. The method for preparing the semiconductor structure comprises: providing a substrate; forming a groove in the substrate; the upper surface of the substrate and the bottom surface of the groove are both the first crystal plane, and the sidewall of the groove is the second crystal plane; obtaining the growth ratio of the oxide layer of the first crystal plane and the second crystal plane under different growth temperature conditions; obtaining the second target thickness of the oxide layer required to be formed on the first crystal plane based on the first target thickness of the oxide layer required to be formed on the second crystal plane, the growth temperature and the growth ratio at the growth temperature; forming an oxide layer on the upper surface of the substrate, the bottom surface of the groove and the bottom of the groove until the thickness of the oxide layer on the first crystal plane reaches the second target thickness. The present application solves the problem that it is impossible to accurately judge whether the thickness of the Si(110) oxide layer reaches the target thickness based on the thickness of the oxide layer on the Si(100) crystal plane, resulting in a long development cycle and high manufacturing cost of the trench oxide layer, and has the advantage of improving the electrical properties and reliability of the semiconductor structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] The thickness of the sidewall oxide layer of the semiconductor trench structure directly affects the electrical properties and reliability of the semiconductor. For example, the sidewall oxide layer of the deep trench isolation structure (DTI) in the monolithic integration process (Bipolar-CMOS-DMOS, BCD) is used for isolation of high-voltage devices, and the sidewall oxide layer of the trench structure in discrete devices is used as the gate oxide layer. Since the oxidation rate of the trench sidewall oxide layer Si(110) is faster than the oxidation rate of the wafer surface and the trench bottom Si(100), the thickness of the Si(110) oxide layer is inconsistent with the thickness of the Si(100) oxide layer. The thickness of the Si(100) oxide layer is usually measured by ellipsometer. The thickness of the Si(110) oxide layer needs to be characterized by transmission electron microscopy (TEM) or scanning electron microscope (SEM) after the trench oxide layer is formed. Therefore, in the process of preparing the trench oxide layer, the thickness of the Si(100) oxide layer can only be measured to determine whether the thickness of the Si(110) oxide layer reaches the target thickness. However, the Si(100) / Si(110) crystal surface oxide layer growth ratio is affected by the oxidation temperature and oxidation method, which results in the inability to accurately judge whether the Si(110) oxide layer thickness has reached the target thickness based on the oxide layer thickness of the Si(100) crystal surface during the trench oxide layer preparation process. This increases the development cycle and production cost of the trench oxide layer, while affecting the electrical properties and reliability of the semiconductor structure. Summary of the invention

[0003] The purpose of the present application is to provide a semiconductor structure and a method for preparing the same, which solves the problem of long development cycle and high production cost of the trench oxide layer due to the inability to accurately determine whether the thickness of the Si (110) oxide layer has reached the target thickness, and has the advantage of improving the electrical properties and reliability of the semiconductor structure.

[0004] To achieve the purpose of this application, this application provides the following technical solutions:

[0005] In a first aspect, the present application provides a method for preparing a semiconductor structure, comprising:

[0006] providing a substrate;

[0007] A groove is formed in the substrate; the upper surface of the substrate and the bottom surface of the groove are both first crystal planes, and the sidewalls of the groove are second crystal planes;

[0008] Obtaining a growth ratio of the oxide layer of the first crystal plane to that of the second crystal plane under different growth temperature conditions;

[0009] Obtaining a second target thickness of the oxide layer to be formed on the first crystal plane based on a first target thickness of the oxide layer to be formed on the second crystal plane, a growth temperature, and a growth ratio at the growth temperature;

[0010] An oxide layer is formed on the upper surface of the substrate, the bottom surface of the trench and the bottom of the trench until the thickness of the oxide layer on the first crystal plane reaches the second target thickness.

[0011] The method for preparing the semiconductor structure of the present application obtains the growth ratio of the oxide layer of the first crystal plane and the second crystal plane under different growth temperature conditions, obtains the second target thickness of the oxide layer to be formed on the first crystal plane based on the first target thickness of the oxide layer to be formed on the second crystal plane, the growth temperature and the growth ratio at the growth temperature, and then forms an oxide layer on the upper surface of the substrate, the bottom surface of the groove and the bottom of the groove until the thickness of the oxide layer on the first crystal plane reaches the second target thickness. The method solves the problem that it is impossible to accurately judge whether the thickness of the Si(110) oxide layer reaches the target thickness based on the thickness of the oxide layer on the Si(100) crystal plane, resulting in a long development cycle and high production cost for the trench oxide layer, and has the advantage of improving the electrical properties and reliability of the semiconductor structure.

[0012] In one embodiment, the first crystal plane includes a (100) crystal plane, and the second crystal plane includes a (110) crystal plane.

[0013] In one embodiment, a thermal oxidation process is used to form the oxide layer on the upper surface of the substrate, the bottom surface of the trench and the bottom of the trench.

[0014] In one embodiment, obtaining the growth ratio of the oxide layer of the first crystal plane to that of the second crystal plane under different growth temperature conditions includes:

[0015] Based on the oxide layer thickness of the first crystal plane of the test substrate and the oxide layer thickness of the second crystal plane of the test substrate under each growth temperature condition, a growth ratio of the oxide layer of the first crystal plane to that of the second crystal plane under different growth temperature conditions is obtained, wherein the oxide layer thickness of the first crystal plane is different from the oxide layer thickness of the second crystal plane under the same growth temperature condition.

[0016] In one embodiment, an ellipsometer is used to measure the thickness of the oxide layer on the first crystal surface under each growth temperature condition; a scanning electron microscope or a transmission electron microscope is used to measure the thickness of the oxide layer on the second crystal surface under each growth temperature condition.

[0017] In one embodiment, obtaining the second target thickness of the oxide layer required to be formed on the first crystal plane based on the first target thickness of the oxide layer required to be formed on the second crystal plane, the growth temperature, and the growth ratio at the growth temperature includes:

[0018] estimating the estimated thickness of the oxide layer required to be formed on the first crystal plane based on a first target thickness of the oxide layer required to be formed on the second crystal plane, a growth temperature, and a growth ratio at the growth temperature;

[0019] providing an experimental substrate, the experimental substrate being the same as the substrate;

[0020] An experimental groove is formed in the experimental substrate, wherein the experimental groove and the groove are formed by the same dry etching process; the upper surface of the experimental substrate and the bottom surface of the experimental groove are both first crystal planes, and the sidewalls of the experimental groove are second crystal planes;

[0021] forming an oxide layer on the upper surface of the experimental substrate, the bottom surface of the experimental trench, and the bottom of the experimental trench until the thickness of the oxide layer on the first crystal surface of the experimental substrate reaches the estimated thickness;

[0022] Measuring the actual thickness of the oxide layer on the second crystal surface of the experimental substrate;

[0023] If the actual thickness of the oxide layer of the second crystal plane of the experimental substrate is within a preset range of the first target thickness, the estimated thickness is used as the second target thickness.

[0024] In one embodiment, if the actual thickness of the oxide layer on the second crystal plane of the experimental substrate is outside the preset range of the first target thickness, the above steps are repeated until the actual thickness of the oxide layer on the second crystal plane of the experimental substrate is within the preset range of the first target thickness.

[0025] In one embodiment, if the actual thickness of the oxide layer of the second crystal plane of the experimental substrate is outside the preset range of the first target thickness, and the error of the actual thickness of the oxide layer of the second crystal plane of the experimental substrate and the preset range of the first target thickness is within a controllable error range, the estimated thickness is fine-tuned according to the error to obtain the second target thickness.

[0026] In one embodiment, an ellipsometer is used to measure the thickness of the oxide layer on the first crystal surface of the experimental substrate online; a scanning electron microscope or a transmission electron microscope is used to measure the thickness of the oxide layer on the second crystal surface of the experimental substrate.

[0027] In a second aspect, the present application further provides a semiconductor structure, which is prepared by using any method for preparing a semiconductor structure in the first aspect.

[0028] The semiconductor structure of the present application obtains the growth ratio of the oxide layer of the first crystal plane and the second crystal plane under different growth temperature conditions, obtains the second target thickness of the oxide layer to be formed on the first crystal plane based on the first target thickness of the oxide layer to be formed on the second crystal plane, the growth temperature and the growth ratio at the growth temperature, and then forms an oxide layer on the upper surface of the substrate, the bottom surface of the groove and the bottom of the groove until the thickness of the oxide layer on the first crystal plane reaches the second target thickness. The problem of being unable to accurately judge whether the thickness of the Si(110) oxide layer has reached the target thickness based on the thickness of the oxide layer on the Si(100) crystal plane, resulting in a long development cycle and high manufacturing cost for the trench oxide layer, is solved, and has the advantage of improving the electrical properties and reliability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0030] Figure 1 is a flow chart of a method for preparing a semiconductor structure provided in an embodiment;

[0031] Figure 2 is a flow chart of steps S141 to S146 in a method for preparing a semiconductor structure provided in an embodiment;

[0032] Figure 3 is a schematic cross-sectional view of a structure obtained in step S11 of a method for preparing a semiconductor structure provided in an embodiment;

[0033] Figure 4 is a schematic cross-sectional view of a structure obtained in step S12 of a method for preparing a semiconductor structure provided in an embodiment;

[0034] Figure 5 is a schematic cross-sectional view of a structure obtained in step S13 of a method for preparing a semiconductor structure provided in an embodiment;

[0035] Figure 6 is a schematic cross-sectional structural diagram of a structure obtained in step S142 in a method for preparing a semiconductor structure provided in an embodiment;

[0036] Figure 7 is a schematic cross-sectional structural diagram of a structure obtained in step S143 in a method for preparing a semiconductor structure provided in an embodiment;

[0037] Figure 8 It is a schematic diagram of the cross-sectional structure of a structure obtained in step S144 in a method for preparing a semiconductor structure provided in an embodiment.

[0038] Description of Reference Numerals

[0039] 10. Substrate; 100a. First crystal plane; 100b. Second crystal plane; 20. Groove; 30. Oxide layer; 40. Experimental substrate; 50. Experimental groove. DETAILED DESCRIPTION

[0040] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0042] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0043] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0044] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0045] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0046] The thickness of the sidewall oxide layer of the trench structure in the semiconductor directly affects the electrical properties and reliability of the semiconductor. For example, the sidewall oxide layer of the deep trench isolation structure (DTI) in the monolithic integration process (Bipolar-CMOS-DMOS, BCD) is used to isolate high-voltage devices, and the sidewall oxide layer of the trench structure in discrete devices is used as the gate oxide layer. Since the oxidation rate of the trench sidewall oxide layer Si (110) is faster than the oxidation rate of the wafer surface and the trench bottom Si (100), the thickness of the Si (110) oxide layer is inconsistent with the thickness of the Si (100) oxide layer. The thickness of the Si (100) oxide layer is usually measured by ellipsometer, and the thickness of the Si (110) oxide layer needs to be characterized by transmission electron microscopy (TEM) or scanning electron microscope (SEM) after the trench oxide layer is formed. Therefore, during the preparation of the trench oxide layer, the thickness of the Si(100) oxide layer can only be measured to determine whether the thickness of the Si(110) oxide layer has reached the target thickness. However, the Si(100) / Si(110) crystal surface oxide layer growth ratio is affected by the oxidation temperature and oxidation method, which will result in the inability to accurately determine whether the Si(110) oxide layer thickness has reached the target thickness based on the oxide layer thickness of the Si(100) crystal surface during the preparation of the trench oxide layer, which increases the development cycle and production cost of the trench oxide layer, and affects the electrical properties and reliability of the semiconductor structure.

[0047] See also Figure 1 , an embodiment of the present application provides a method for preparing a semiconductor structure, the method for preparing a semiconductor structure comprising:

[0048] S11: providing a substrate.

[0049] S12: forming a trench in the substrate; the upper surface of the substrate and the bottom surface of the trench are both first crystal planes, and the sidewalls of the trench are second crystal planes.

[0050] S13: Obtaining a growth ratio of the oxide layer on the first crystal plane to that on the second crystal plane under different growth temperature conditions.

[0051] S14: Calculating a second target thickness of the oxide layer to be formed on the first crystal plane based on the first target thickness of the oxide layer to be formed on the second crystal plane, the growth temperature, and the growth ratio at the growth temperature.

[0052] S15: forming an oxide layer on the upper surface of the substrate, the bottom surface of the trench and the bottom of the trench until the thickness of the oxide layer on the first crystal surface reaches a second target thickness.

[0053] In the embodiment of the present application, by obtaining the growth ratio of the oxide layer of the first crystal plane and the second crystal plane under different growth temperature conditions, the second target thickness of the oxide layer required to be formed on the first crystal plane is obtained based on the first target thickness of the oxide layer required to be formed on the second crystal plane, the growth temperature and the growth ratio at the growth temperature, and then the oxide layer is formed on the upper surface of the substrate, the bottom surface of the groove and the bottom of the groove until the thickness of the oxide layer on the first crystal plane reaches the second target thickness. The problem of being unable to accurately judge whether the thickness of the Si(110) oxide layer reaches the target thickness based on the thickness of the oxide layer on the Si(100) crystal plane, resulting in a long development cycle and high production cost of the trench oxide layer, is solved, and the electrical properties and reliability of the semiconductor structure are improved.

[0054] In some embodiments, see Figure 2 In step S13, obtaining the growth ratio of the oxide layer on the first crystal plane and the second crystal plane under different growth temperature conditions may include the following steps: S131.

[0055] S131: Based on the oxide layer thickness of the first crystal plane and the oxide layer thickness of the second crystal plane under each growth temperature condition, a growth ratio of the oxide layer of the first crystal plane to that of the second crystal plane under different growth temperature conditions is obtained, wherein the oxide layer thickness of the first crystal plane is different from the oxide layer thickness of the second crystal plane under the same growth temperature condition.

[0056] In some embodiments, see Figure 3 In step S14, obtaining the second target thickness of the oxide layer required to be formed on the first crystal surface based on the first target thickness of the oxide layer required to be formed on the second crystal surface, the growth temperature and the growth ratio at the growth temperature may include the following steps: S141~S146.

[0057] S141: estimating the estimated thickness of the oxide layer required to be formed on the first crystal surface based on the first target thickness of the oxide layer required to be formed on the second crystal surface, the growth temperature, and the growth ratio at the growth temperature.

[0058] S142: Provide an experimental substrate, which is the same as the substrate.

[0059] S143: forming an experimental trench in the experimental substrate, wherein the experimental trench and the trench are formed by the same dry etching process; the upper surface of the experimental substrate and the bottom surface of the experimental trench are both the first crystal plane, and the sidewall of the experimental trench is the second crystal plane.

[0060] S144: forming an oxide layer on the upper surface of the experimental substrate, the bottom surface of the experimental trench, and the bottom of the experimental trench until the thickness of the oxide layer on the first crystal surface of the experimental substrate reaches an estimated thickness.

[0061] S145: Measure the actual thickness of the oxide layer on the second crystal surface of the experimental substrate.

[0062] S146: If the actual thickness of the oxide layer on the second crystal surface of the experimental substrate is within a preset range of the first target thickness, the estimated thickness is used as the second target thickness.

[0063] It should be understood that although Figure 1~Figure 3 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1~Figure 3 At least part of the steps may include multiple steps or multiple stages. These steps or stages do not necessarily have to be executed at the same time, but can be executed at different times. The execution order of these steps or stages does not have to be sequentially, but can be executed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0064] In order to more clearly illustrate the method for preparing the semiconductor structure in some of the above embodiments, the following embodiments are combined with Figure 3~Figure 8 Understand.

[0065] In step S11, refer to Figure 1 Step S11 in Figure 3 , providing a substrate 10.

[0066] As an example, the substrate 10 may include but is not limited to at least one of a silicon substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon on insulator (SOI) substrate, a silicon on diamond (SOD) substrate, and a strained layer silicon substrate deposited on a silicon germanium wafer. Specifically, in the present embodiment, the substrate 10 is a silicon substrate.

[0067] In another example, after step S11, the method for preparing the semiconductor structure may further include the step of cleaning the substrate 10. In this way, by cleaning the substrate 10, impurities on the surface of the substrate 10 can be removed to prevent the impurities from affecting subsequent processes, thereby ensuring the performance of the device. Specifically, the substrate 10 can be cleaned with a cleaning solution to achieve cleaning of the substrate 10, or the substrate 10 can be purged with a gas such as nitrogen to achieve cleaning of the substrate 10. It should be noted that when the substrate 10 is cleaned with a cleaning solution, the step of drying the substrate 10 is also included after cleaning. Specifically, the substrate 10 can be purged with a gas such as nitrogen to dry the substrate 10, but is not limited to.

[0068] In another example, after step S11, the method for preparing the semiconductor device structure may further include making an alignment mark on the substrate 10. In this way, the alignment mark made on the substrate 10 can be used as an alignment reference mark for subsequent preparation processes or measurements, thereby ensuring the accuracy of subsequent preparation processes or measurements.

[0069] In step S12, refer to Figure 1 Step S12 in Figure 4 , a trench 20 is formed in the substrate 10; the upper surface of the substrate 10 and the bottom surface of the trench 20 are both the first crystal plane 100a, and the sidewall of the trench 20 is the second crystal plane 100b.

[0070] As an example, the trench 20 may be formed in the substrate 10 by using, but not limited to, a dry etching process.

[0071] In a specific example, forming the trench 20 in the substrate 10 may include the following steps: S121 - S125 .

[0072] S121: forming a first mask layer on the upper surface of the substrate 10; illustratively, the first mask layer may be formed on the upper surface of the substrate 10 by, but not limited to, a physical vapor deposition process (PVD), a chemical vapor deposition process (CVD), or an atomic layer deposition process (ALD).

[0073] S122: forming a photoresist layer on the upper surface of the first mask layer; illustratively, but not limited to, a photoresist coating and developing device may be used to form the photoresist layer on the upper surface of the first mask layer.

[0074] S123: exposing and developing the photoresist layer based on the photomask to obtain a patterned photoresist layer, and removing the photomask.

[0075] S124: etching the first mask layer based on the patterned photoresist layer to obtain a patterned mask layer, and removing the patterned photoresist layer; illustratively, a wet etching process or a dry etching process may be used to etch the first mask layer to obtain the patterned mask layer.

[0076] S125: etching the substrate 10 based on the patterned mask layer to form a groove 20, such as Figure 4 As shown in; for example, the patterned mask layer has an opening, which defines the shape and position of the groove 20. The shape of the opening may include but is not limited to a circle, an ellipse or other polygons with a side number greater than 2.

[0077] In some embodiments, please refer to Figure 4 , the first crystal plane 100 a may include a (100) crystal plane, and the second crystal plane 100 b may include a (110) crystal plane.

[0078] In step S13, refer to Figure 1 Step S13 in Figure 5 , obtaining the growth ratio of the oxide layer 30 of the first crystal plane 100a and the second crystal plane 100b under different growth temperature conditions.

[0079] As an example, the growth ratio of the oxide layer of the first crystal plane 100 a and the second crystal plane 100 b under different growth temperature conditions may be obtained through, but not limited to, a database or experiment.

[0080] In some embodiments, step S13 may include step S131.

[0081] In step S131, please continue to refer to Figure 5 Based on the thickness of the oxide layer 30 of the first crystal plane 100a and the thickness of the oxide layer 30 of the second crystal plane 100b under each growth temperature condition, the growth ratio of the oxide layer 30 of the first crystal plane 100a and the second crystal plane 100b under different growth temperature conditions is obtained, wherein the thickness of the oxide layer 30 of the first crystal plane 100a is different from the thickness of the oxide layer 30 of the second crystal plane 100b under the same growth temperature condition.

[0082] As an example, the growth ratio of the oxide layer 30 of the first crystal plane 100a to the second crystal plane 100b under different growth temperature conditions can be obtained based on the thickness of the oxide layer 30 of the first crystal plane 100a and the thickness of the oxide layer 30 of the second crystal plane 100b under different growth temperature conditions by means of, but not limited to, experiments. For example, at a temperature of 1050° C., in a wet oxygen oxidation process, the growth rate of the oxide layer 30 of the first crystal plane 100a and the growth rate of the oxide layer 30 of the second crystal plane 100b are 1.2:1; at a temperature of 950° C., in a wet oxygen oxidation process, the growth rate of the oxide layer 30 of the first crystal plane 100a is 1.2:1. The ratio of the growth rate of the thickness of the oxide layer 30 on the first crystal plane 100a to the growth rate of the thickness of the oxide layer 30 on the second crystal plane 100b is 1.45:1; in the wet oxygen oxidation process at a temperature of 900°C, the ratio of the growth rate of the thickness of the oxide layer 30 on the first crystal plane 100a to the growth rate of the thickness of the oxide layer 30 on the second crystal plane 100b is 1.6:1; the growth ratio of the oxide layer 30 of the first crystal plane 100a and the second crystal plane 100b under different growth temperature conditions can be established to form a database, so as to obtain the growth ratio of the oxide layer 30 of the first crystal plane 100a and the second crystal plane 100b in the database during the growth of the oxide layer 30.

[0083] In some embodiments, see Figures 6 to 8 In step S14, obtaining the second target thickness of the oxide layer 30 required to be formed on the first crystal surface 100a based on the first target thickness of the oxide layer 30 required to be formed on the second crystal surface 100b, the growth temperature and the growth ratio at the growth temperature may include the following steps: S141~S146.

[0084] In step S141, refer to Figures 6 to 8 The estimated thickness of the oxide layer 30 required to be formed on the first crystal surface 100a is estimated based on the first target thickness of the oxide layer 30 required to be formed on the second crystal surface 100b, the growth temperature, and the growth ratio at the growth temperature.

[0085] As an example, the estimated thickness of the oxide layer 30 required to be formed on the first crystal plane 100a is estimated based on the first target thickness of the oxide layer 30 required to be formed on the second crystal plane 100b, the growth temperature and the growth ratio at the growth temperature. For example, under the temperature condition of 1050°C, in the wet oxygen oxidation process, the first target thickness of the oxide layer 30 required to be formed on the second crystal plane 100b is 1200Å. The growth rate of the oxide layer 30 thickness of the first crystal plane 100a and the growth rate of the oxide layer 30 thickness of the second crystal plane 100b under this condition are obtained in the database or experimentally, and the ratio of 1.2:1 is obtained. It is estimated that the estimated thickness of the oxide layer 30 required to be formed on the first crystal plane 100a is 1000Å.

[0086] In step S142, refer to Figure 2 Step S142 in Figure 6 , an experimental substrate 40 is provided, and the experimental substrate 40 is the same as the substrate 10.

[0087] As an example, the experimental substrate 40 may include but is not limited to at least one of a silicon substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon on insulator (SOI) substrate, a silicon on diamond (SOD) substrate, and a strained layer silicon substrate deposited on a germanium silicon wafer. Specifically, in the present embodiment, the experimental substrate 40 is a silicon substrate.

[0088] In step S143, refer to Figure 2 Step S143 in Figure 7 , an experimental substrate 40 is formed in the experimental substrate 40, and the experimental substrate 40 and the groove 20 are formed by the same dry etching process; the upper surface of the experimental substrate 40 and the bottom surface of the experimental groove 50 are both the first crystal plane 100a, and the side wall of the experimental groove 50 is the second crystal plane 100b.

[0089] As an example, the experimental substrate 40 and the groove 20 are formed by the same dry etching process. Specifically, the experimental substrate 40 can be etched under but not limited to the same etching process conditions as the groove 20. For example, in the process of forming the experimental substrate 40, the patterned photomask layer, the position and shape of the opening are the same as those in the process of forming the groove 20.

[0090] In step S144, refer to Figure 2 Step S144 in Figure 8 , an oxide layer 30 is formed on the upper surface of the experimental substrate 40 , the bottom surface of the experimental substrate 40 , and the bottom of the experimental substrate 40 , until the thickness of the oxide layer 30 on the first crystal plane 100 a of the experimental substrate 40 reaches an estimated thickness.

[0091] As an example, a thermal oxidation process may be used but is not limited to form an oxide layer 30 on the upper surface, the bottom surface and the bottom of the experimental substrate 40 until the thickness of the oxide layer 30 on the first crystal surface 100a of the experimental substrate 40 reaches an estimated thickness.

[0092] In step S145, refer to Figure 2 Step S145 in Figure 8 , measuring the actual thickness of the oxide layer 30 on the second crystal surface 100 b of the experimental substrate 40 .

[0093] As an example, the actual thickness of the oxide layer 30 on the second crystal plane 100 b of the experimental substrate 40 may be measured by using, but not limited to, a transmission electron microscope or a scanning electron microscope.

[0094] In step S146, refer to Figure 2 Step S146 in Figure 8 If the actual thickness of the oxide layer 30 of the second crystal plane 100 b of the experimental substrate 40 is within the preset range of the first target thickness, the estimated thickness is used as the second target thickness.

[0095] In another embodiment, please refer to Figure 8 If the actual thickness of the oxide layer 30 of the second crystal plane 100b of the experimental substrate 40 is outside the preset range of the first target thickness, repeat steps S141 to S145 until the actual thickness of the oxide layer 30 of the second crystal plane 100b of the experimental substrate 40 is within the preset range of the first target thickness.

[0096] In yet another embodiment, please continue to refer to Figure 8 If the actual thickness of the oxide layer 30 of the second crystal plane 100b of the experimental substrate 40 is outside the preset range of the first target thickness, and the error between the actual thickness of the oxide layer 30 of the second crystal plane 100b of the experimental substrate 40 and the preset range of the first target thickness is within the controllable error range, the estimated thickness is fine-tuned according to the error to obtain the second target thickness.

[0097] The present application also provides a semiconductor structure. Figure 5 The semiconductor structure can be prepared by using the method for preparing the semiconductor structure of any one of the above embodiments. The semiconductor structure may include: a substrate 10; a groove 20 located in the substrate 10; the upper surface of the substrate 10 and the bottom surface of the groove 20 are both the first crystal plane 100a, and the sidewall of the groove 20 is the second crystal plane 100b; an oxide layer 30 located on the upper surface of the substrate 10, the bottom surface of the groove 20 and the bottom of the groove 20.

[0098] In the embodiment of the present application, by obtaining the growth ratio of the oxide layer of the first crystal plane and the second crystal plane under different growth temperature conditions, the second target thickness of the oxide layer required to be formed on the first crystal plane is obtained based on the first target thickness of the oxide layer required to be formed on the second crystal plane, the growth temperature and the growth ratio at the growth temperature, and then the oxide layer is formed on the upper surface of the substrate, the bottom surface of the groove and the bottom of the groove until the thickness of the oxide layer on the first crystal plane reaches the second target thickness. The problem of being unable to accurately judge whether the thickness of the Si(110) oxide layer reaches the target thickness based on the thickness of the oxide layer on the Si(100) crystal plane, resulting in a long development cycle and high production cost of the trench oxide layer, is solved, and the electrical properties and reliability of the semiconductor structure are improved.

[0099] As an example, see Figure 5The substrate 10 may include but is not limited to at least one of a silicon substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon on insulator (SOI) substrate, a silicon on diamond (SOD) substrate, and a strained layer silicon substrate deposited on a germanium silicon wafer. Specifically, in the present embodiment, the substrate 10 is a silicon substrate.

[0100] As an example, the shape of the groove 20 may include but is not limited to a circle, an ellipse, or other polygons with more than two sides.

[0101] As an example, the oxide layer 30 may include but is not limited to an oxide layer. For example, the oxide layer 30 may be a silicon dioxide layer.

[0102] As an example, the first crystal plane 100 a may include a (100) crystal plane, and the second crystal plane 100 b may include a (110) crystal plane.

[0103] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0104] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor structure, It is characterized in that include: providing a substrate; forming a groove in the substrate; The upper surface of the substrate and the bottom surface of the groove are both first crystal planes, and the sidewalls of the groove are second crystal planes; Obtaining a growth ratio of the oxide layer of the first crystal plane to that of the second crystal plane under different growth temperature conditions; Obtaining a second target thickness of the oxide layer to be formed on the first crystal plane based on a first target thickness of the oxide layer to be formed on the second crystal plane, a growth temperature, and a growth ratio at the growth temperature; An oxide layer is formed on the upper surface of the substrate, the bottom surface of the trench and the bottom of the trench until the thickness of the oxide layer on the first crystal plane reaches the second target thickness.

2. The method for preparing a semiconductor structure according to claim 1, It is characterized in that The first crystal plane includes a (100) crystal plane, and the second crystal plane includes a (110) crystal plane.

3. The method for preparing a semiconductor structure according to claim 1, It is characterized in that The oxide layer is formed on the upper surface of the substrate, the bottom surface of the trench and the bottom of the trench by using a thermal oxidation process.

4. The method for preparing a semiconductor structure according to claim 1, It is characterized in that The obtaining of the growth ratio of the oxide layer of the first crystal plane to that of the second crystal plane under different growth temperature conditions includes: Based on the oxide layer thickness of the first crystal plane and the oxide layer thickness of the second crystal plane under each growth temperature condition, a growth ratio of the oxide layer of the first crystal plane to that of the second crystal plane under different growth temperature conditions is obtained, wherein the oxide layer thickness of the first crystal plane is different from the oxide layer thickness of the second crystal plane under the same growth temperature condition.

5. The method for preparing a semiconductor structure according to claim 4, It is characterized in that The thickness of the oxide layer on the first crystal surface under each growth temperature condition is measured by using an ellipsometer; the thickness of the oxide layer on the second crystal surface under each growth temperature condition is measured by using a scanning electron microscope or a transmission electron microscope.

6. The method for preparing a semiconductor structure according to claim 1, It is characterized in that The obtaining of a second target thickness of the oxide layer required to be formed on the first crystal plane based on the first target thickness of the oxide layer required to be formed on the second crystal plane, the growth temperature, and the growth ratio at the growth temperature includes: estimating the estimated thickness of the oxide layer required to be formed on the first crystal plane based on a first target thickness of the oxide layer required to be formed on the second crystal plane, a growth temperature, and a growth ratio at the growth temperature; providing an experimental substrate, the experimental substrate being the same as the substrate; An experimental groove is formed in the experimental substrate, wherein the experimental groove and the groove are formed by the same dry etching process; the upper surface of the experimental substrate and the bottom surface of the experimental groove are both first crystal planes, and the sidewalls of the experimental groove are second crystal planes; forming an oxide layer on the upper surface of the experimental substrate, the bottom surface of the experimental trench, and the bottom of the experimental trench until the thickness of the oxide layer on the first crystal surface of the experimental substrate reaches the estimated thickness; Measuring the actual thickness of the oxide layer on the second crystal surface of the experimental substrate; If the actual thickness of the oxide layer of the second crystal plane of the experimental substrate is within a preset range of the first target thickness, the estimated thickness is used as the second target thickness.

7. The method for preparing a semiconductor structure according to claim 6, It is characterized in that If the actual thickness of the oxide layer on the second crystal plane of the experimental substrate is outside the preset range of the first target thickness, repeat the steps of obtaining the second target thickness of the oxide layer on the first crystal plane based on the first target thickness of the oxide layer on the second crystal plane, the growth temperature and the growth ratio at the growth temperature as described in claim 6 until the actual thickness of the oxide layer on the second crystal plane of the experimental substrate is within the preset range of the first target thickness.

8. The method for preparing a semiconductor structure according to claim 6, It is characterized in that If the actual thickness of the oxide layer on the second crystal plane of the experimental substrate is outside the preset range of the first target thickness, and the error of the actual thickness of the oxide layer on the second crystal plane of the experimental substrate within the preset range of the first target thickness is within a controllable error range, the estimated thickness is fine-tuned according to the error to obtain the second target thickness.

9. The method for preparing a semiconductor structure according to claim 6, It is characterized in that The thickness of the oxide layer on the first crystal plane of the experimental substrate was measured online using an ellipsometer.

10. The method for preparing a semiconductor structure according to claim 6, It is characterized in that The thickness of the oxide layer on the second crystal surface of the experimental substrate is measured using a scanning electron microscope or a transmission electron microscope.

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