Server bus port control system and method, storage medium and electronic device

Abstract

The embodiment of the present application provides a control system and method for a server bus port, a storage medium and an electronic device, including: a processor, configured to receive a first instruction in the POST stage of the BIOS of the server to control the opening and closing of the bus port of the server; a baseboard management controller, configured to receive a second instruction in the startup stage and the operation stage of the server to control the opening and closing of the bus port; a controller, connected to the processor and the baseboard management controller respectively, and the controller is configured to control the opening and closing of the bus port according to a first control signal generated by the first instruction in the POST stage, or to control the opening and closing of the bus port according to a second control signal generated by the second instruction in the startup stage and the operation stage.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computers, and in particular, to a control system and method for a server bus port, a storage medium, and an electronic device. Background Art

[0002] The server is equipped with bus ports, such as USB ports. USB ports are widely used to connect mice, keyboards, storage devices, and various peripheral devices due to their plug-and-play features, fast transmission speed, and compatibility with a variety of devices. However, although the convenience of USB ports is widely welcomed, it also brings a series of security and management issues.

[0003] In the existing server system, under the server OS, users can flexibly control the opening and closing of the USB Port through the relevant instructions driven by the xHCI (eXtensible Host Controller Interface), but this method has poor security. For example, in a server architecture that expands the USB Port through a PCIe to USB conversion chip, during the startup phase of the server operating system, when the USB port is opened and closed through BIOS, after entering the OS (Operating System), the USB port can still be opened and closed through commands. Summary of the invention

[0004] The embodiments of the present application provide a control system and method for a server bus port, a storage medium, and an electronic device to at least solve the problem of low security in the control of the server bus port in the related art.

[0005] According to one embodiment of the present application, a control system for a server bus port is provided, comprising: a processor, configured to receive a first instruction in the POST stage of the BIOS of the server to control the opening and closing of the bus port of the server; a baseboard management controller, configured to receive a second instruction in the startup stage and the operation stage of the server to control the opening and closing of the bus port; a controller, connected to the processor and the baseboard management controller respectively, the controller being configured to control the opening and closing of the bus port according to a first control signal generated by the first instruction in the POST stage, or to control the opening and closing of the bus port according to a second control signal generated by the second instruction in the startup stage and the operation stage.

[0006] In an exemplary embodiment, the system includes: an extension device, which is connected to the processor and the controller respectively, and the extension device is configured to receive a third instruction initiated by the processor in response to the first instruction in the POST stage to generate a third control signal in the first control signal, or to receive a fourth instruction initiated by the processor in the startup stage and the operation stage to generate the third control signal, and the controller is configured to extract the third control signal generated by the extension device, wherein when the bus port is controlled to be turned on, a high level third control signal is generated, and when the bus port is controlled to be turned off, a low level third control signal is generated.

[0007] In an exemplary embodiment, the controller is configured to perform an AND operation on the first control signal in the POST stage to obtain a first target control signal to control the opening and closing of the bus port, wherein when the first target control signal is at a high level, the bus port is controlled to be opened, and when the first target control signal is at a low level, the bus port is controlled to be closed.

[0008] In an exemplary embodiment, the system includes: a conversion chip, which is connected to the processor and the controller respectively, and the conversion chip is configured to receive a first target control signal initiated by the controller in response to the first control signal during the POST stage, so as to control the opening and closing of the bus port.

[0009] In an exemplary embodiment, a second pin and a bus pin are disposed on the conversion chip, the second pin is connected to the controller, and the bus pin is connected to the bus port. The conversion chip is configured to receive the first target control signal through the second pin, and to control the opening and closing of the bus port through the bus port.

[0010] In an exemplary embodiment, the controller is configured to perform an AND operation on the second control signal during the startup phase and the operation phase to obtain a second target control signal to control the opening and closing of the bus port, wherein when the second target control signal is at a high level, the bus port is controlled to be opened, and when the second target control signal is at a low level, the bus port is controlled to be closed.

[0011] In an exemplary embodiment, the system includes: a load switch, wherein the load switch is connected to the processor and the bus port, respectively, and the load switch is configured to receive a second target control signal initiated by the controller in response to the second control signal during the startup phase and the operation phase, and to control the opening and closing of the bus port by controlling the opening and closing of the load switch, wherein when the second target control signal is at a low level, the load switch is controlled to be closed to control the bus port to be closed, and when the second target control signal is at a high level, the load switch is controlled to be opened to control the bus port to be opened.

[0012] In an exemplary embodiment, the system includes: a load switch, the load switch is connected to the controller, the controller is configured to extract the fourth control signal generated by the load switch in the POST stage, and generate a high-level fifth control signal in response to a received fifth instruction initiated by the baseboard management controller, wherein the first control signal includes the fourth control signal and the fifth control signal, and when the bus port is controlled to be turned on, the fourth control signal is at a high level, and when the bus port is controlled to be turned off, the fourth control signal is at a low level, or the controller is configured to extract the high-level fourth control signal generated by the load switch in the startup stage and the operation stage, and generate the fifth control signal in response to a received fifth instruction initiated by the baseboard management controller, wherein when the bus port is controlled to be turned on, the fifth control signal is at a high level, and when the bus port is controlled to be turned off, the fifth control signal is at a low level.

[0013] In an exemplary embodiment, the system includes: a conversion chip and an expansion device, the conversion chip is connected to the processor and the controller respectively, the expansion device is connected to the processor and the controller respectively, the controller is configured to extract the sixth control signal in the second control signal generated by the expansion device in response to the sixth instruction initiated by the processor received in the POST stage; and generate a seventh control signal of a high level in the second control signal in response to the seventh instruction initiated by the baseboard management controller received, wherein the sixth control signal is a high level in the case of controlling the bus port to be turned on, and the sixth control signal is a low level in the case of controlling the bus port to be turned off; or, the controller is configured to extract the sixth control signal of a high level in the second control signal generated by the expansion device in response to the sixth instruction initiated by the processor received in the startup stage and the operation stage; and generate a seventh control signal in the second control signal in response to the seventh instruction initiated by the baseboard management controller received, wherein the seventh control signal is a high level in the case of controlling the bus port to be turned on, and the seventh control signal is a low level in the case of controlling the bus port to be turned off.

[0014] In an exemplary embodiment, a first pin is deployed on the conversion chip, and the first pin is connected to the controller. The conversion chip is configured to receive an eighth instruction initiated by the processor in response to the first instruction during the startup phase and the operation phase of the server, and generate an eighth control signal in the second control signal. The controller is configured to extract the eighth control signal through the first pin during the startup phase and the operation phase of the server.

[0015] According to another embodiment of the present application, a method for controlling a server bus port is provided, wherein a processor, a control device and a bus port connected in sequence are deployed on the server, and the server is configured to allow the operating state of the bus port to be controlled by the operating system when the operating system of the processor is running. The method is applied to a first controller, and the first controller is connected to the processor and the control device respectively. The method includes: during the startup of the operating system, detecting the startup operating state of the bus port in the operating system, wherein the startup operating state is used to indicate the operating state of the bus port when the operating system is started; generating a target control signal matching the startup operating state according to the startup operating state, wherein the target control signal is used to adjust the connection state of the power supply line of the bus port on the control device to match the startup operating state; and sending the target control signal to the control device, wherein the control device is used to control the power supply line of the bus port according to the target control signal.

[0016] In an exemplary embodiment, generating a target control signal matching the startup operation state according to the startup operation state includes: detecting an initial control signal set matching the startup operation state according to the startup operation state; and generating the target control signal according to the initial control signal set.

[0017] In an exemplary embodiment, the control device includes a load switch and a conversion chip, the first controller is connected to the load switch and the conversion chip respectively, an extension device is further deployed in the server, the first controller is connected to the extension device, and the detecting the initial control signal set matching the startup operation state according to the startup operation state includes: extracting a first initial control signal corresponding to the startup operation state output by the extension device, detecting a second initial control signal corresponding to the startup operation state, and extracting a third initial control signal corresponding to the startup operation state output by the conversion chip, wherein the initial control signal set includes a first control signal set, the first control signal set includes the first initial control signal, the second initial control signal and the third initial control signal; or extracting a fourth initial control signal corresponding to the startup operation state output by the extension device, detecting a fifth initial control signal corresponding to the startup operation state, and extracting a sixth initial control signal corresponding to the startup operation state output by the load switch, wherein the initial control signal set includes a second control signal set, the second control signal set includes the fourth initial control signal, the fifth initial control signal and the sixth initial control signal.

[0018] In an exemplary embodiment, the server is also deployed with a second controller, the first controller is connected to the second controller, and the detecting the second initial control signal corresponding to the startup operation state includes: when the startup operation state includes the detected operation state set by the second controller, receiving a first signal generation instruction initiated by the second controller, wherein the first signal generation instruction is used to instruct the first controller to generate a second initial control signal corresponding to a second signal parameter, and the second signal parameter is a signal parameter corresponding to the startup operation state set by the second controller, and the second signal parameter is used to indicate that the second initial control signal is a high level when the startup operation state is used to indicate that the bus port is turned on, and indicates that the second initial control signal is a low level when the startup operation state is used to indicate that the bus port is turned off; in response to the first signal generation instruction, generate the second initial control signal corresponding to the second signal parameter.

[0019] In an exemplary embodiment, the extension device is connected to the processor, and before extracting the fourth initial control signal corresponding to the startup operation state output by the extension device, the method also includes: when the startup operation state is extracted from the startup item, extracting a third signal parameter corresponding to the startup operation state by the processor, wherein the third signal parameter is used to indicate that the fourth initial control signal is at a high level when the startup operation state is used to indicate that the bus port is turned on, and to indicate that the fourth initial control signal is at a low level when the startup operation state is used to indicate that the bus port is turned off; and controlling the extension device by the processor through the first bus between the extension device and the extension device to generate and output the fourth initial control signal corresponding to the third signal parameter.

[0020] In an exemplary embodiment, the server is also deployed with a second controller, the first controller is connected to the second controller, and the detection of the fifth initial control signal corresponding to the startup operation state includes: when the startup operation state includes the detected operation state set by the second controller, receiving a second signal generation instruction initiated by the second controller, wherein the second signal generation instruction is used to instruct the first controller to generate a fifth initial control signal corresponding to a fourth signal parameter, and the fourth signal parameter is a signal parameter corresponding to the startup operation state set by the second controller, and the fourth signal parameter is used to indicate that the fifth initial control signal is a high level when the startup operation state is used to indicate that the bus port is turned on, and indicates that the fifth initial control signal is a low level when the startup operation state is used to indicate that the bus port is turned off; in response to the second signal generation instruction, the fifth initial control signal corresponding to the fourth signal parameter is generated.

[0021] In an exemplary embodiment, generating the target control signal according to the initial control signal set includes: when the target control signal is used to adjust the connection state of the power supply line of the bus port on the load switch to match the startup operation state, performing an AND operation on the first control signal set to obtain a first reference control signal, wherein the initial control signal set includes the first control signal set, and the target control signal includes the first reference control signal; when the target control signal is used to adjust the connection state of the power supply line of the bus port on the conversion chip to match the startup operation state, performing an AND operation on the second control signal set to obtain a second reference control signal, wherein the initial control signal set includes the second control signal set, and the target control signal includes the second reference control signal.

[0022] In an exemplary embodiment, performing an AND operation on the first control signal set to obtain a first reference control signal includes: when the startup operation state is extracted from the startup item, and the first control signal set includes a first initial control signal, a second initial control signal and a third initial control signal, and the startup operation state is on, performing an AND operation on the first initial control signal, the second initial control signal and the third initial control signal to obtain the first reference control signal, wherein, when the startup operation state is on, the first initial control signal is set to a high level, the second initial control signal is set to a high level, and the third initial control signal is set to a high level. The first reference control signal is set to a high level, and the first reference control signal is a high level; when the startup operation state is extracted from the startup item, and the first control signal set includes a first initial control signal, a second initial control signal and a third initial control signal, and the startup operation state is closed, the first initial control signal, the second initial control signal and the third initial control signal are ANDed to obtain the first reference control signal, wherein, when the startup operation state is closed, the first initial control signal is set to a low level, the second initial control signal is set to a high level, the third initial control signal is set to a high level, and the first reference control signal is The signal is at a low level; when the startup operation state is the operation state set by the detected second controller, and the first control signal set includes a first initial control signal, a second initial control signal and a third initial control signal, and the startup operation state is when the bus port is turned on, an AND operation is performed on the first initial control signal, the second initial control signal and the third initial control signal to obtain the first reference control signal, wherein, when the startup operation state is when the bus port is turned on, the first initial control signal is set to a high level, the second initial control signal is set to a high level, the third initial control signal is set to a high level, and the first reference control signal is high level; when the startup operation state is the operation state set by the second controller detected, and the first control signal set includes a first initial control signal, a second initial control signal and a third initial control signal, and the startup operation state is when the bus port is closed, an AND operation is performed on the first initial control signal, the second initial control signal and the third initial control signal to obtain the first reference control signal, wherein, when the startup operation state is when the bus port is closed, the first initial control signal is set to a high level, the second initial control signal is set to a low level, the third initial control signal is set to a high level, and the first reference control signal is a low level.

[0023] In an exemplary embodiment, performing an AND operation on the second control signal set to obtain a second reference control signal includes: when the startup operation state is extracted from the startup item, and the second control signal set includes a fourth initial control signal, a fifth initial control signal and a sixth initial control signal, and the startup operation state is a bus port open, performing an AND operation on the fourth initial control signal, the fifth initial control signal and the sixth initial control signal to obtain the second reference control signal, wherein, when the startup operation state is a bus port open, the fourth initial control signal is set to a high level, the fifth initial control signal is set to a high level, and the sixth initial control signal is set to a high level. The first control signal is set to a high level, and the second reference control signal is a high level; when the startup operation state is extracted from the startup item, and the second control signal set includes a fourth initial control signal, a fifth initial control signal and a sixth initial control signal, and the startup operation state is a bus port closed, an AND operation is performed on the fourth initial control signal, the fifth initial control signal and the sixth initial control signal to obtain the second reference control signal, wherein, when the startup operation state is a bus port closed, the fourth initial control signal is set to a low level, the fifth initial control signal is set to a high level, and the sixth initial control signal is set to a high level, The second reference control signal is at a low level; when the startup operation state is the operation state set by the detected second controller, and the second control signal set includes a fourth initial control signal, a fifth initial control signal and a sixth initial control signal, and the startup operation state is when the bus port is turned on, an AND operation is performed on the fourth initial control signal, the fifth initial control signal and the sixth initial control signal to obtain the second reference control signal, wherein, when the startup operation state is when the bus port is turned on, the fourth initial control signal is set to a high level, the fifth initial control signal is set to a high level, the sixth initial control signal is set to a high level, and the second reference control The signal is at a high level; when the startup operation state is the operation state set by the second controller detected, and the second control signal set includes a fourth initial control signal, a fifth initial control signal and a sixth initial control signal, and the startup operation state is when the bus port is closed, an AND operation is performed on the fourth initial control signal, the fifth initial control signal and the sixth initial control signal to obtain the second reference control signal, wherein, when the startup operation state is when the bus port is closed, the fourth initial control signal is set to a high level, the fifth initial control signal is set to a low level, the sixth initial control signal is set to a high level, and the second reference control signal is a high level.

[0024] In an exemplary embodiment, the control device includes a conversion chip and a bus connector, a second pin and a bus pin are disposed on the conversion chip, the bus port is disposed on the bus connector, the bus pin is connected to the bus connector, the first controller is connected to the second pin, and the sending of the target control signal to the control device includes: initiating the target control signal to the second pin, wherein the conversion chip is used to connect and maintain the power supply line between the bus pin and the bus port when the target control signal is at a high level, and the conversion chip is used to disconnect the power supply line between the bus pin and the bus port when the target control signal is at a low level; or, the control device includes a load switch, the first controller is connected to the load switch, and the sending of the target control signal to the control device includes: initiating the target control signal to the load switch, wherein the load switch is used to connect the power supply line between the load switch and the bus port and maintain the power supply line of the bus port when the target control signal is at a high level, and the load switch is used to disconnect the power supply line between the load switch and the bus port when the target control signal is at a low level.

[0025] According to another embodiment of the present application, a control device for a server bus port is also provided, wherein a processor, a control device and a bus port connected in sequence are deployed on the server, and the server is configured to allow the operating state of the bus port to be controlled by the operating system when the operating system of the processor is running. The device is applied to a first controller, and the first controller is connected to the processor and the control device respectively. The device includes: a first detection module, which is used to detect the startup operating state of the bus port in the operating system during the startup of the operating system, wherein the startup operating state is used to indicate the operating state of the bus port when the operating system is started; a generation module, which is used to generate a target control signal matching the startup operating state according to the startup operating state, wherein the target control signal is used to adjust the connection state of the power supply line of the bus port on the control device to match the startup operating state; a sending module, which is used to send the target control signal to the control device, wherein the control device is used to control the power supply line of the bus port according to the target control signal.

[0026] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0027] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0028] According to another embodiment of the present application, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0029] Through the present application, the processor of the server can control the opening and closing of the bus port of the server during the POST stage, and the baseboard management controller of the server can control the opening and closing of the bus port during the startup stage and the operation stage of the server. In this way, the controller can control the power supply line of the bus port according to the corresponding control signal, thereby realizing the control of the opening and closing of the bus port. For example, when the power supply circuit of the bus port is disconnected, the bus port can no longer be opened through commands at the software level. Therefore, the problem of low security of the control of the server bus port can be solved, thereby achieving the effect of improving the security of the control of the server bus port. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a schematic diagram of an optional control system of a server bus port according to an embodiment of the present application Figure 1 ;

[0031] Figure 2 is a schematic diagram of an optional control system of a server bus port according to an embodiment of the present application Figure 2 ;

[0032] Figure 3 It is a hardware structure block diagram of a server device of a method for controlling a server bus port according to an embodiment of the present application;

[0033] Figure 4 is a flow chart of a method for controlling a server bus port according to an embodiment of the present application;

[0034] Figure 5 is a schematic diagram of an optional method for generating a target control signal according to an embodiment of the present application;

[0035] Figure 6 It is a structural block diagram of a control device for a server bus port according to an embodiment of the present application. DETAILED DESCRIPTION

[0036] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0037] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0038] First, the terms involved in the embodiments of the present application are explained as follows:

[0039] USB: Universal Serial Bus, universal serial bus;

[0040] OC:Over Current, overcurrent;

[0041] BIOS: Basic Input Output System, basic input output system.

[0042] In this embodiment, a control system of a server bus port is provided. Figure 1 is a schematic diagram of an optional control system of a server bus port according to an embodiment of the present application Figure 1 ,like Figure 1 As shown, the control system of the server bus port includes: a processor, configured to receive a first instruction in the POST stage of the BIOS of the server to control the opening and closing of the bus port of the server; a baseboard management controller, configured to receive a second instruction in the startup stage and the operation stage of the server to control the opening and closing of the bus port; a controller, connected to the processor and the baseboard management controller respectively, and the controller is configured to control the opening and closing of the bus port according to a first control signal generated by the first instruction in the POST stage, or to control the opening and closing of the bus port according to a second control signal generated by the second instruction in the startup stage and the operation stage.

[0043] Optionally, in this embodiment, a bus port may be deployed on the server but is not limited to being deployed. The bus port may be used but is not limited to connecting a bus device. When the bus port is turned on, the bus device connected to the bus port may be used but is not limited to allowing data interaction with the server. For example, the bus device connected to the bus port is set to allow reading or writing operations on data stored on the server, etc. When the bus port is closed, the bus device connected to the bus port is set to not allow data interaction with the server.

[0044] As an optional example, the bus port may include but is not limited to a port that complies with the target bus protocol. For example, the target bus protocol may include but is not limited to a USB (Universal Serial Bus) protocol, or a PCIE (peripheral component interconnect express, a high-speed serial computer expansion bus standard) protocol, etc. The bus port may include but is not limited to a USB port or a PCIE interface, etc.

[0045] Optionally, in this embodiment, the processor may include but is not limited to a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit) deployed on the server, etc. Taking the processor including the CPU as an example, it may include but is not limited to receiving the first instruction in the POST (Power-On Self Test) stage of the BIOS (Basic Input Output System) of the server to control the opening and closing of the bus port.

[0046] Optionally, in this embodiment, the controller may include but is not limited to a CPLD (Complex Programmable Logic Device) or an FPGA (Field Programmable Gate Array) deployed in a server, and the controller and the baseboard management controller may be connected via a bus but is not limited to being connected.

[0047] In an exemplary embodiment, the system further includes: an extension device, which is connected to the processor and the controller respectively, and the extension device is configured to receive a third instruction initiated by the processor in response to the first instruction in the POST stage to generate a third control signal in the first control signal, or to receive a fourth instruction initiated by the processor in the startup stage and the operation stage to generate the third control signal, and the controller is configured to extract the third control signal generated by the extension device, wherein when the bus port is controlled to be turned on, a high level third control signal is generated, and when the bus port is controlled to be turned off, a low level third control signal is generated.

[0048] Optionally, in this embodiment, the expansion device may include, but is not limited to, a device for expanding input and output interfaces of the server. For example, the expansion device may include, but is not limited to, an IO (Input / Output) Expander.

[0049] In an exemplary embodiment, the system further includes: the controller is configured to perform an AND operation on the first control signal in the POST stage to obtain a first target control signal to control the opening and closing of the bus port, wherein when the first target control signal is at a high level, the bus port is controlled to be opened, and when the first target control signal is at a low level, the bus port is controlled to be closed.

[0050] Optionally, in this embodiment, when all control signals in the first control signal are at a high level, an AND operation is performed on the first control signal to obtain a first target control signal of a high level; when at least one control signal in the first control signal is at a low level, an AND operation is performed on the first control signal to obtain a first target control signal of a low level.

[0051] It should be noted that the high level and low level involved in the embodiments of the present application are logic levels. For example, when the voltage is higher than the voltage threshold, the level state can be but is not limited to a high level, and when the voltage is lower than the voltage threshold, the level state can be but is not limited to a low level.

[0052] In an exemplary embodiment, the system further includes: a conversion chip, which is connected to the processor and the controller respectively, and is configured to receive a first target control signal initiated by the controller in response to the first control signal during the POST stage, so as to control the opening and closing of the bus port.

[0053] Optionally, in this embodiment, the conversion chip can be used but is not limited to converting a first bus port of a server to a second bus port, wherein the first bus port supports a first bus protocol, the second bus port supports a second bus protocol, and the first bus protocol and the second bus protocol are different. For example, the conversion chip includes a PCIe to USB chip, the first bus protocol can be but is not limited to including a PCIE protocol, and the second bus protocol can be but is not limited to including a USB port.

[0054] In an exemplary embodiment, a second pin and a bus pin are disposed on the conversion chip, the second pin is connected to the controller, and the bus pin is connected to the bus port. The conversion chip is configured to receive the first target control signal through the second pin, and to control the opening and closing of the bus port through the bus port.

[0055] Optionally, in this embodiment, the second pin may include but is not limited to an OC pin, the bus pin may include but is not limited to a USB pin (or a pin supporting other bus protocols, which is not limited in this application), and the conversion chip may receive but is not limited to receiving the first target control signal through the second pin, and when the first target control signal is at a high level, connect and maintain the connection between the corresponding bus port and the conversion chip, for example, the conversion chip turns on and maintains the signal and power of the bus port, and the bus port appears to be turned on, and when the first target control signal is at a low level, disconnect the connection between the bus port and the conversion chip, for example, the conversion chip disconnects the signal and power of the bus port, and the bus port appears to be turned off.

[0056] In an exemplary embodiment, the controller is configured to perform an AND operation on the second control signal during the startup phase and the operation phase to obtain a second target control signal to control the opening and closing of the bus port, wherein when the second target control signal is at a high level, the bus port is controlled to be opened, and when the second target control signal is at a low level, the bus port is controlled to be closed.

[0057] Optionally, in this embodiment, when all control signals in the second control signal are at a high level, an AND operation is performed on the second control signal, and the obtained second target control signal is a high level; when at least one control signal in the second control signal is at a low level, an AND operation is performed on the second control signal, and the obtained second target control signal is a low level.

[0058] In an exemplary embodiment, the system includes: a load switch, wherein the load switch is connected to the processor and the bus port, respectively, and the load switch is configured to receive a second target control signal initiated by the controller in response to the second control signal during the startup phase and the operation phase, and to control the opening and closing of the bus port by controlling the opening and closing of the load switch, wherein when the second target control signal is at a low level, the load switch is controlled to be closed to control the bus port to be closed, and when the second target control signal is at a high level, the load switch is controlled to be opened to control the bus port to be opened.

[0059] Optionally, in this embodiment, a load switch and a power supply may be deployed in the server but are not limited to being connected to the bus port through the load switch. When the second target control signal is at a low level, the load switch may be controlled to be closed to disconnect the connection between the power supply and the bus port, and the bus port appears to be closed. When the second target control signal is at a high level, the load switch may be controlled to be opened to connect and maintain the connection between the power supply and the bus port, and the bus port appears to be opened.

[0060] In an exemplary embodiment, the system includes: a load switch, the load switch is connected to the controller, the controller is configured to extract the fourth control signal generated by the load switch in the POST stage, and generate a high-level fifth control signal in response to a received fifth instruction initiated by the baseboard management controller, wherein the first control signal includes the fourth control signal and the fifth control signal, and when the bus port is controlled to be turned on, the fourth control signal is at a high level, and when the bus port is controlled to be turned off, the fourth control signal is at a low level, or the controller is configured to extract the high-level fourth control signal generated by the load switch in the startup stage and the operation stage, and generate the fifth control signal in response to a received fifth instruction initiated by the baseboard management controller, wherein when the bus port is controlled to be turned on, the fifth control signal is at a high level, and when the bus port is controlled to be turned off, the fifth control signal is at a low level.

[0061] Optionally, in this embodiment, when the control bus port is desired to be turned on, the controller generates a high level fifth control signal, and when the control bus port is desired to be turned off, the controller generates a low level fifth control signal. The high level and the low level can be represented by, but not limited to, corresponding identifiers, for example, 1 represents a high level and 0 represents a low level.

[0062] In an exemplary embodiment, the system includes: a conversion chip and an expansion device, the conversion chip is connected to the processor and the controller respectively, the expansion device is connected to the processor and the controller respectively, the controller is configured to extract the sixth control signal in the second control signal generated by the expansion device in response to the sixth instruction initiated by the processor received in the POST stage; and generate a seventh control signal of a high level in the second control signal in response to the seventh instruction initiated by the baseboard management controller received, wherein the sixth control signal is a high level in the case of controlling the bus port to be turned on, and the sixth control signal is a low level in the case of controlling the bus port to be turned off; or, the controller is configured to extract the sixth control signal of a high level in the second control signal generated by the expansion device in response to the sixth instruction initiated by the processor received in the startup stage and the operation stage; and generate a seventh control signal in the second control signal in response to the seventh instruction initiated by the baseboard management controller received, wherein the seventh control signal is a high level in the case of controlling the bus port to be turned on, and the seventh control signal is a low level in the case of controlling the bus port to be turned off.

[0063] Optionally, in this embodiment, the extension device and the processor may be connected via a bus, but not limited thereto. It is understandable that the processor initiates the sixth instruction to the extension device via the bus, and the extension device responds to the received sixth instruction and generates a high-level sixth control signal. As an optional example, the sixth instruction carries a signal parameter of the sixth control signal, such as a high level or a low level.

[0064] In an exemplary embodiment, it includes: a first pin is deployed on a conversion chip, the first pin is connected to the controller, the conversion chip is configured to receive an eighth instruction initiated by the processor in response to the first instruction during the startup phase and the operation phase of the server, and generate an eighth control signal in the second control signal; the controller is configured to extract the eighth control signal through the first pin during the startup phase and the operation phase of the server.

[0065] Optionally, in this embodiment, a first pin may be deployed on the conversion chip but is not limited to being deployed. For example, the first pin may include but is not limited to a PPON pin. In this case, the controller may extract the eighth control signal generated by the conversion chip through the PPON pin. As an optional example, the eighth control signal may be but is not limited to being a high level.

[0066] In order to better understand the control system of the server bus port in the embodiment of the present application, the control system of the server bus port in the embodiment of the present application is explained and illustrated in combination with optional embodiments below, which can be applicable to but not limited to the embodiment of the present application.

[0067] Figure 2 is a schematic diagram of an optional control system of a server bus port according to an embodiment of the present application Figure 2 ,like Figure 2 As shown, it can be explained and illustrated by taking, but not limited to, a server architecture of a USB port expanded by a PCIe to USB conversion chip, a bus port including a USB port, a first controller including a CPLD, a second controller including a BMC (Baseboard Management Controller), a processor including a CPU, a conversion chip including a PCIe to USB chip, an expansion device including an IO Expander, and a load switch including a Load Switch as an example, and the BMC and BIOS can respectively control the USB port power supply and the OC pin to realize the opening and closing of the USB port.

[0068] The server is deployed with CPU0 and CPU1, CPU0 is connected to CPU1, CPU0 is used as the main processor, wherein the processor may include but is not limited to CPU0, CPU0 is connected to IO Expander and PCIe to USB chip respectively, PCIe to USB chip is deployed with OC pin (equivalent to the second pin), PPON pin (equivalent to PPON pin) and USB pin (equivalent to bus pin), USB pin is connected to USB Connector, USB Connector is deployed with bus port. USB Connector may be connected to power supply (for example, P5V_STBY) through Load Switch but is not limited to. CPLD is connected to IO Expander, BMC and PCIe to USB chip respectively, and users may set USB port to be turned on or off in BMC through network but is not limited to.

[0069] exist Figure 2Only one group of USB port design is illustrated in the figure, wherein the CPU realizes the expansion of USB port through PCIe to USB conversion chip, the conversion chip is connected to CPU through PCIe upstream, and outputs USB2.0 and USB3.0 signals to USB connector downstream to realize a group of USB interface expansion, through which the CPU system can communicate with USB devices such as U disk, mouse, keyboard, etc.; the PCIe to USB conversion chip has two pins, PPON and OC, which can control the function of the group of USB, wherein the PPON pin is used to control the power supply of the USB port, and after the conversion chip is powered on and the code is loaded, the pin will be pulled high to control the power on of the USB port, and the embodiment of the present application connects the PPON pin to CPLD through FM_CTL_PPON signal; the OC pin is used to monitor the overcurrent condition of the USB port, and when the USB port has overcurrent, the PCIe to USB conversion chip will connect the corresponding USB The port is closed and the exception is reported to the CPU system. In the embodiment of the present application, the CPLD is connected to the OC pin through the FM_OC_N signal; the BMC is connected to the CPLD through the BMC_PLD_SMBUS bus signal, and the relevant information of controlling the USB port is transmitted to the CPLD through the bus; the CPU is connected to the IO Expander through the HOST_SMBUS bus signal, and the IO expansion is realized with the help of the IO Expander, wherein the expanded FM_BIOS_PPON signal is connected to the CPLD for controlling the power supply of the USB port, and the expanded FM_BIOS_OC_N signal is used to actively trigger the overcurrent state of the USB port; the system-side P5V_STBY is connected to the USB connector through the load switch to power the USB device, and the CPLD is connected to the load switch through the FM_LS_EN signal to control the load switch, that is, the USB power supply to be turned on and off. At the same time, the CPLD monitors whether the load switch is in an overcurrent state through the FM_LS_OC_N signal.

[0070] In terms of the internal logic of CPLD, CPLD identifies the PPON_EN and OC_N signals sent by BMC by parsing I2C signals, wherein PPON and FM_BIOS_PPON\FM_CTL_PPON signals are ANDed and output to FM_LS_EN signal, that is, if any one signal is low, FM_LS_EN is low, and the load switch is turned off, and OC_N signal, FM_LS_OC_N signal and FM_BIOS_OC_N signal are ANDed and output to FM_OC_N signal, that is, if any one signal is low, FM_OC_N is low, and the port triggers the overcurrent state, turns off the USB port signal and reports the overcurrent exception to the CPU system. Through the embodiments of the present application, BMC and BIOS can respectively control the opening and closing of the USB port power control port, and can also respectively control the opening and closing of the USB port by forcing the corresponding port to sense the overcurrent abnormal state through the OC pin of the PCIe to USB conversion chip.

[0071] The method embodiments provided in the embodiments of the present application can be executed in a server device or a similar computing device. Taking running on a server device as an example, Figure 3 1 is a hardware structure block diagram of a server device of a method for controlling a server bus port according to an embodiment of the present application. Figure 3 As shown, the server device may include one or more ( Figure 3 Only one is shown in the figure) a processor 302 (the processor 302 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 304 for storing data, wherein the server device may also include a transmission device 306 and an input / output device 308 for communication functions. It can be understood by those skilled in the art that Figure 3 The structure shown is only for illustration and does not limit the structure of the above server device. Figure 3 More or fewer components as shown, or with Figure 3 Different configurations are shown.

[0072] The memory 304 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the control method of the server bus port in the embodiment of the present application. The processor 302 executes various functional applications and data processing by running the computer program stored in the memory 304, that is, to implement the above method. The memory 304 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 304 may further include a memory remotely arranged relative to the processor 302, and these remote memories may be connected to the server device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0073] The transmission device 306 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the server device. In one example, the transmission device 306 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 306 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0074] In this embodiment, a method for controlling a bus port of a server is provided. A processor, a control device and a bus port connected in sequence are deployed on the server. The server is configured to allow the operating state of the bus port to be controlled by the operating system when the operating system of the processor is running. The method is applied to a first controller, which is connected to the processor and the control device respectively. Figure 4 is a flow chart of a method for controlling a server bus port according to an embodiment of the present application. Figure 4 As shown, the process includes the following steps:

[0075] Step S402, during the process of starting the operating system, detecting the startup running state of the bus port in the operating system, wherein the startup running state is used to indicate the running state of the bus port when the operating system is started;

[0076] Step S404, generating a target control signal matching the startup operation state according to the startup operation state, wherein the target control signal is used to adjust the connection state of the power supply line of the bus port on the control device to match the startup operation state;

[0077] Step S406: sending the target control signal to the control device, wherein the control device is used to control the power supply line of the bus port according to the target control signal.

[0078] Through the above steps, the server's processor can control the opening and closing of the server's bus port in the POST stage, and the server's baseboard management controller can control the opening and closing of the bus port in the server's startup stage and operation stage. In this way, the controller can control the power supply line of the bus port according to the corresponding control signal, thereby realizing control over the opening and closing of the bus port. For example, when the power supply circuit of the bus port is disconnected, the bus port can no longer be opened through commands at the software level. Therefore, the problem of low security of the control of the server's bus port can be solved, thereby achieving the effect of improving the security of the control of the server's bus port.

[0079] In the technical solution provided in the above step S402, the startup operation status can be but is not limited to indicating the operation status to which the bus port is set during the startup of the server's operating system, for example, the bus port is set to be turned on or off during the startup of the operating system, etc.

[0080] Optionally, in this embodiment, the startup and running status of the bus port in the operating system can be detected in the following manner but is not limited to: detecting the startup and running status of the bus port from the BIOS option of the server, wherein the startup and running status of the bus port is recorded in the BIOS option, and the startup and running status of the bus port recorded in the BIOS option is set to allow adjustment.

[0081] Optionally, in this embodiment, the startup and running status of the bus port in the operating system can be detected in the following manner but is not limited to: detecting the startup and running status of the bus port set by the second controller in the server. It should be noted that the second controller can also adjust the startup and running status of the bus port at any time during the operation stage of the server.

[0082] In the technical solution provided in the above step S404, the connection status of the power supply line may include but is not limited to disconnecting the power supply line between the bus port and the control device, or connecting the power supply line between the bus port and the control device, etc. It can be understood that the power supply line may include but is not limited to a power supply line that is physically connected between the bus port and the control device.

[0083] In an exemplary embodiment, a target control signal matching the startup operation state can be generated according to the startup operation state in the following manner but is not limited to: according to the startup operation state, an initial control signal set matching the startup operation state is detected; and according to the initial control signal set, the target control signal is generated.

[0084] As an optional example, the control device includes a load switch and a conversion chip, and the detecting, based on the startup operating state, an initial control signal set matching the startup operating state includes: when the target control signal is used to adjust the connection state of the power supply line of the bus port on the load switch to match the startup operating state, detecting a first control signal set of the load switch matching the startup operating state, wherein the initial control signal set includes the first control signal set; and when the target control signal is used to adjust the connection state of the power supply line of the bus port on the conversion chip to match the startup operating state, detecting a second control signal set of the conversion chip matching the startup operating state, wherein the initial control signal set includes the second control signal set.

[0085] Optionally, in this embodiment, the first control signal set may include but is not limited to control signals for controlling the connection status of the power supply line of the bus port on the load switch, and the second control signal set may include but is not limited to control signals for controlling the connection status of the power supply line of the bus port on the conversion chip.

[0086] Figure 5 is a schematic diagram of an optional method for generating a target control signal according to an embodiment of the present application, such as Figure 5 As shown, the startup operation states allowed by the bus port may include but are not limited to startup operation state 1 to startup operation state 3. In this case, if the startup operation state desired by the user is startup operation state 2, in this case, it is possible but not limited to detecting an initial control signal set matching the startup operation state 2, and generating a target control signal based on the initial control signal set.

[0087] In an exemplary embodiment, the control device includes a load switch and a conversion chip, the first controller is connected to the load switch and the conversion chip respectively, the server is further disposed with an extension device, the first controller is connected to the extension device, and the initial control signal set matching the startup operation state is detected according to the startup operation state: a first initial control signal corresponding to the startup operation state output by the extension device is extracted, a second initial control signal corresponding to the startup operation state is detected, and a third initial control signal corresponding to the startup operation state output by the conversion chip is extracted, wherein the initial control signal set includes a first control signal set, the first control signal set includes the first initial control signal, the second initial control signal and the third initial control signal; or a fourth initial control signal corresponding to the startup operation state output by the extension device is extracted, a fifth initial control signal corresponding to the startup operation state is detected, and a sixth initial control signal corresponding to the startup operation state output by the load switch is extracted, wherein the initial control signal set includes a second control signal set, the second control signal set includes the fourth initial control signal, the fifth initial control signal and the sixth initial control signal.

[0088] As an optional example, the extension device is connected to the processor, and before extracting the first initial control signal corresponding to the startup running state output by the extension device, the method also includes: when the startup running state is extracted from the startup item, extracting the first signal parameter corresponding to the startup running state by the processor; controlling the extension device through the first bus between the processor and the extension device to generate and output the first control signal corresponding to the first signal parameter, wherein the first signal parameter is used to indicate that the first control signal is at a high level when the startup running state is used to indicate that the bus port is turned on, and indicating that the first control signal is at a low level when the startup running state is used to indicate that the bus port is turned off.

[0089] As an optional example, a target pin is deployed on the conversion chip, the first controller is connected to the first pin, and the extraction of the third initial control signal corresponding to the startup running state output by the conversion chip includes: extracting the third initial control signal through the target pin.

[0090] In an exemplary embodiment, the server is also deployed with a second controller, the first controller is connected to the second controller, and the second initial control signal corresponding to the startup operation state is detected: when the startup operation state includes the detected operation state set by the second controller, a first signal generation instruction initiated by the second controller is received, wherein the first signal generation instruction is used to instruct the first controller to generate a second initial control signal corresponding to a second signal parameter, and the second signal parameter is a signal parameter corresponding to the startup operation state set by the second controller, and the second signal parameter is used to indicate that the second initial control signal is a high level when the startup operation state is used to indicate that the bus port is turned on, and indicates that the second initial control signal is a low level when the startup operation state is used to indicate that the bus port is turned off; in response to the first signal generation instruction, a second initial control signal corresponding to the second signal parameter is generated.

[0091] Optionally, in this embodiment, the first controller and the second controller may be connected via a bus but is not limited to being connected. For example, the second controller may include but is not limited to a baseboard management controller BMC, and the first controller may include but is not limited to a CPLD or FPGA deployed in a server, etc. For example, the second controller includes a BMC and the first controller includes a CPLD, the CPLD may generate but is not limited to generating a second initial control signal in response to a received first signal generation instruction.

[0092] In an exemplary embodiment, an extension device is connected to the processor, and before extracting the fourth initial control signal corresponding to the startup operation state output by the extension device: when the startup operation state is extracted from a startup item, extracting a third signal parameter corresponding to the startup operation state by the processor, wherein the third signal parameter is used to indicate that the fourth initial control signal is at a high level when the startup operation state is used to indicate that the bus port is turned on, and to indicate that the fourth initial control signal is at a low level when the startup operation state is used to indicate that the bus port is turned off; and controlling the extension device by the processor through the first bus between the extension device and the extension device to generate and output the fourth initial control signal corresponding to the third signal parameter.

[0093] Optionally, in this embodiment, the expansion device may include, but is not limited to, a device for expanding input and output interfaces of the server. For example, the expansion device may include, but is not limited to, an IO (Input / Output) Expander.

[0094] Optionally, in the present embodiment, the startup and operating status of the bus port recorded in the startup item is set to allow adjustment. It is understandable that the startup and operating status of the bus port recorded in the startup item may change dynamically. For example, the startup and operating status of the bus port recorded in the startup item is adjusted from on to off. After the startup and operating status of the bus port recorded in the startup item is adjusted, it may take effect, but is not limited to, after the server is restarted, thereby resetting the startup and operating status of the bus port.

[0095] Optionally, in this embodiment, the processor can control the extension device to generate and output the fourth initial control signal corresponding to the third signal parameter through the first bus between the processor and the extension device in the following manner, but is not limited to: the processor sends a target instruction to the extension device through the first bus, wherein the target instruction is used to instruct the extension device to generate a fourth control signal corresponding to the third signal parameter, and the extension device is configured to generate the fourth control signal corresponding to the third signal parameter in response to the received target instruction.

[0096] In an exemplary embodiment, the server is also deployed with a second controller, the first controller is connected to the second controller, and the fifth initial control signal corresponding to the startup operation state is detected: when the startup operation state includes the detected operation state set by the second controller, a second signal generation instruction initiated by the second controller is received, wherein the second signal generation instruction is used to instruct the first controller to generate a fifth initial control signal corresponding to a fourth signal parameter, and the fourth signal parameter is a signal parameter corresponding to the startup operation state set by the second controller, and the fourth signal parameter is used to indicate that the fifth initial control signal is a high level when the startup operation state is used to indicate that the bus port is turned on, and to indicate that the fifth initial control signal is a low level when the startup operation state is used to indicate that the bus port is turned off; in response to the second signal generation instruction, the fifth initial control signal corresponding to the fourth signal parameter is generated.

[0097] Optionally, in this embodiment, the second signal generation instruction may, but is not limited to, carry a fourth signal generation parameter, or the fourth signal generation parameter may be obtained from a control method and a signal generation parameter having a corresponding relationship, wherein the control method includes a method for controlling the startup operating state, for example, the control method may, but is not limited to, include controlling the startup operating state of the bus port through a second controller, or controlling the startup operating state of the bus port by adjusting the startup item, etc.

[0098] In an exemplary embodiment, the target control signal can be generated according to the initial control signal set in the following manner, but not limited to: when the target control signal is used to adjust the connection state of the power supply line of the bus port on the load switch to match the startup operation state, performing a phase AND operation on the first control signal set to obtain a first reference control signal, wherein the initial control signal set includes the first control signal set, and the target control signal includes the first reference control signal; when the target control signal is used to adjust the connection state of the power supply line of the bus port on the conversion chip to match the startup operation state, performing a phase AND operation on the second control signal set to obtain a second reference control signal, wherein the initial control signal set includes the second control signal set, and the target control signal includes the second reference control signal.

[0099] Optionally, in this embodiment, a first reference control signal can be obtained by performing an AND operation on the first control signal set in the following manner, but is not limited to: performing an AND operation on each control signal in the first control signal set to obtain a first reference control signal, wherein, when each control signal in the first control signal set is at a high level, the first reference control signal obtained by performing an AND operation on the first control signal set is a high level; when there is at least one control signal at a low level in the first control signal set, the first reference control signal obtained by performing an AND operation on the first control signal set is a low level.

[0100] Optionally, in this embodiment, the second reference control signal can be obtained by performing an AND operation on the second control signal set in the following manner, but is not limited to: performing an AND operation on each control signal in the second control signal set to obtain a second reference control signal, wherein, when each control signal in the second control signal set is at a high level, the second reference control signal obtained by performing an AND operation on the second control signal set is a high level; when there is at least one control signal at a low level in the second control signal set, the second reference control signal obtained by performing an AND operation on the second control signal set is a low level.

[0101] In an exemplary embodiment, the first reference control signal can be obtained by performing an AND operation on the first control signal set in the following manner, but is not limited to: when the startup operation state is extracted from the startup item, and the first control signal set includes a first initial control signal, a second initial control signal and a third initial control signal, and the startup operation state is on, performing an AND operation on the first initial control signal, the second initial control signal and the third initial control signal to obtain the first reference control signal, wherein, when the startup operation state is on, the first initial control signal is set to a high level, the second initial control signal is set to a high level, and the The third initial control signal is set to a high level, and the first reference control signal is a high level; when the startup operation state is extracted from the startup item, and the first control signal set includes the first initial control signal, the second initial control signal and the third initial control signal, and the startup operation state is closed, the first initial control signal, the second initial control signal and the third initial control signal are ANDed to obtain the first reference control signal, wherein, when the startup operation state is closed, the first initial control signal is set to a low level, the second initial control signal is set to a high level, the third initial control signal is set to a high level, and the first The reference control signal is at a low level; when the startup operation state is the operation state set by the detected second controller, and the first control signal set includes a first initial control signal, a second initial control signal and a third initial control signal, and the startup operation state is when the bus port is turned on, an AND operation is performed on the first initial control signal, the second initial control signal and the third initial control signal to obtain the first reference control signal, wherein, when the startup operation state is when the bus port is turned on, the first initial control signal is set to a high level, the second initial control signal is set to a high level, the third initial control signal is set to a high level, and the first reference control signal is a high level; when the startup operation state is the operation state set by the second controller detected, and the first control signal set includes a first initial control signal, a second initial control signal and a third initial control signal, and the startup operation state is when the bus port is closed, an AND operation is performed on the first initial control signal, the second initial control signal and the third initial control signal to obtain the first reference control signal, wherein, when the startup operation state is when the bus port is closed, the first initial control signal is set to a high level, the second initial control signal is set to a low level, the third initial control signal is set to a high level, and the first reference control signal is a low level.

[0102] Optionally, in this embodiment, the control mode includes a mode for controlling the startup operation state. For example, the control mode may include, but is not limited to, controlling the startup operation state of the bus port through the second controller, or controlling the startup operation state of the bus port by adjusting the startup item, etc. In different control modes, the control signals included in the first control signal set based on which the first reference control signal is determined may include, but are not limited to, the same, but the signal parameters (for example, high level or low level, etc.) of the control signals included in the first control signal set may be, but are not limited to, different. It is understandable that for different control modes, the same control signal in the first control signal set may have different signal parameters. For example, signal A may be a high level or a low level, etc. in different control modes.

[0103] In order to better understand the control method of the server bus port in the embodiment of the present application, the control method of the server bus port in the embodiment of the present application is explained and illustrated in combination with optional embodiments below, which can be applicable to but not limited to the embodiment of the present application.

[0104] As an optional implementation, the opening and closing of the bus port can be controlled by, but not limited to, BMC or modifying BIOS options. For example, by modifying the BIOS options, the opening and closing of the USB port can be controlled by controlling the opening and closing of the power of the bus port. It should be noted that after modifying the BIOS options, the options need to be saved and the system restarted to realize the opening and closing of the USB port.

[0105] After the server system is powered on, the PCIe to USB conversion chip is powered on and the code is loaded, that is, the FM_CTL_PPON signal (equivalent to the third initial control signal, or the eighth control signal) is controlled to be pulled high, and the USB2.0 and USB3.0 signals are enabled; at this time, if the user does not perform any operation on the USB port through the BMC, the PPON_EN signal (equivalent to the second initial control signal, or the seventh control signal) and the OC_N signal (equivalent to the fifth initial control signal, or the fifth control signal) in the internal logic of the CPLD are high by default, and have no effect on the opening and closing of the USB port.

[0106] If the USB port is enabled by default in the BIOS option (equivalent to the startup item), the FM_BIOS_PPON signal (equivalent to the sixth control signal, or the first initial control signal) of the IO Expander is controlled to be high through the HOST_SMBUS bus of CPU0 during this POST loading process, and the CPLD logic ANDs the PPON signal with the FM_BIOS_PPON signal and the FM_CTL_PPON signal (equivalent to the third initial control signal, or the eighth control signal). If the result is high, the output FM_LS_EN signal (equivalent to the first reference control signal, or the second target control signal) is high, the load switch is in the on state, and P5V_STBY (equivalent to the power supply) outputs P5V_USB0 normally through the load switch. If a device such as a mouse, keyboard, or U disk is inserted, the device power supply is normal, and the USB signal can communicate normally, so the USB connector port appears to be enabled; after entering the OS, the FM_BIOS_PPON signal remains high, and the bus port of the USB connector remains in the on state.

[0107] If you modify the BIOS option to close the USB port, save the option and restart the system, then during this POST loading process, the BIOS will control the FM_BIOS_PPON signal of the IO Expander to be low through the HOST_SMBUS bus of CPU0. The CPLD logic will AND the PPON signal with the FM_BIOS_PPON signal and the FM_CTL_PPON signal. If the result is low, the output FM_LS_EN signal is low, the load switch is in the closed state, and P5V_STBY cannot output P5V_USB0 normally through the load switch. If a mouse, keyboard, U disk or other device is inserted, the USB signal can communicate normally, but there is no device power, so the USB connector port appears to be closed; after entering the OS, the FM_BIOS_PPON signal remains low, and the bus port of the USB connector remains in the closed state.

[0108] As another optional implementation, for example, the user can directly control the opening and closing of the USB port by controlling the power on and off of the bus port through the BMC. After the port status modification operation is issued under the control of the BMC, the USB port can be immediately opened and closed.

[0109] After the server system is powered on, the PCIe to USB conversion chip is powered on and the code is loaded, that is, the FM_CTL_PPON signal is controlled to be pulled high, and the USB2.0 and USB3.0 signals are enabled; at this time, the BIOS setting is to enable the USB port by default, then the FM_BIOS_PPON signal and the FM_BIOS_OC_N signal (equivalent to the third control signal, or the fourth initial control signal) are high, which has no effect on the opening and closing of the USB port.

[0110] If the user sets the USB port to be enabled by default under BMC, the BMC controls the PPON_EN signal to be high through BMC_PLM_SMBUS communication with CPLD, and the CPLD logic ANDs the PPON_EN signal with the FM_BIOS_PPON signal and the FM_CTL_PPON signal, and outputs the FM_LS_EN signal to be high, the load switch is in the on state, and P5V_STBY normally outputs P5V_USB0 through the load switch. If a mouse, keyboard, USB disk or other device is inserted, the device power is normal, and the USB signal can communicate normally, so the USB connector port is shown as enabled; if the user modifies and disables the USB port under BMC, the BMC controls the PPON_EN signal to be immediately pulled low through BMC_PLM_SMBUS communication with CPLD, and the CPLD logic ANDs the PPON_EN signal with the FM_BIOS_PPON signal and the FM_CTL_PPON signal, and outputs the FM_LS_EN signal to be low, the load switch is changed to the off state, and P5V_STBY cannot output P5V_USB0 through the load switch, the USB device power is turned off, and the USB connector port is shown as closed.

[0111] In this way, the power status of the USB port can be controlled through BIOS options and BMC to turn the USB port on and off, and the control logic of BMC and BIOS on the USB port is summarized in CPLD, realizing two different control logics of BIOS options and BMC at the same time.

[0112] In an exemplary embodiment, the second reference control signal may be obtained by performing an AND operation on the second control signal set in the following manner, but is not limited to: when the startup operation state is extracted from the startup item, and the second control signal set includes a fourth initial control signal, a fifth initial control signal and a sixth initial control signal, and the startup operation state is when the bus port is turned on, performing an AND operation on the fourth initial control signal, the fifth initial control signal and the sixth initial control signal to obtain the second reference control signal, wherein when the startup operation state is when the bus port is turned on, the fourth initial control signal is set to a high level, and the fifth initial control signal is set to a high level, The sixth initial control signal is set to a high level, and the second reference control signal is a high level; when the startup operation state is extracted from the startup item, and the second control signal set includes a fourth initial control signal, a fifth initial control signal and a sixth initial control signal, and the startup operation state is a bus port closed, an AND operation is performed on the fourth initial control signal, the fifth initial control signal and the sixth initial control signal to obtain the second reference control signal, wherein, when the startup operation state is a bus port closed, the fourth initial control signal is set to a low level, the fifth initial control signal is set to a high level, and the sixth initial control signal is set to a high level. level, the second reference control signal is a low level; when the startup operation state is the operation state set by the detected second controller, and the second control signal set includes a fourth initial control signal, a fifth initial control signal and a sixth initial control signal, and the startup operation state is a case where the bus port is turned on, an AND operation is performed on the fourth initial control signal, the fifth initial control signal and the sixth initial control signal to obtain the second reference control signal, wherein, when the startup operation state is a case where the bus port is turned on, the fourth initial control signal is set to a high level, the fifth initial control signal is set to a high level, the sixth initial control signal is set to a high level, and the second reference control signal is control signal is a high level; when the startup operation state is the operation state set by the second controller detected, and the second control signal set includes a fourth initial control signal, a fifth initial control signal and a sixth initial control signal, and the startup operation state is a case where the bus port is closed, an AND operation is performed on the fourth initial control signal, the fifth initial control signal and the sixth initial control signal to obtain the second reference control signal, wherein, when the startup operation state is a case where the bus port is closed, the fourth initial control signal is set to a high level, the fifth initial control signal is set to a low level, the sixth initial control signal is set to a high level, and the second reference control signal is a high level.

[0113] Optionally, in this embodiment, the control mode includes a mode for controlling the startup operation state. For example, the control mode may include, but is not limited to, controlling the startup operation state of the bus port through the second controller, or controlling the startup operation state of the bus port by adjusting the startup item, etc. In different control modes, the control signals included in the second control signal set based on which the second reference control signal is determined may include, but are not limited to, the same, but the signal parameters (for example, high level or low level, etc.) of the control signals included in the second control signal set may be, but are not limited to, different. It is understandable that for different control modes, the same control signal in the second control signal set may have different signal parameters. For example, signal A may be a high level or a low level, etc. in different control modes.

[0114] In order to better understand the control method of the server bus port in the embodiment of the present application, the control method of the server bus port in the embodiment of the present application is explained and illustrated in combination with optional embodiments below, which can be applicable to but not limited to the embodiment of the present application.

[0115] The opening and closing of the bus port can be controlled, but not limited to, by BMC or by modifying BIOS options. As an optional implementation, the user can modify the BIOS options to enable and disable the USB port through the OC overcurrent signal, but after modifying the BIOS options, the options need to be saved and the system restarted to enable and disable the USB port.

[0116] After the server system is powered on, the PCIe to USB conversion chip is powered on and the code is loaded, that is, the FM_CTL_PPON signal is controlled to be pulled high, and the USB2.0 and USB3.0 signals are enabled; at this time, if the user does not perform any operation on the USB port through the BMC, the PPON_EN signal and OC_N signal in the internal logic of the CPLD are high by default, and have no effect on the opening and closing of the USB port, and the BIOS does not perform additional control on the FM_BIOS_PPON signal, and the default setting is high (for example, high level), then the CPLD outputs the FM_LS_EN signal high, the load switch is in the on state, and P5V_STBY outputs P5V_USB0 normally through the load switch.

[0117] If the USB port is enabled by default, the FM_BIOS_OC_N signal of IOExpander is controlled to be high through the HOST_SMBUS bus of CPU0 during this POST loading process, and the load switch outputs power normally. In the non-OC state, the output FM_LS_OC_N signal is high, and the CPLD logic ANDs the OC_N signal with the FM_BIOS_OC_N signal and the FM_LS_OC_N signal (equivalent to the sixth initial control signal, or the fourth control signal). If the result is high, the output FM_OC_N signal (equivalent to the first target control signal, or the second reference control signal) is high, and the conversion chip is in normal working state, and the USB2.0 signal and USB3.0 signal output by the corresponding port are normal; if a mouse, keyboard, U disk or other device is inserted, the device power is normal, and the USB signal can communicate normally, so the USB connector port is shown as enabled; after entering the OS, the FM_BIOS_OC_N signal maintains a high level state, and the USB connector port maintains an enabled state.

[0118] If the BIOS option is changed to close the USB port, save the option and restart the system, then during this POST loading process, the FM_BIOS_OC_N signal of the IO Expander is controlled to be low through the HOST_SMBUS bus of CPU0, and the load switch outputs power normally. When the load switch is not in the overcurrent OC state, the output FM_LS_OC_N signal is high. The CPLD logic ANDs the OC_N signal with the FM_BIOS_OC_N signal and the FM_LS_OC_N signal. If the result is low, the output FM_OC_N signal is low, and the conversion chip enters the overcurrent abnormal working state, shuts down the relevant signals and power of the corresponding port, and the USB connector port is closed; after entering the OS, the FM_BIOS_OC_N signal maintains a low level state, and the USB connector port maintains a closed state.

[0119] In the technical solution provided in the above step S406, the control device can, but is not limited to, control the power supply line of the bus port according to the target control signal in the following manner: when the target control signal is at a low level, the power supply line of the bus port is controlled to be disconnected; when the target control signal is at a low level, the power supply line of the bus port is controlled to be connected and maintained.

[0120] As another optional implementation, the user can directly open and close the USB port through the OC overcurrent signal through the BMC. After the port status modification operation under the BMC is issued, the USB port can be opened and closed immediately.

[0121] After the server system is powered on, the PCIe to USB conversion chip is powered on and the code is loaded, that is, the FM_CTL_PPON signal is controlled to be pulled high, and the USB2.0 signal and USB3.0 signal are enabled; at this time, the BIOS setting is to enable the USB port by default, then the FM_BIOS_PPON signal and FM_BIOS_OC_N signal are high, which has no effect on the opening and closing of the USB port.

[0122] If the user sets the USB port to be enabled by default under BMC, the BMC controls OC_N to be high through BMC_PLM_SMBUS communication with CPLD, and the CPLD logic ANDs OC_N with FM_BIOS_OC_N\FM_LS_OC_N signals, outputting FM_OC_N signal to be high, the conversion chip is in normal working state, and the USB2.0 signal and USB3.0 signal outputted by the corresponding port are normal; if a device such as a mouse, keyboard, or USB disk is inserted, the device power is normal, and the USB signal can communicate normally, so the USB connector port is shown as enabled; if the user modifies and disables the USB port under BMC, the BMC controls OC_N signal to be immediately pulled low (for example, low level) through BMC_PLM_SMBUS communication with CPLD, and the CPLD logic ANDs OC_N signal with FM_BIOS_OC_N signal and FM_LS_OC_N signal, and outputs FM_OC_N signal to be low, the conversion chip enters an abnormal overcurrent working state, turns off the relevant signals and power of the corresponding port, and the USB connector port is shown as disabled.

[0123] In this way, it is possible to control the overcurrent signal status of the USB port through BIOS options and BMC to enable the USB port to be turned on and off, and the control logic of the USB port by BMC and BIOS is summarized in CPLD, and two different control logics of BIOS options and BMC are implemented at the same time.

[0124] In an exemplary embodiment, the control device includes a conversion chip and a bus connector, the conversion chip is disposed with a second pin and a bus pin, the bus connector is disposed with the bus port, the bus pin is connected to the bus connector, the first controller is connected to the second pin, and the sending of the target control signal to the control device includes: initiating the target control signal to the second pin, wherein the conversion chip is used to connect and maintain the power supply line between the bus pin and the bus port when the target control signal is at a high level, and the conversion chip is used to disconnect the power supply line between the bus pin and the bus port when the target control signal is at a low level; or, the control device includes a load switch, the first controller is connected to the load switch, and the sending of the target control signal to the control device includes: initiating the target control signal to the load switch, wherein the load switch is used to connect the power supply line between the load switch and the bus port and maintain the power supply line of the bus port when the target control signal is at a high level, and the load switch is used to disconnect the power supply line between the load switch and the bus port when the target control signal is at a low level.

[0125] Optionally, in this embodiment, when the target control signal is at a low level, the power supply line between the bus pin and the bus port may be disconnected, for example, the conversion chip may be turned off, and the bus port appears to be turned off. When the target control signal is at a high level, the power supply line between the bus pin and the bus port may be connected and maintained, for example, the conversion chip may be turned on and maintained, and the bus port appears to be turned on.

[0126] Optionally, in this embodiment, a power supply is also deployed in the server, and the power supply is connected to the bus port through a load switch. When the target control signal is at a low level, the power supply line between the power supply and the bus port can be disconnected by controlling the load switch to be turned off, thereby achieving the closing of the bus port. When the target control signal is at a low level, the power supply line between the power supply and the bus port can be connected and maintained by controlling the load switch to be turned on, thereby achieving the opening of the bus port.

[0127] It can be understood that through the embodiment of the present application, the user can realize the opening and closing of the USB port by modifying the BIOS option (equivalent to the startup item) and controlling the power supply and OC overcurrent signal respectively under the BMC. To ensure the USB security, after closing the USB port by any method, the USB port is in a closed state; in addition, for the two control methods of controlling the power supply and the OC overcurrent signal, the user can choose a single method to open and close the USB port, or turn off the power supply and the OC overcurrent signal together, and completely turn off the power supply and the signal to ensure that the USB port is completely closed. The opening and closing states of the USB port are shown in Table 1.

[0128] Table 1

[0129] ,

[0130] In Table 1, "x" indicates any state.

[0131] Through the embodiments of the present application, for the USB port expanded by the PCIe to USB conversion chip, the USB port can be turned on and off by setting the BIOS option, and the status set in the BIOS cannot be modified by software under the OS, thereby improving system security. The USB port can be turned on and off by modifying the BMC, and the change in the USB port status takes effect immediately without the need for additional restart operations.

[0132] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0133] In this embodiment, a control device for a server bus port is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and will not be repeated hereafter. As used below, the term "module" may be a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0134] Figure 6 is a structural block diagram of a control device for a server bus port according to an embodiment of the present application, such as Figure 6 As shown, the device includes a processor, a control device and a bus port connected in sequence deployed on a server, the server is configured to allow the operating state of the bus port to be controlled by the operating system when the operating system of the processor is running, the device is applied to a first controller, the first controller is connected to the processor and the control device respectively, and the device includes:

[0135] A first detection module 602 is used to detect the startup operation state of the bus port in the operating system during the startup of the operating system, wherein the startup operation state is used to indicate the operation state of the bus port when the operating system is started;

[0136] A generating module 604, configured to generate a target control signal matching the startup operation state according to the startup operation state, wherein the target control signal is used to adjust the connection state of the power supply line of the bus port on the control device to match the startup operation state;

[0137] The sending module 606 is used to send the target control signal to the control device, wherein the control device is used to control the power supply line of the bus port according to the target control signal.

[0138] Through the above-mentioned device, the server's processor can control the opening and closing of the server's bus port in the POST stage, and the server's baseboard management controller can control the opening and closing of the bus port in the server's startup stage and operation stage. In this way, the controller can control the power supply line of the bus port according to the corresponding control signal, thereby realizing the control of the opening and closing of the bus port. For example, when the power supply circuit of the bus port is disconnected, the bus port can no longer be opened through commands at the software level. Therefore, the problem of low security of the control of the server's bus port can be solved, thereby achieving the effect of improving the security of the control of the server's bus port.

[0139] In an exemplary embodiment, the generating module includes:

[0140] a detection unit, configured to detect, according to the startup operation state, an initial control signal set matching the startup operation state;

[0141] A generating unit is used to generate the target control signal according to the initial control signal set.

[0142] In an exemplary embodiment, the detection unit is used to:

[0143] Extracting a first initial control signal corresponding to the startup operation state output by the extension device, detecting a second initial control signal corresponding to the startup operation state, and extracting a third initial control signal corresponding to the startup operation state output by the conversion chip, wherein the initial control signal set includes a first control signal set, and the first control signal set includes the first initial control signal, the second initial control signal, and the third initial control signal; or,

[0144] Extract the fourth initial control signal corresponding to the startup operating state output by the extension device, detect the fifth initial control signal corresponding to the startup operating state, and extract the sixth initial control signal corresponding to the startup operating state output by the load switch, wherein the initial control signal set includes a second control signal set, and the second control signal set includes the fourth initial control signal, the fifth initial control signal and the sixth initial control signal.

[0145] In an exemplary embodiment, the server is further equipped with a second controller, the first controller is connected to the second controller, and the detection unit is used to:

[0146] In a case where the startup operation state includes the detected operation state set by the second controller, receiving a first signal generation instruction initiated by the second controller, wherein the first signal generation instruction is used to instruct the first controller to generate a second initial control signal corresponding to a second signal parameter, the second signal parameter is a signal parameter corresponding to the startup operation state set by the second controller, and the second signal parameter is used to indicate that the second initial control signal is a high level when the startup operation state is used to indicate that the bus port is turned on, and to indicate that the second initial control signal is a low level when the startup operation state is used to indicate that the bus port is turned off;

[0147] In response to the first signal generation instruction, a second initial control signal corresponding to the second signal parameter is generated.

[0148] In an exemplary embodiment, the apparatus further comprises:

[0149] an extraction module, used for connecting the extension device to the processor, before extracting the fourth initial control signal corresponding to the startup operation state output by the extension device, when the startup operation state is extracted from the startup item, extracting a third signal parameter corresponding to the startup operation state through the processor, wherein the third signal parameter is used to indicate that the fourth initial control signal is at a high level when the startup operation state is used to indicate that the bus port is turned on, and indicates that the fourth initial control signal is at a low level when the startup operation state is used to indicate that the bus port is turned off;

[0150] The output module is used to control the extension device to generate and output the fourth initial control signal corresponding to the third signal parameter through the processor and the first bus between the processor and the extension device.

[0151] In an exemplary embodiment, the server is further equipped with a second controller, the first controller is connected to the second controller, and the detection unit is used to:

[0152] In a case where the startup operation state includes the detected operation state set by the second controller, receiving a second signal generation instruction initiated by the second controller, wherein the second signal generation instruction is used to instruct the first controller to generate a fifth initial control signal corresponding to a fourth signal parameter, the fourth signal parameter is a signal parameter corresponding to the startup operation state set by the second controller, and the fourth signal parameter is used to indicate that the fifth initial control signal is at a high level when the startup operation state is used to indicate that the bus port is turned on, and to indicate that the fifth initial control signal is at a low level when the startup operation state is used to indicate that the bus port is turned off;

[0153] In response to the second signal generation instruction, the fifth initial control signal corresponding to the fourth signal parameter is generated.

[0154] In an exemplary embodiment, the generating unit is used to:

[0155] In a case where the target control signal is used to adjust the connection state of the power supply line of the bus port on the load switch to match the startup operation state, performing an AND operation on the first control signal set to obtain a first reference control signal, wherein the initial control signal set includes the first control signal set, and the target control signal includes the first reference control signal;

[0156] When the target control signal is used to adjust the connection state of the power supply line of the bus port on the conversion chip to match the startup operation state, an AND operation is performed on the second control signal set to obtain a second reference control signal, wherein the initial control signal set includes the second control signal set, and the target control signal includes the second reference control signal.

[0157] In an exemplary embodiment, the generating unit is used to:

[0158] In the case where the startup operation state is extracted from the startup item, and the first control signal set includes a first initial control signal, a second initial control signal, and a third initial control signal, and the startup operation state is on, performing an AND operation on the first initial control signal, the second initial control signal, and the third initial control signal to obtain the first reference control signal, wherein, in the case where the startup operation state is on, the first initial control signal is set to a high level, the second initial control signal is set to a high level, the third initial control signal is set to a high level, and the first reference control signal is a high level;

[0159] In the case where the startup operation state is extracted from the startup item, and the first control signal set includes a first initial control signal, a second initial control signal, and a third initial control signal, and the startup operation state is off, performing an AND operation on the first initial control signal, the second initial control signal, and the third initial control signal to obtain the first reference control signal, wherein, in the case where the startup operation state is off, the first initial control signal is set to a low level, the second initial control signal is set to a high level, the third initial control signal is set to a high level, and the first reference control signal is a low level;

[0160] In the case where the startup operation state is the operation state set by the detected second controller, and the first control signal set includes a first initial control signal, a second initial control signal and a third initial control signal, and the startup operation state is that the bus port is turned on, performing an AND operation on the first initial control signal, the second initial control signal and the third initial control signal to obtain the first reference control signal, wherein, in the case where the startup operation state is that the bus port is turned on, the first initial control signal is set to a high level, the second initial control signal is set to a high level, the third initial control signal is set to a high level, and the first reference control signal is a high level;

[0161] When the startup operation state is the operation state set by the second controller detected, and the first control signal set includes a first initial control signal, a second initial control signal and a third initial control signal, and the startup operation state is that the bus port is closed, an AND operation is performed on the first initial control signal, the second initial control signal and the third initial control signal to obtain the first reference control signal, wherein, when the startup operation state is that the bus port is closed, the first initial control signal is set to a high level, the second initial control signal is set to a low level, the third initial control signal is set to a high level, and the first reference control signal is a low level.

[0162] In an exemplary embodiment, the generating unit is further configured to:

[0163] When the startup operation state is extracted from the startup item, and the second control signal set includes a fourth initial control signal, a fifth initial control signal, and a sixth initial control signal, and the startup operation state is that the bus port is turned on, performing an AND operation on the fourth initial control signal, the fifth initial control signal, and the sixth initial control signal to obtain the second reference control signal, wherein, when the startup operation state is that the bus port is turned on, the fourth initial control signal is set to a high level, the fifth initial control signal is set to a high level, the sixth initial control signal is set to a high level, and the second reference control signal is a high level;

[0164] In the case where the startup operation state is extracted from the startup item, and the second control signal set includes a fourth initial control signal, a fifth initial control signal, and a sixth initial control signal, and the startup operation state is that the bus port is closed, performing an AND operation on the fourth initial control signal, the fifth initial control signal, and the sixth initial control signal to obtain the second reference control signal, wherein, in the case where the startup operation state is that the bus port is closed, the fourth initial control signal is set to a low level, the fifth initial control signal is set to a high level, the sixth initial control signal is set to a high level, and the second reference control signal is a low level;

[0165] When the startup operation state is the operation state set by the detected second controller, and the second control signal set includes a fourth initial control signal, a fifth initial control signal and a sixth initial control signal, and the startup operation state is that the bus port is turned on, performing an AND operation on the fourth initial control signal, the fifth initial control signal and the sixth initial control signal to obtain the second reference control signal, wherein, when the startup operation state is that the bus port is turned on, the fourth initial control signal is set to a high level, the fifth initial control signal is set to a high level, the sixth initial control signal is set to a high level, and the second reference control signal is a high level;

[0166] When the startup operating state is the operating state detected to be set by the second controller, and the second control signal set includes a fourth initial control signal, a fifth initial control signal and a sixth initial control signal, and the startup operating state is that the bus port is closed, an AND operation is performed on the fourth initial control signal, the fifth initial control signal and the sixth initial control signal to obtain the second reference control signal, wherein, when the startup operating state is that the bus port is closed, the fourth initial control signal is set to a high level, the fifth initial control signal is set to a low level, the sixth initial control signal is set to a high level, and the second reference control signal is a high level.

[0167] In an exemplary embodiment, the control device includes a conversion chip and a bus connector, the conversion chip is disposed with a second pin and a bus pin, the bus connector is disposed with the bus port, the bus pin is connected to the bus connector, the first controller is connected to the second pin, and the sending module includes:

[0168] a first initiating unit, configured to initiate the target control signal to the second pin, wherein the conversion chip is configured to connect and maintain a power supply line between the bus pin and the bus port when the target control signal is at a high level, and the conversion chip is configured to disconnect a power supply line between the bus pin and the bus port when the target control signal is at a low level; or

[0169] The control device includes a load switch, the first controller is connected to the load switch, and the sending module includes: a second initiating unit, used to initiate the target control signal to the load switch, wherein the load switch is used to connect the power supply line between the load switch and the bus port and maintain the power supply line of the bus port when the target control signal is at a high level, and the load switch is used to disconnect the power supply line between the load switch and the bus port when the target control signal is at a low level.

[0170] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0171] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0172] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0173] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0174] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0175] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above method embodiments are implemented.

[0176] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0177] An embodiment of the present application also provides a computer program, which includes computer instructions stored in a computer-readable storage medium; a processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the steps in any one of the above method embodiments.

[0178] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0179] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0180] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A control system for a server bus port, It is characterized in that include: The processor is configured to receive a first instruction in a POST phase of the BIOS of the server to control the opening and closing of the bus port of the server; A baseboard management controller is configured to receive a second instruction during a startup phase and an operation phase of the server to control the opening and closing of the bus port; a controller, connected to the processor and the baseboard management controller, respectively, the controller being configured to control the opening and closing of the bus port according to a first control signal generated by the first instruction in the POST stage, or to control the opening and closing of the bus port according to a second control signal generated by the second instruction in the startup stage and the operation stage; The controller is configured to perform an AND operation on the first control signal in the POST stage to obtain a first target control signal to control the opening and closing of the bus port, wherein when the first target control signal is at a high level, the bus port is controlled to be opened, and when the first target control signal is at a low level, the bus port is controlled to be closed; Wherein, the controller is configured to perform an AND operation on the second control signal in the startup phase and the operation phase to obtain a second target control signal to realize the control of opening and closing of the bus port, wherein when the second target control signal is at a high level, the bus port is controlled to be opened, and when the second target control signal is at a low level, the bus port is controlled to be closed.

2. The system according to claim 1, characterized in that include: An extension device, wherein the extension device is connected to the processor and the controller respectively, and the extension device is configured to receive a third instruction initiated by the processor in response to the first instruction in the POST stage to generate a third control signal in the first control signal, or to receive a fourth instruction initiated by the processor in the startup stage and the operation stage to generate the third control signal, and the controller is configured to extract the third control signal generated by the extension device, wherein when the bus port is controlled to be turned on, a high-level third control signal is generated, and when the bus port is controlled to be turned off, a low-level third control signal is generated.

3. The system according to claim 1, characterized in that include: A conversion chip is connected to the processor and the controller respectively, and is configured to receive a first target control signal initiated by the controller in response to the first control signal during the POST stage, so as to control the opening and closing of the bus port.

4. The system according to claim 3, characterized in that include: A second pin and a bus pin are disposed on the conversion chip, the second pin is connected to the controller, and the bus pin is connected to the bus port. The conversion chip is configured to receive the first target control signal through the second pin, and to control the opening and closing of the bus port through the bus port.

5. The system according to claim 1, characterized in that include: A load switch, wherein the load switch is connected to the processor and the bus port respectively, and the load switch is configured to receive a second target control signal initiated by the controller in response to the second control signal during the startup phase and the operation phase, and to control the opening and closing of the bus port by controlling the opening and closing of the load switch, wherein when the second target control signal is at a low level, the load switch is controlled to be closed to control the bus port to be closed, and when the second target control signal is at a high level, the load switch is controlled to be opened to control the bus port to be opened.

6. The system according to claim 1, characterized in that include: a load switch, the load switch being connected to the controller, the controller being configured to extract, during the POST phase, a fourth control signal generated by the load switch, and generate a fifth control signal of a high level in response to a fifth instruction received from the baseboard management controller, wherein the first control signal includes the fourth control signal and the fifth control signal, and when the bus port is controlled to be turned on, the fourth control signal is at a high level, and when the bus port is controlled to be turned off, the fourth control signal is at a low level, or, The controller is configured to extract the high-level fourth control signal generated by the load switch during the startup phase and the operation phase, and generate the fifth control signal in response to the received fifth instruction initiated by the baseboard management controller, wherein the fifth control signal is high-level when the bus port is controlled to be turned on, and is low-level when the bus port is controlled to be turned off.

7. The system according to claim 1, It is characterized in that The method comprises: a conversion chip and an expansion device, wherein the conversion chip is connected to the processor and the controller respectively, and the expansion device is connected to the processor and the controller respectively, and the controller is configured to extract, during the POST stage, a sixth control signal in the second control signal generated by the expansion device in response to a sixth instruction received from the processor; and generate a seventh control signal of a high level in the second control signal in response to a seventh instruction received from the baseboard management controller, wherein the sixth control signal is a high level when the bus port is controlled to be turned on, and the sixth control signal is a low level when the bus port is controlled to be turned off; or, The controller is configured to extract, during the startup phase and the operation phase, a high-level sixth control signal from the second control signal generated by the extension device in response to a received sixth instruction initiated by the processor; and generate a seventh control signal from the second control signal in response to a received seventh instruction initiated by the baseboard management controller, wherein the seventh control signal is high-level when the bus port is controlled to be turned on, and is low-level when the bus port is controlled to be turned off.

8. The system according to claim 1, characterized in that include: A first pin is deployed on the conversion chip, and the first pin is connected to the controller. The conversion chip is configured to receive an eighth instruction initiated by the processor in response to the first instruction during the startup phase and the operation phase of the server, and generate an eighth control signal in the second control signal. The controller is configured to extract the eighth control signal through the first pin during the startup phase and the operation phase of the server.

9. A method for controlling a server bus port, characterized in that: A processor, a control device and a bus port connected in sequence are deployed on a server, and the server is configured to allow the operating state of the bus port to be controlled by the operating system when the operating system of the processor is running. The method is applied to a first controller, and the first controller is connected to the processor and the control device respectively. The method includes: During the process of starting the operating system, detecting the startup operation state of the bus port in the operating system, wherein the startup operation state is used to indicate the operation state of the bus port when the operating system is started; According to the startup operation state, generating a target control signal matching the startup operation state, wherein the target control signal is used to adjust the connection state of the power supply line of the bus port on the control device to match the startup operation state; Sending the target control signal to the control device, wherein the control device is used to control the power supply line of the bus port according to the target control signal; Wherein, generating a target control signal matching the startup operation state according to the startup operation state includes: According to the startup operation state, detecting an initial control signal set matching the startup operation state; generating the target control signal according to the initial control signal set; The step of generating the target control signal according to the initial control signal set includes: In a case where the target control signal is used to adjust the connection state of the power supply line of the bus port on the load switch to match the startup operation state, performing an AND operation on the first control signal set to obtain a first reference control signal, wherein the initial control signal set includes the first control signal set, and the target control signal includes the first reference control signal; When the target control signal is used to adjust the connection state of the power supply line of the bus port on the conversion chip to match the startup operation state, an AND operation is performed on the second control signal set to obtain a second reference control signal, wherein the initial control signal set includes the second control signal set, and the target control signal includes the second reference control signal.

10. The method according to claim 9, characterized in that The control device includes a load switch and a conversion chip, the first controller is connected to the load switch and the conversion chip respectively, and an expansion device is also deployed in the server, the first controller is connected to the expansion device, The detecting, according to the startup operation state, an initial control signal set matching the startup operation state comprises: extracting a first initial control signal corresponding to the startup operation state output by the extension device, detecting a second initial control signal corresponding to the startup operation state, and extracting a third initial control signal corresponding to the startup operation state output by the conversion chip, wherein the initial control signal set comprises a first control signal set, the first control signal set comprises the first initial control signal, the second initial control signal and the third initial control signal; or, Extract the fourth initial control signal corresponding to the startup operating state output by the extension device, detect the fifth initial control signal corresponding to the startup operating state, and extract the sixth initial control signal corresponding to the startup operating state output by the load switch, wherein the initial control signal set includes a second control signal set, and the second control signal set includes the fourth initial control signal, the fifth initial control signal and the sixth initial control signal.

11. The method according to claim 10, characterized in that The server is further equipped with a second controller, the first controller is connected to the second controller, and the detecting of the second initial control signal corresponding to the startup operation state includes: In a case where the startup operation state includes the detected operation state set by the second controller, receiving a first signal generation instruction initiated by the second controller, wherein the first signal generation instruction is used to instruct the first controller to generate a second initial control signal corresponding to a second signal parameter, the second signal parameter is a signal parameter corresponding to the startup operation state set by the second controller, and the second signal parameter is used to indicate that the second initial control signal is a high level when the startup operation state is used to indicate that the bus port is turned on, and to indicate that the second initial control signal is a low level when the startup operation state is used to indicate that the bus port is turned off; In response to the first signal generation instruction, a second initial control signal corresponding to the second signal parameter is generated.

12. The method according to claim 10, characterized in that The extension device is connected to the processor, and before extracting the fourth initial control signal corresponding to the startup operation state output by the extension device, the method further includes: When the startup operation state is extracted from the startup item, extracting, by the processor, a third signal parameter corresponding to the startup operation state, wherein the third signal parameter is used to indicate that the fourth initial control signal is at a high level when the startup operation state is used to indicate that the bus port is turned on, and indicates that the fourth initial control signal is at a low level when the startup operation state is used to indicate that the bus port is turned off; The processor controls the extension device through the first bus between the processor and the extension device to generate and output the fourth initial control signal corresponding to the third signal parameter.

13. The method according to claim 10, characterized in that The server is further equipped with a second controller, the first controller is connected to the second controller, and the fifth initial control signal corresponding to the startup operation state is detected, including: In a case where the startup operation state includes the detected operation state set by the second controller, receiving a second signal generation instruction initiated by the second controller, wherein the second signal generation instruction is used to instruct the first controller to generate a fifth initial control signal corresponding to a fourth signal parameter, the fourth signal parameter is a signal parameter corresponding to the startup operation state set by the second controller, and the fourth signal parameter is used to indicate that the fifth initial control signal is at a high level when the startup operation state is used to indicate that the bus port is turned on, and to indicate that the fifth initial control signal is at a low level when the startup operation state is used to indicate that the bus port is turned off; In response to the second signal generation instruction, the fifth initial control signal corresponding to the fourth signal parameter is generated.

14. The method according to claim 9, characterized in that The performing an AND operation on the first control signal set to obtain a first reference control signal includes: In the case where the startup operation state is extracted from the startup item, and the first control signal set includes a first initial control signal, a second initial control signal, and a third initial control signal, and the startup operation state is on, performing an AND operation on the first initial control signal, the second initial control signal, and the third initial control signal to obtain the first reference control signal, wherein, in the case where the startup operation state is on, the first initial control signal is set to a high level, the second initial control signal is set to a high level, the third initial control signal is set to a high level, and the first reference control signal is a high level; In the case where the startup operation state is extracted from the startup item, and the first control signal set includes a first initial control signal, a second initial control signal, and a third initial control signal, and the startup operation state is off, performing an AND operation on the first initial control signal, the second initial control signal, and the third initial control signal to obtain the first reference control signal, wherein, in the case where the startup operation state is off, the first initial control signal is set to a low level, the second initial control signal is set to a high level, the third initial control signal is set to a high level, and the first reference control signal is a low level; In the case where the startup operation state is the operation state set by the detected second controller, and the first control signal set includes a first initial control signal, a second initial control signal and a third initial control signal, and the startup operation state is that the bus port is turned on, performing an AND operation on the first initial control signal, the second initial control signal and the third initial control signal to obtain the first reference control signal, wherein, in the case where the startup operation state is that the bus port is turned on, the first initial control signal is set to a high level, the second initial control signal is set to a high level, the third initial control signal is set to a high level, and the first reference control signal is a high level; When the startup operation state is the operation state set by the second controller detected, and the first control signal set includes a first initial control signal, a second initial control signal and a third initial control signal, and the startup operation state is that the bus port is closed, an AND operation is performed on the first initial control signal, the second initial control signal and the third initial control signal to obtain the first reference control signal, wherein, when the startup operation state is that the bus port is closed, the first initial control signal is set to a high level, the second initial control signal is set to a low level, the third initial control signal is set to a high level, and the first reference control signal is a low level.

15. The method according to claim 9, characterized in that The performing an AND operation on the second control signal set to obtain a second reference control signal includes: When the startup operation state is extracted from the startup item, and the second control signal set includes a fourth initial control signal, a fifth initial control signal, and a sixth initial control signal, and the startup operation state is that the bus port is turned on, performing an AND operation on the fourth initial control signal, the fifth initial control signal, and the sixth initial control signal to obtain the second reference control signal, wherein, when the startup operation state is that the bus port is turned on, the fourth initial control signal is set to a high level, the fifth initial control signal is set to a high level, the sixth initial control signal is set to a high level, and the second reference control signal is a high level; In the case where the startup operation state is extracted from the startup item, and the second control signal set includes a fourth initial control signal, a fifth initial control signal, and a sixth initial control signal, and the startup operation state is that the bus port is closed, performing an AND operation on the fourth initial control signal, the fifth initial control signal, and the sixth initial control signal to obtain the second reference control signal, wherein, in the case where the startup operation state is that the bus port is closed, the fourth initial control signal is set to a low level, the fifth initial control signal is set to a high level, the sixth initial control signal is set to a high level, and the second reference control signal is a low level; When the startup operation state is the operation state set by the detected second controller, and the second control signal set includes a fourth initial control signal, a fifth initial control signal and a sixth initial control signal, and the startup operation state is that the bus port is turned on, performing an AND operation on the fourth initial control signal, the fifth initial control signal and the sixth initial control signal to obtain the second reference control signal, wherein, when the startup operation state is that the bus port is turned on, the fourth initial control signal is set to a high level, the fifth initial control signal is set to a high level, the sixth initial control signal is set to a high level, and the second reference control signal is a high level; When the startup operating state is the operating state detected to be set by the second controller, and the second control signal set includes a fourth initial control signal, a fifth initial control signal and a sixth initial control signal, and the startup operating state is that the bus port is closed, an AND operation is performed on the fourth initial control signal, the fifth initial control signal and the sixth initial control signal to obtain the second reference control signal, wherein, when the startup operating state is that the bus port is closed, the fourth initial control signal is set to a high level, the fifth initial control signal is set to a low level, the sixth initial control signal is set to a high level, and the second reference control signal is a high level.

16. The method according to claim 9, characterized in that The control device includes a conversion chip and a bus connector, the conversion chip is provided with a second pin and a bus pin, the bus connector is provided with the bus port, the bus pin is connected to the bus connector, the first controller is connected to the second pin, and sending the target control signal to the control device includes: Initiate the target control signal to the second pin, wherein the conversion chip is used to connect and maintain the power supply line between the bus pin and the bus port when the target control signal is at a high level, and the conversion chip is used to disconnect the power supply line between the bus pin and the bus port when the target control signal is at a low level; or The control device includes a load switch, the first controller is connected to the load switch, and the sending of the target control signal to the control device includes: initiating the target control signal to the load switch, wherein the load switch is used to connect the power supply line between the load switch and the bus port and maintain the power supply line of the bus port when the target control signal is at a high level, and the load switch is used to disconnect the power supply line between the load switch and the bus port when the target control signal is at a low level.

17. A control device for a server bus port, characterized in that: A processor, a control device and a bus port connected in sequence are deployed on a server, and the server is configured to allow the operating state of the bus port to be controlled by the operating system when the operating system of the processor is running. The device is applied to a first controller, and the first controller is connected to the processor and the control device respectively. The device includes: A first detection module, configured to detect a startup operation state of the bus port in the operating system during startup of the operating system, wherein the startup operation state is used to indicate an operation state of the bus port when the operating system is started; A generating module, configured to generate a target control signal matching the startup operation state according to the startup operation state, wherein the target control signal is used to adjust the connection state of the power supply line of the bus port on the control device to match the startup operation state; A sending module, used for sending the target control signal to the control device, wherein the control device is used for controlling the power supply line of the bus port according to the target control signal; Wherein, the generating module comprises: a detection unit, configured to detect, according to the startup operation state, an initial control signal set matching the startup operation state; A generating unit, configured to generate the target control signal according to the initial control signal set; Wherein, the generating unit is used for: In a case where the target control signal is used to adjust the connection state of the power supply line of the bus port on the load switch to match the startup operation state, performing an AND operation on the first control signal set to obtain a first reference control signal, wherein the initial control signal set includes the first control signal set, and the target control signal includes the first reference control signal; When the target control signal is used to adjust the connection state of the power supply line of the bus port on the conversion chip to match the startup operation state, an AND operation is performed on the second control signal set to obtain a second reference control signal, wherein the initial control signal set includes the second control signal set, and the target control signal includes the second reference control signal.

18. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in any one of claims 9 to 16 when executed by a processor.

19. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method described in any one of claims 9 to 16 are implemented.

20. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method described in any one of claims 9 to 16 are implemented.

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