Electrostatic protection circuit

Abstract

The embodiment of the invention provides an electrostatic protection circuit and a chip. The electrostatic protection circuit is connected with an internal circuit in parallel and is connected between an IO pin and the ground, the electrostatic protection circuit comprises an isolation module and an electrostatic discharge (ESD) module, the isolation module can release charges accumulated by the IO pin to the ESD module when an ESD event occurs, the ESD module can release the charges released by the isolation module to the ground, and the ESD module can release the charges accumulated by the IO pin to the ground when the ESD event occurs. Static current is prevented from flowing into a rear-end internal circuit, and the internal circuit can be protected. According to the electrostatic protection circuit, due to the fact that the isolation module and the large-area ESD module can bear high power density, high-voltage protection can be achieved, meanwhile, due to the fact that the capacitance value of the isolation module is smaller than that of the ESD module, and the ESD module is connected with the isolation module in series, the total parasitic capacitance of the IO pin to the ground GND is determined by the capacitance value of the isolation module, and the capacitance value of the isolation module is smaller than that of the ESD module. The circuit has a low capacitance value, so that quick response can be realized.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular to an electrostatic protection circuit. Background Art

[0002] During the manufacturing, transportation and use of integrated circuit chips, a certain amount of charge will accumulate in the external environment and / or internal structure of the chip. These accumulated charges will instantly enter the integrated circuit through the chip's input or output (IO) pins, causing electrostatic discharge (ESD) problems. ESD may cause permanent damage to the tiny structures inside electronic components, so ESD protection is extremely important in the electronics industry. Especially as the feature size decreases, ESD is becoming more and more the most important reliability problem in integrated circuits, so it is necessary to design ESD protection units to effectively protect the internal circuits from ESD shocks.

[0003] Nowadays, with the advancement of high-speed communication technologies such as 5G, satellite communications, and radar systems, high-voltage and high-speed chips occupy a vital position, so ESD that can be applied in high-voltage and high-speed environments has become increasingly important. In existing technologies, large-area devices and wide metal paths required by ESD devices in high-voltage environments will introduce capacitance, while high-speed circuits require ESD protection structures to have low capacitance. The two design intentions are contradictory, so how to design high-voltage and high-speed ESD has become a difficult problem. Summary of the invention

[0004] The embodiments of the present disclosure provide an electrostatic protection circuit that can achieve high voltage protection and rapid response.

[0005] In a first aspect, the present disclosure provides an electrostatic protection circuit, which is connected in parallel with an internal circuit and between an input / output IO pin and ground. The electrostatic protection circuit includes an isolation module and an electrostatic discharge (ESD) module.

[0006] The isolation module is connected between the IO pin and the ESD module, and the capacitance value of the isolation module is smaller than the capacitance value of the ESD module.

[0007] The isolation module is configured to release the charge accumulated in the IO pin to the ESD module when an ESD event occurs. The ESD module is configured to release the charge released by the isolation module to ground.

[0008] In some embodiments of the present disclosure, the isolation module is further configured to release static current from the IO pin to the ESD module when positive charge accumulates on the IO pin and the ESD event occurs. The ESD module is further configured to release the static current from the isolation module to ground.

[0009] In some embodiments of the present disclosure, the isolation module includes a first diode, an anode of the first diode is connected to the IO pin, and a cathode of the first diode is connected to the ESD module.

[0010] In some embodiments of the present disclosure, the ESD module is further configured to release static current from the ground to the isolation module when negative charge accumulates on the IO pin and the ESD event occurs. The isolation module is further configured to release the static current from the ESD module to the IO pin.

[0011] In some embodiments of the present disclosure, the isolation module includes a second diode, a cathode of the second diode is connected to the IO pin, and an anode of the second diode is connected to the ESD module.

[0012] In some embodiments of the present disclosure, the electrostatic protection circuit further includes a clamping module, a first end of the clamping module is connected to the anode of the first diode, and a second end of the clamping module is connected to the cathode of the first diode.

[0013] The clamping module is configured to clamp the voltage of the first diode to be less than the forward conduction voltage of the first diode when the ESD event does not occur.

[0014] In some embodiments of the present disclosure, the clamping module includes a resistor, a first end of the resistor is connected to the anode of the first diode, and a second end of the resistor is connected to the cathode of the first diode.

[0015] When the ESD event does not occur, the voltage across the resistor is less than the forward conduction voltage.

[0016] In some embodiments of the present disclosure, the ESD module includes a transistor, a first end of the transistor is connected to a control end of the transistor and the isolation module, and a second end of the transistor is grounded.

[0017] The transistor is further configured to avalanche breakdown when positive charge accumulates on the IO pin and the ESD event occurs, and to forward conduct when negative charge accumulates on the IO pin and the ESD event occurs.

[0018] In some embodiments of the present disclosure, the ESD module and the isolation module are further configured to limit the voltage of the IO pin to a clamping voltage when the ESD event occurs, wherein the clamping voltage is lower than a breakdown voltage of the internal circuit.

[0019] In a second aspect, the present disclosure provides a chip, including an internal circuit, an IO pin, and any electrostatic protection circuit provided in the first aspect.

[0020] In the technical solution of the embodiment of the present disclosure, the electrostatic protection circuit is connected in parallel with the internal circuit and connected between the IO pin and the ground. The electrostatic protection circuit includes an isolation module and an electrostatic discharge ESD module. The isolation module can release the charge accumulated in the IO pin to the ESD module when an ESD event occurs. The ESD module can release the charge released by the isolation module to the ground to prevent static current from flowing into the internal circuit at the rear end, thereby protecting the internal circuit. Since the isolation module and the large-area ESD module can withstand high power density, high-voltage protection can be achieved. At the same time, since the capacitance value of the isolation module is less than the capacitance value of the ESD module, the ESD module is connected in series with the isolation module, so the total parasitic capacitance of the IO pin to the ground GND is determined by the capacitance value of the isolation module, and the circuit has a lower capacitance value, thereby being able to respond quickly.

[0021] The above description is only an overview of the technical solution of the embodiment of the present application. In order to more clearly understand the technical means of the embodiment of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiment of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, a brief introduction will be given below to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 A schematic diagram of the structure of an electrostatic protection circuit provided in an embodiment of the present disclosure.

[0024] Figure 2 A circuit diagram of an electrostatic protection circuit provided in an embodiment of the present disclosure.

[0025] Figure 3 A circuit diagram of another electrostatic protection circuit provided in an embodiment of the present disclosure.

[0026] Figure 4 A schematic diagram of the structure of a chip provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0028] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the disclosed subject matter belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" together shall mean that the parts are joined together directly or through one or more intermediate components.

[0029] Reference to "embodiments" in this disclosure means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase "embodiments" in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described in this disclosure may be combined with other embodiments.

[0030] In addition, the terms "first", "second", etc. in the specification and claims of the present disclosure or the above-mentioned drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.

[0031] The term "and / or" in this disclosure is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0032] In the description of the present disclosure, unless otherwise specified, "plurality" and "at least two" mean more than two (including two), and similarly, "multiple groups" and "at least two groups" mean more than two groups (including two).

[0033] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0034] The ESD phenomenon in the present disclosure refers to the accumulation of a certain amount of charge in the external environment and / or internal structure of an integrated circuit chip during its manufacture, transportation and use, and these accumulated charges instantly enter the interior of the integrated circuit through the chip's IO pins.

[0035] ESD may cause permanent damage to the tiny structures inside electronic components, such as transistors, diodes, and integrated circuits. This damage may be immediate or latent and gradually manifest itself in subsequent use. ESD protection is extremely important in the electronics industry. In particular, integrated circuit manufacturing technology has entered the nano era. With the reduction of feature size, ESD issues are becoming more and more the main reliability issues in integrated circuits.

[0036] There are three main ways to solve the ESD problem: the first is to avoid the occurrence of ESD; the second is to use off-chip dedicated ESD protection devices; the third is to design on-chip ESD protection units. In actual ESD solutions, the ESD problem is usually solved by all three methods at the same time. However, since ESD events can be controlled but not eliminated, and off-chip ESD protection devices take up a lot of additional system-level and / or board-level resources, the most economical and effective solution to the ESD problem is to reasonably design on-chip ESD protection units to effectively protect the internal circuits from ESD shocks.

[0037] Nowadays, with the advancement of high-speed communication technologies such as 5G, satellite communications, and radar systems, high-voltage and high-speed chips occupy a vital position, so ESD that can be applied in high-voltage and high-speed has become increasingly important. In a high-voltage environment, the occurrence of ESD will release a huge amount of energy. The protection structure must be able to withstand high power density without damage, and at the same time, it needs to quickly disperse this energy to avoid overheating caused by heat accumulation. Therefore, ESD devices need to have a large enough area and the metal channel needs to be very wide to meet the high-voltage environment. Large-area devices and wide metal paths will introduce large capacitance. High-speed circuits require ESD protection structures to respond and conduct quickly to limit transient voltage spikes. At the same time, high-speed signal integrity requires ESD protection structures to have low capacitance and low insertion loss to avoid negative effects on signal quality.

[0038] In summary, the large-area devices and wide metal paths required in high-voltage environments will introduce capacitance, while high-speed circuits require ESD protection structures to have low capacitance. The two design intentions contradict each other, so how to design high-voltage and high-speed ESD has become a difficult problem.

[0039] In order to solve the above technical problems, the embodiments of the present disclosure provide an electrostatic protection circuit, which is connected in parallel with the internal circuit and between the IO pin and the ground. The electrostatic protection circuit includes an isolation module and an electrostatic discharge ESD module. When an ESD event occurs, the isolation module can release the charge accumulated in the IO pin to the ESD module, and the ESD module can release the charge released by the isolation module to the ground, thereby preventing static current from flowing into the internal circuit at the rear end, and protecting the internal circuit. Since the isolation module and the large-area ESD module can withstand high power density, high-voltage protection can be achieved. At the same time, since the capacitance value of the isolation module is less than the capacitance value of the ESD module, the ESD module is connected in series with the isolation module, so the total parasitic capacitance of the IO pin to the ground GND is determined by the capacitance value of the isolation module, and the circuit has a lower capacitance value, thereby being able to respond quickly.

[0040] The technical solution of the present disclosure is described in detail below with reference to several specific embodiments.

[0041] Figure 1 A schematic diagram of a structure of an electrostatic protection circuit provided in an embodiment of the present disclosure is shown in FIG. Figure 1 As shown, the electrostatic protection circuit 100 is connected in parallel with the internal circuit 200 and connected between the IO pin and the ground GND. The electrostatic protection circuit 100 includes an isolation module 110 and an ESD module 120, wherein the isolation module 110 is connected between the IO pin and the ESD module 120, and the capacitance value of the isolation module 110 is less than the capacitance value of the ESD module 120.

[0042] The isolation module 110 is configured to, when an ESD event occurs, release the charges accumulated in the IO pin to the ESD module 120. The ESD module 120 is configured to release the charges released by the isolation module 110 to the ground GND.

[0043] For example, Figure 2 A circuit diagram of an electrostatic protection circuit provided by an embodiment of the present disclosure is shown in FIG. Figure 2 As shown, the isolation module 110 includes a first diode D1 , wherein an anode of the first diode D1 is connected to the IO pin, and a cathode of the first diode D1 is connected to the ESD module 120 .

[0044] Specifically, the anode of the first diode D1 is connected to the first end of the internal circuit 200 and the IO pin, the cathode of the first diode D1 is connected to the first end of the ESD module 120, and the second end of the ESD module 120 and the second end of the internal circuit 200 are grounded.

[0045] When positive charges are accumulated on the IO pin and the voltage of the IO pin increases, an ESD event occurs, the first diode D1 is forward-conducted, and the accumulated positive charges flow from the IO pin through the first diode D1 to the ESD module 120, that is, the static current flows from the IO pin through the first diode D1 to the ESD module 120. Since the forward-conducting first diode D1 can withstand high power density, the isolation module 110 can withstand high power density.

[0046] When the voltage exceeds the breakdown voltage of the internal device of the ESD module 120, the internal device generates an avalanche breakdown, causing the impedance of the ESD module 120 to drop sharply, thereby forming a low-impedance conductive path. The positive charge output by the first diode D1 flows through the ESD module 120 to the ground GND, that is, the static current output by the first diode D1 flows through the ESD module 120 to the ground GND.

[0047] In this way, when positive charge accumulates on the IO pin and an ESD event occurs, the isolation module 110 can release the static current from the IO pin to the ESD module 120, and the ESD module 120 can release the static current from the isolation module 110 to the ground GND to prevent the static current from flowing into the internal circuit 200 at the back end, thereby protecting the internal circuit 200.

[0048] Since the isolation module 110 and the large-area ESD module 120 can withstand high power density, the electrostatic protection circuit 100 can achieve high-voltage protection. In addition, the ESD module 120 and the first diode D1 have different mechanisms for discharging charges, resulting in the size of the first diode D1 being much smaller than the size of the ESD module 120 when discharging the same positive charge. The capacitance value of the first diode D1 is smaller than the capacitance value of the ESD module 120, that is, the capacitance value of the isolation module 110 is smaller than the capacitance value of the ESD module 120. Since the ESD module 120 is connected in series with the isolation module 110, the total parasitic capacitance of the IO pin to the ground GND is determined by the capacitance value of the isolation module 110, so the electrostatic protection circuit 100 has a lower capacitance value, thereby enabling a fast response.

[0049] In some embodiments, see Figure 2 The isolation module 110 further includes a second diode D2 , a cathode of the second diode D2 is connected to the IO pin, and an anode of the second diode D2 is connected to the ESD module 120 .

[0050] Exemplarily, the cathode of the second diode D2 is connected to the IO pin, the first end of the internal circuit 200 and the anode of the first diode D1 , and the anode of the second diode D2 is connected to the cathode of the first diode D1 and the first end of the ESD module 120 .

[0051] Specifically, when negative charges accumulate on the IO pin and the voltage of the IO pin decreases, an ESD event occurs, the second diode D2 is forward-conducted, and the accumulated negative charges flow from the IO pin through the second diode D2 to the ESD module 120, that is, the static current flows from the ESD module 120 through the second diode D2 to the IO pin. Since the forward-conducting second diode D2 can withstand high power density, the isolation module 110 can withstand high power density.

[0052] When the voltage exceeds the forward conduction voltage of the internal device of the ESD module 120, the internal device conducts forward to form a low impedance conductive path. The negative charge output by the second diode D2 flows through the ESD module 120 to the ground GND, that is, the static current output by the ground GND flows through the ESD module 120 to the second diode D2.

[0053] In this way, when negative charge accumulates on the IO pin and an ESD event occurs, the ESD module 120 can release the static current from the ground GND to the isolation module 110, and the isolation module 110 can release the static current from the ESD module 120 to the IO pin to prevent the static current from flowing into the internal circuit 200 at the back end, thereby protecting the internal circuit 200.

[0054] When positive charge accumulates on the IO pin and an ESD event occurs, the first diode D1 is forward-conducted, and the internal devices of the ESD module 120 avalanche breakdown to form a low-impedance conductive path. The static current flows from the IO pin through the first diode D1 and the ESD module 120 in sequence and then flows to the ground GND. The forward-conducting first diode D1 can withstand high power density.

[0055] In summary, no matter whether positive charge or negative charge is accumulated on the IO pin, the isolation module 110 and the ESD module 120 can cooperate to release the charge from the IO pin to the ground GND to prevent static current from flowing into the internal circuit 200 at the back end, thereby protecting the internal circuit 200.

[0056] The first forward-conducting diode D1 and the second forward-conducting diode D2 can both withstand high power density, so whether positive charge or negative charge is accumulated on the IO pin, the isolation module 110 can withstand high power density. In other words, the isolation module 110 and the large-area ESD module 120 can withstand high power density, so the electrostatic protection circuit 100 can achieve high voltage protection.

[0057] The ESD module 120 discharges positive charges based on avalanche breakdown and discharges negative charges based on forward conduction, and the isolation module 110 discharges positive charges based on the forward conduction of the first diode D1 and discharges negative charges based on the forward conduction of the second diode D2. The ESD module 120 discharges positive charges based on the mechanism of avalanche breakdown, so that the ESD module 120 has a larger size than the isolation module 110, and the capacitance value of the isolation module 110 is smaller than the capacitance value of the ESD module 120. Since the ESD module 120 is connected in series with the isolation module 110, the total parasitic capacitance of the IO pin to the ground GND is determined by the capacitance value of the isolation module 110, so the electrostatic protection circuit 100 has a lower capacitance value, so that it can respond quickly.

[0058] In some embodiments, see Figure 2 The ESD module 120 includes a transistor M, a first end of the transistor M is connected to a control end of the transistor M and the isolation module 110, and a second end of the transistor M is grounded GND.

[0059] The transistor M is further configured to avalanche breakdown when positive charges are accumulated on the IO pin and an ESD event occurs, and to forward conduct when negative charges are accumulated on the IO pin and an ESD event occurs.

[0060] For example, Figure 2 As shown, the transistor M is a bipolar junction transistor (BJT), the emitter of the transistor M is connected to the base of the transistor M, the cathode of the first diode D1 and the anode of the second diode D2, and the collector of the transistor M is grounded GND.

[0061] Specifically, under normal working conditions, the transistor M is in a high impedance state, which hardly affects the normal transmission of signals.

[0062] When positive charge accumulates on the IO pin and an ESD event occurs, the IO pin voltage suddenly increases. Once it exceeds the breakdown voltage of the internal diode of the transistor M, the diode will produce an avalanche breakdown, and the impedance of the transistor M will drop sharply, thereby forming a low-impedance conductive path with the forward-conducting first diode D1. The static current flows into the ground GND through this path, which can prevent the static current from flowing into the internal circuit 200 at the back end, thereby protecting the internal circuit 200.

[0063] Since the process of the static current flowing into the ground GND through the path is very fast, usually completed in nanoseconds, it can ensure that the static electricity protection circuit 100 responds quickly.

[0064] When the ESD time is over, transistor M automatically returns to a high impedance state, and the circuit returns to normal operating mode without affecting signal quality and device performance.

[0065] When negative charge accumulates on the IO pin and an ESD event occurs, the IO pin voltage suddenly decreases, and the transistor M and the second diode D2 are both forward-conducted to form a low-impedance conductive path. Static current flows from the ground GND into the IO pin through the path, which can prevent the static current from flowing into the internal circuit 200 at the back end, thereby protecting the internal circuit 200.

[0066] In some embodiments, when positive charge accumulates on the IO pin and an ESD event occurs, when the static current passes through the first diode D1 and the transistor M, the forward-conducting first diode D1 and the avalanche-breakdown-conducting transistor M can limit the voltage across the internal circuit 200 to a first clamping voltage, that is, the voltage of the IO pin is limited to the first clamping voltage, and the first clamping voltage is less than the breakdown voltage of the internal circuit 200, thereby avoiding damage to the internal circuit 200.

[0067] When negative charge accumulates on the IO pin and an ESD event occurs, when the static current passes through the second diode D2 and the transistor M, the forward-conducting second diode D2 and the forward-conducting transistor M can limit the voltage of the IO pin to a second clamping voltage, and the second clamping voltage is less than the breakdown voltage of the internal circuit 200, thereby avoiding damage to the internal circuit 200.

[0068] In this way, when an ESD event occurs, the ESD module 120 and the isolation module 110 cooperate to limit the voltage of the IO pin to a clamping voltage, wherein the clamping voltage is lower than the breakdown voltage of the internal circuit 200 to avoid damage to the internal circuit 200 .

[0069] In some embodiments, Figure 3 A circuit diagram of another electrostatic protection circuit provided by an embodiment of the present disclosure is shown in FIG. Figure 3 As shown, the electrostatic protection circuit 100 further includes a clamping module 130 , wherein a first end of the clamping module 130 is connected to the anode of the first diode D1 , and a second end of the clamping module 130 is connected to the cathode of the first diode D1 .

[0070] The clamping module 130 is configured to clamp the voltage of the first diode D1 to be less than the forward conduction voltage of the first diode D1 when no ESD event occurs.

[0071] For example, Figure 3 As shown, the clamping module 130 includes a resistor R, a first end of the resistor R is connected to the anode of the first diode D1 , and a second end of the resistor R is connected to the cathode of the first diode D1 .

[0072] Specifically, the ESD module 120 has reverse leakage current, and the reverse leakage current will cause the first diode D1 to be in a forward conduction state through the first diode D1. It is not desirable for the first diode D1 to be in a forward conduction state during normal operation.

[0073] In this way, a resistor R is connected in parallel at both ends of the first diode D1, and when no ESD event occurs, the reverse leakage current flows into the resistor R and forms a potential difference at both ends of the resistor R. Since the potential difference at both ends of the resistor R is smaller than the forward conduction voltage of the first diode D1, the first diode D1 can be prevented from being in a forward conduction state during normal operation.

[0074] In other implementations, the clamping module 130 may also be a Schottky diode, or other types of devices with a clamping function, and the present disclosure does not impose any specific limitation on this.

[0075] The embodiment of the present disclosure further provides a chip, comprising the electrostatic protection circuit 100 provided in any of the above embodiments.

[0076] For example, Figure 4 A schematic diagram of the structure of a chip provided in an embodiment of the present disclosure is shown in FIG. Figure 4 As shown, the chip includes an electrostatic protection circuit 100, an internal circuit 200 and an IO pin. The IO pin is connected to a first end of the electrostatic protection circuit 100 and a first end of the internal circuit 200, and a second end of the electrostatic protection circuit 100 and a second end of the internal circuit 200 are grounded GND.

[0077] The chip provided in the embodiments of the present disclosure includes the electrostatic protection circuit 100 provided in any of the above embodiments, and has the same functional modules and beneficial effects as the electrostatic protection circuit 100, which will not be repeated here.

[0078] Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it is located after a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0079] Further aspects and scopes of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present application can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended for purposes of illustration only and are not intended to limit the scope of the present application.

[0080] Several embodiments of the present disclosure are described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the attached claims.

Claims

1. An electrostatic protection circuit, characterized in that: The electrostatic protection circuit is connected in parallel with the internal circuit and between the input and output IO pins and the ground, and the electrostatic protection circuit includes an isolation module and an electrostatic discharge (ESD) module; The isolation module is connected between the IO pin and the ESD module, and the capacitance value of the isolation module is smaller than the capacitance value of the ESD module; The isolation module is configured to release the charge accumulated in the IO pin to the ESD module when an ESD event occurs; The ESD module is configured to discharge the charges discharged by the isolation module to ground.

2. The electrostatic protection circuit according to claim 1, characterized in that: The isolation module is further configured to release static current from the IO pin to the ESD module when positive charge accumulates on the IO pin and the ESD event occurs; The ESD module is further configured to discharge the static current from the isolation module to ground.

3. The electrostatic protection circuit according to claim 2, characterized in that: The isolation module includes a first diode; An anode of the first diode is connected to the IO pin, and a cathode of the first diode is connected to the ESD module.

4. The electrostatic protection circuit according to claim 3, characterized in that: The ESD module is further configured to release static current from the ground to the isolation module when negative charge accumulates on the IO pin and the ESD event occurs; The isolation module is further configured to discharge the static current from the ESD module to the IO pin.

5. The electrostatic protection circuit according to claim 4, characterized in that: The isolation module includes a second diode; A cathode of the second diode is connected to the IO pin, and an anode of the second diode is connected to the ESD module.

6. The electrostatic protection circuit according to claim 3, characterized in that: The electrostatic protection circuit also includes a clamping module; The first end of the clamping module is connected to the anode of the first diode, and the second end of the clamping module is connected to the cathode of the first diode; The clamping module is configured to clamp the voltage of the first diode to be less than the forward conduction voltage of the first diode when the ESD event does not occur.

7. The electrostatic protection circuit according to claim 6, characterized in that: The clamping module includes a resistor; The first end of the resistor is connected to the anode of the first diode, and the second end of the resistor is connected to the cathode of the first diode; When the ESD event does not occur, the voltage across the resistor is less than the forward conduction voltage.

8. The electrostatic protection circuit according to any one of claims 1 to 7, characterized in that: The ESD module includes a transistor; The first end of the transistor is connected to the control end of the transistor and the isolation module, and the second end of the transistor is grounded; The transistor is further configured to avalanche breakdown when positive charge accumulates on the IO pin and the ESD event occurs, and to forward conduct when negative charge accumulates on the IO pin and the ESD event occurs.

9. The electrostatic protection circuit according to any one of claims 1 to 7, characterized in that: The ESD module and the isolation module are further configured to limit the voltage of the IO pin to a clamping voltage when the ESD event occurs; wherein the clamping voltage is less than a breakdown voltage of the internal circuit.

10. A chip, characterized in that: It comprises an internal circuit, an IO pin and the electrostatic protection circuit according to any one of claims 1 to 9.

Images