HDCP receiver and display device

Abstract

The invention discloses an HDCP receiver and a display device. An algorithm circuit of the HDCP receiver can calculate a receiving end authentication key, and an interface circuit can allow an HDCP transmitter to read the receiving end authentication key, so that the HDCP transmitter authenticates the receiving end authentication key and sends an encrypted video stream to the interface circuit after the authentication is passed. A data decryption circuit in the HDCP receiver can decrypt the video stream using the data decryption password. Wherein the data decryption password is calculated based on the receiving end authentication key. The algorithm circuit in the HDCP receiver can directly calculate the receiving end authentication key, so that the key calculation by the processor is not needed, and the load of the processor is effectively reduced.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to an HDCP receiver and a display device. Background Art

[0002] High-bandwidth digital content protection system (HDCP) is a content protection system based on data encryption and authorization verification, which is widely used in high-definition multimedia interface (HDMI). HDCP can solve the problem that digital video content provided by computers or other digital video content providers can be copied and broadcasted multiple times without degradation of the source signal quality.

[0003] In order to protect the video data, the HDCP transmitting device and the HDCP receiving device need to exchange authentication keys to achieve device authentication. After the authentication is passed, the HDCP transmitting device can send the video stream to the HDCP receiving device.

[0004] However, the above solution usually requires the processor to calculate the authentication key, resulting in a high load on the processor. Summary of the invention

[0005] The present application provides an HDCP receiver and display device, which can solve the technical problem that the processor is loaded with a high load due to the calculation of the authentication key by the processor. The technical solution is as follows:

[0006] In a first aspect, an HDCP receiver is provided, which is applied to a display device; the HDCP receiver comprises: an algorithm circuit, an interface circuit and a data decryption circuit;

[0007] The algorithm circuit is used to calculate the receiving end authentication key;

[0008] The interface circuit is used for the HDCP transmitter to read the receiving end authentication key, so that the HDCP transmitter authenticates the receiving end authentication key based on the transmitting end authentication key, and sends the video stream to the interface circuit after the authentication is passed;

[0009] The data decryption circuit is used to calculate a data decryption password based on the receiving end authentication key, and decrypt the video stream based on the data decryption password.

[0010] Optionally, the display device further includes a processor;

[0011] The interface circuit is further used to receive the first key information sent by the processor, receive the second key information sent by the HDCP transmitter, and be used for the HDCP transmitter to read the first key information so that the HDCP transmitter calculates the transmitting end authentication key based on the first key information;

[0012] The algorithm circuit is used to calculate the first key information and the second key information using an encryption algorithm to obtain the receiving end authentication key.

[0013] Optionally, the interface circuit includes: a high-performance extended bus interface (advanced extensible interface, AXI) circuit, and an inter-integrated circuit (inter-integrated circuit, I2C) interface circuit;

[0014] The AXI circuit is used to connect to the processor, and the I2C interface circuit is used to connect to the HDCP transmitter.

[0015] Optionally, the HDCP receiver further comprises: an interrupt circuit;

[0016] The interrupt circuit is used to send an interrupt request to the processor after the interface circuit interacts with the HDCP transmitter;

[0017] The interface circuit is further configured to receive a first calculation instruction sent by the processor, where the first calculation instruction is sent by the processor based on the interrupt request;

[0018] The algorithm circuit is used to calculate the first key information and the second key information using an encryption algorithm under the instruction of the first calculation instruction to obtain the receiving end authentication key.

[0019] Optionally, the HDCP receiver further includes: an instruction register, a key memory and a first channel register;

[0020] The instruction register is used to store the first computing instruction sent by the processor;

[0021] The key storage device is used to store the first key information sent by the processor;

[0022] The first channel register is used to store the second key information and the receiving end authentication key.

[0023] Optionally, the algorithm circuit comprises: a first algorithm subcircuit and a second algorithm subcircuit, wherein different versions of the encryption algorithm are configured in the first algorithm subcircuit and the second algorithm subcircuit;

[0024] The HDCP receiver further includes: a multiplexer, the multiplexer being connected to the instruction register, the first channel register, the first algorithm subcircuit and the second algorithm subcircuit respectively;

[0025] The instruction register is further used to store a second computing instruction sent by the processor through the interface circuit;

[0026] The multiplexer is used to obtain the second secret key information stored in the first channel register according to the first calculation instruction, and is used to transmit the obtained second secret key information to the first algorithm sub-circuit or the second algorithm sub-circuit according to the second calculation instruction.

[0027] Optionally, the HDCP receiver further comprises: a second channel register, and the multiplexer is further connected to the second channel register;

[0028] The instruction register is further used to store a third computing instruction sent by the processor through the interface circuit;

[0029] The second channel register is used to store input parameters sent by the processor through the interface circuit;

[0030] The multiplexer is further configured to obtain the input parameter stored in the second channel register according to the third calculation instruction, and transmit the input parameter to the algorithm circuit;

[0031] The algorithm circuit is further used to calculate the input parameters using the encryption algorithm and write the calculation results into the second channel register for reading by the processor.

[0032] Optionally, the data decryption circuit includes: an HDCP cipher subcircuit, a signal decoding subcircuit and a decryption subcircuit;

[0033] The HDCP cryptographic subcircuit is used to calculate a data decryption cryptogram based on the receiving end authentication key;

[0034] The signal decoding subcircuit is used to decode the video stream;

[0035] The decryption subcircuit is used to decrypt the decoded video stream using the data decryption password.

[0036] In a second aspect, a display device is provided, the display device comprising: a processor, and the HDCP receiver as described in the first aspect;

[0037] The processor is used to send first key information to the HDCP receiver, receive an interrupt request sent by the HDCP receiver, and send a first calculation instruction to the HDCP receiver based on the interrupt request; the first calculation instruction is used to instruct the HDCP receiver to calculate a receiving end authentication key based on the first key information.

[0038] Optionally, the processor is further used to send a second calculation instruction to the HDCP receiver, where the second calculation instruction is used to instruct the HDCP receiver to calculate the receiving end authentication key through the first algorithm subcircuit or the second algorithm subcircuit.

[0039] The beneficial effects of the technical solution provided by this application include at least:

[0040] The present application provides an HDCP receiver and a display device. The algorithm circuit of the HDCP receiver can calculate the receiving end authentication key, and the interface circuit can allow the HDCP transmitter to read the receiving end authentication key, so that the HDCP transmitter can authenticate the receiving end authentication key and send the encrypted video stream to the interface circuit after the authentication is passed. The data decryption circuit in the HDCP receiver can decrypt the video stream using a data decryption password. Among them, the data decryption password is calculated based on the receiving end authentication key. Since the algorithm circuit in the HDCP receiver can directly calculate the receiving end authentication key, there is no need for the processor to perform key calculation, thereby effectively reducing the load on the processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0042] Figure 1 is a structural diagram of an HDCP receiver provided in an embodiment of the present application;

[0043] Figure 2 is a structural diagram of another HDCP receiver provided in an embodiment of the present application;

[0044] Figure 3 It is a partial structural diagram of an HDCP receiver provided in an embodiment of the present application;

[0045] Figure 4 It is a structural schematic diagram of a data decryption circuit provided in an embodiment of the present application;

[0046] Figure 5It is a timing diagram of a password valid signal and a password received signal provided in an embodiment of the present application;

[0047] Figure 6 is a schematic diagram of a TMDS cycle of a video frame provided in an embodiment of the present application;

[0048] Figure 7 is a flowchart of an initialization process provided by an embodiment of the present application;

[0049] Figure 8 It is a schematic diagram of an HDCP authentication process provided by an embodiment of the present application;

[0050] Fig. 9 It is a structural schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0052] The embodiment of the present application provides an HDCP receiver, which can be applied to a display device. The display device can be a television, a computer, a monitor or a projector, etc. In addition, the HDCP receiver can be connected to an HDCP transmitter in a video stream sending device. The video stream sending device can be a set-top box, a player or a computer, etc. Among them, the video stream sending device and the display device can be connected via HDMI or a digital visual interface (DVI). In addition, the video stream sending device can send a video stream to the display device via HDMI or DVI.

[0053] Figure 1 is a structural diagram of an HDCP receiver provided in an embodiment of the present application, such as Figure 1 As shown, the HDCP receiver 01 includes: an algorithm circuit 10, an interface circuit 20 and a data decryption circuit 30.

[0054] The algorithm circuit 10 is used to calculate the receiving end authentication key.

[0055] The interface circuit 20 is used for the HDCP transmitter 03 to read the receiving end authentication key, so that the HDCP transmitter 03 authenticates the receiving end authentication key based on the transmitting end authentication key, and after the authentication is passed, sends the video stream to the interface circuit 20. It can be understood that if the HDCP transmitter 03 detects that the receiving end authentication key is the same as the transmitting end authentication key, it can be determined that the HDCP receiver 01 is authenticated.

[0056] The data decryption circuit 30 is used to calculate a data decryption password based on the receiving end authentication key, and decrypt the video stream sent by the HDCP transmitter 03 based on the data decryption password.

[0057] It is understandable that, after determining that the HDCP receiver 01 has passed the authentication, the HDCP transmitter 03 can also use the transmitting authentication key to calculate the data encryption password, encrypt the video stream to be sent based on the data encryption password, and send the encrypted video stream to the HDCP receiver 01. Based on the authentication mechanism between the HDCP transmitter 03 and the HDCP receiver 01, it can be ensured that the data encryption password is the same as the data decryption password, and further ensure that the data decryption circuit 30 can correctly restore the original video stream after decrypting the encrypted video stream using the data decryption password.

[0058] Since the algorithm circuit of the HDCP receiver provided in the embodiment of the present application can directly calculate the receiving end authentication key, there is no need for the processor to perform key calculation, thereby effectively reducing the load on the processor.

[0059] Optionally, refer to Figure 1 The display device may also include a processor 02.

[0060] The interface circuit 20 is connected to the processor 02 in the display device and the HDCP transmitter 03 respectively. The interface circuit 20 is also used to receive the first key information sent by the processor 02, and receive the second key information and the video stream sent by the HDCP transmitter 03, and is used for the HDCP transmitter 03 to read the first key information so that the HDCP transmitter 03 calculates the transmitting end authentication key based on the first key information. The first key information may be pre-configured in the display device, and the second key information may be pre-configured in the video stream sending device.

[0061] The algorithm circuit 10 is used to calculate the first key information and the second key information using an encryption algorithm to obtain a receiving end authentication key.

[0062] The algorithm circuit 10 is pre-configured with an encryption algorithm, and the algorithm circuit 10 can use the encryption algorithm to calculate the first key information of the display device and the second key information of the video stream sending device to obtain a receiving end authentication key.

[0063] Optionally, continue to refer to Figure 1, the HDCP receiver 01 may also include an interrupt circuit 40. The interrupt circuit 40 is used to send an interrupt request (IRQ) to the processor 02 after the interface circuit 20 exchanges data with the HDCP transmitter 03. In addition, the interrupt circuit 40 may also send an interrupt request to the processor 02 after the algorithm circuit 10 performs a calculation operation. That is, each time the interface circuit 20 receives data sent by the HDCP transmitter 03, each time the HDCP transmitter 03 reads data in the HDCP receiver 01 through the interface circuit 20, and each time the algorithm circuit 10 performs a calculation operation, the interrupt circuit 40 may send an interrupt request to the processor 02. In this way, it can be ensured that the processor 02 accurately knows the authentication progress between the HDCP transmitter 03 and the HDCP receiver 01, and sends corresponding instructions.

[0064] The interface circuit 20 can also be used to receive a first calculation instruction sent by the processor 02. The algorithm circuit 10 can be used to calculate the first key information and the second key information using an encryption algorithm under the instruction of the first calculation instruction to obtain a receiving end authentication key.

[0065] The first calculation instruction may be sent by the processor 02 based on an interrupt request. For example, the processor 02 may send the first calculation instruction to the HDCP receiver 01 after receiving an interrupt request indicating that the interface circuit 20 has received the second key information.

[0066] In the embodiment of the present application, the interrupt circuit of the HDCP receiver can send an interrupt request to the processor after each data exchange between the interface circuit and the HDCP transmitter, and after each calculation operation performed by the algorithm circuit, so that the processor can determine the authentication progress between the HDCP receiver and the HDCP transmitter and send corresponding instructions. Since the HDCP receiver can calculate the receiving end authentication key under the instruction of the processor, that is, the receiving end authentication key can be calculated by the hardware circuit, the processor does not need to calculate the receiving end authentication key, thereby effectively reducing the load of the processor.

[0067] Furthermore, in the solution provided by the embodiment of the present application, the HDCP receiver sends an interrupt to the processor during the authentication process, and performs hardware calculations under the instruction of the processor, thereby realizing the HDCP authentication process through a combination of software and hardware. In this combination of software and hardware, the HDCP receiver only needs to focus on hardware calculations, without considering the switching between various processes during the authentication process, so the complexity of the hardware code can also be effectively reduced. In addition, this combination of software and hardware can also improve compatibility with different video stream sending devices, and its application flexibility is higher.

[0068] Optionally, Figure 2is a schematic diagram of the structure of another HDCP receiver provided in an embodiment of the present application. Figure 2 As shown, the interface circuit 20 may include: an AXI circuit 201 and an I2C interface circuit 202 .

[0069] The AXI circuit 201 is used to connect to the processor 02 and receive the first key information and the first calculation instruction sent by the processor 02. The processor 02 may be a central processing unit (CPU). For example, the processor 02 may be a processor with security attributes (such as a firewall) to ensure the reliability of the first key information sent by the processor 02 to the AXI circuit 201.

[0070] The I2C interface circuit 202 is used to connect to the HDCP transmitter 03 and to exchange data with the HDCP transmitter 03. The data may include key information and video stream.

[0071] For example, the display device to which the HDCP receiver 01 belongs may include an HDMI receiving (receive, RX) circuit, and the video stream sending device may include an HDMI transmitting (transit, TX) circuit. The HDMI transmitting circuit includes an HDCP transmitter 03, and the HDMI receiving circuit includes an HDCP receiver 01. The HDMI transmitting circuit and the HDMI receiving circuit are connected via HDMI, and the I2C interface circuit 202 may be a part of HDMI.

[0072] Figure 3 is a partial structural diagram of an HDCP receiver provided in an embodiment of the present application. Figure 2 and Figure 3 The HDCP receiver 01 may further include: a command (CMD) register 50, a key memory 60 and a channel register bank 70. The channel register bank 70 may include a plurality of channel registers, and the plurality of channel registers at least include: a first channel register 701.

[0073] The instruction register 50 is used to store the first computing instruction sent by the processor 02. The process of the processor 02 sending the instruction can also be understood as: the processor 02 writes the instruction to the instruction register 50 through the interface circuit 20 (such as the AXI circuit 201). The instruction register 50 is also called a command decoder (CMD decoder), which can be used to decode the instruction sent by the processor 02.

[0074] The key memory 60 is used to store the first key information sent by the processor 02. The key memory 60 may be a static random-access memory (SRAM).

[0075] The first channel register 701 is used to store the second key information and the receiving end authentication key.

[0076] It can be understood that the interface circuit 20 of the HDCP receiver 01 may include multiple I2C interface circuits 202, and different I2C interface circuits 202 can be connected to different HDCP transmitters 03. That is, the display device to which the HDCP receiver 01 belongs may have multiple HDMI interfaces, and the multiple HDMI interfaces can be connected to different video stream sending devices. The channel register group 70 may include multiple first channel registers 701 corresponding to the multiple I2C interface circuits 202, and each first channel register 701 is used to store the second key information written by the corresponding I2C interface circuit 202. The algorithm circuit 10 can be multiplexed by multiple first channel registers 701 to authenticate with the HDCP transmitters 03 in different video stream sending devices.

[0077] Alternatively, if Figure 2 and Figure 3 As shown, the algorithm circuit 10 may include: a first algorithm subcircuit 101 and a second algorithm subcircuit 102. The first algorithm subcircuit 101 and the second algorithm subcircuit 102 are configured with different versions of encryption algorithms. For example, the first algorithm subcircuit 101 is configured with an HDCP1.4 algorithm, and the second algorithm subcircuit 102 is configured with an HDCP2.3 algorithm. Figure 2 , the HDCP1.4 algorithm may include km generation (generate, gen) and ks generation algorithms, etc., and km and ks are keys required to be calculated during the authentication process. The HDCP2.3 algorithm may include: RSA-OAEP decryption algorithm, secure hash algorithm (secure hash algorithm, SHA) 256 encryption algorithm, HMAC-SHA256 encryption algorithm and advanced encryption standard (advanced encryption standard, AES) encryption algorithm, etc. Among them, OAEP refers to optimal asymmetric encryption padding, and HMAC refers to a key-related hash operation message authentication code.

[0078] For the scenario where the algorithm circuit 20 includes two algorithm sub-circuits, such as Figure 2 and Figure 3 As shown, the HDCP receiver 01 may further include a multiplexer MUX. The control end of the multiplexer MUX may be connected to the instruction register 50, the first end of the multiplexer MUX is connected to the first channel register 701, and the second end of the multiplexer MUX is connected to the first algorithm subcircuit 101 and the second algorithm subcircuit 102 respectively.

[0079] Among them, the instruction register 50 is also used to store the second calculation instruction sent by the processor 02 through the interface circuit 20 (for example, the AXI circuit 201). The multiplexer MUX can be used to obtain the second secret key information from the first channel register 701 according to the first calculation instruction, and can be used to transmit the obtained second secret key information to the first algorithm subcircuit 101 or the second algorithm subcircuit 102 according to the second calculation instruction. That is, the multiplexer MUX can send the second key information stored in the first channel register 701 to the first algorithm subcircuit 101 or the second algorithm subcircuit 102 under the instruction of the second calculation instruction. Or it can be understood that: the processor 02 can instruct the HDCP receiver 01 to use different versions of encryption algorithms to process the first key information and the second key information through the second calculation instruction to calculate the receiving end authentication key.

[0080] Optionally, the processor 02 may determine the version of the encryption algorithm required to be adopted by the HDCP receiver 01 according to the interrupt sent by the HDCP transmitter 03, and send a corresponding second calculation instruction.

[0081] It is understandable that the contents of the first key information and the second key information are different according to the different versions of the encryption algorithm required to be adopted by the HDCP receiver 01. The first key information may be the key information of the HDCP receiver 01 specified in the corresponding version of the encryption algorithm protocol, which includes the secret key information used to calculate the receiving end authentication key and the key information for the HDCP transmitter 03 to read. The second key information may be the key information of the HDCP transmitter 03 specified in the corresponding version of the encryption algorithm protocol, which includes the secret key information used to calculate the transmitting end authentication key and the key information for sending to the HDCP receiver 01.

[0082] For example, if the encryption algorithm used by the HDCP transmitter 03 and the HDCP receiver 01 is the HDCP1.4 algorithm, the first key information and the second key information are the key information of the receiving end and the sending end respectively specified in the HDCP1.4 algorithm protocol. If the encryption algorithm used is the HDCP2.3 algorithm, the first key information and the second key information are the key information of the receiving end and the sending end respectively specified in the HDCP2.3 algorithm protocol.

[0083] It can also be understood that the key memory 60, the instruction register 50 and the channel register set 70 in the HDCP receiver 01 have different base addresses.

[0084] Optionally, continue to refer to Figure 3 The channel register group 70 in the HDCP receiver 01 may further include: a second channel register 702. The first end of the multiplexer MUX may also be connected to the second channel register 702.

[0085] The instruction register 50 may also be used to store a third computing instruction sent by the processor 02 through the interface circuit 20. For example, the processor 02 may send the third computing instruction through the AXI circuit 201.

[0086] The second channel register 702 may be used to store input parameters sent by the processor 02 through the interface circuit 20 .

[0087] The multiplexer MUX is further configured to obtain the input parameter stored in the second channel register 70 according to the third calculation instruction, and transmit the input parameter to the algorithm circuit 20 .

[0088] Correspondingly, the algorithm circuit 20 can also be used to calculate the input parameters using an encryption algorithm, and write the calculation results to the second channel register 702 for the processor 02 to read.

[0089] For example, the second channel register 702 can be a 1 kilobit (kb) space register, which is used to allocate corresponding space for the input parameters of the encryption algorithm. When applied, the processor 02 only needs to write the input parameters of the encryption algorithm into the corresponding second channel register 702, and send a third calculation instruction to instruct the algorithm circuit 20 to perform the calculation. After the algorithm circuit 20 completes the calculation, the calculation result can be written back to the second channel register 702 again. In addition, the interrupt circuit 30 can also send an interrupt request to the processor 02 after the algorithm circuit 20 completes the calculation, and the processor 02 can read the calculation result from the second channel register 702 based on the interrupt request.

[0090] It can be understood that the above-mentioned input parameters can be other parameters that need to be processed by the encryption algorithm in addition to the key information, that is, the input parameters are parameters that are unrelated to the HDCP authentication process. That is, the encryption algorithm configured in the algorithm circuit 20 can not only calculate the authentication key during the HDCP authentication process, but also be reused by other processes as a general algorithm intellectual property (IP) algorithm. As a result, the code utilization rate of the encryption algorithm in the algorithm circuit 20 is effectively improved. In addition, the processor 02 can call the encryption algorithm in the algorithm circuit 20 by writing the input parameters and the third calculation instruction. The calling process is relatively simple and efficient, and can further reduce the load on the processor 02.

[0091] Optionally, the RSA-OAEP algorithm, SHA256 algorithm, HMAC-SHA256 algorithm and AES encryption algorithm configured in the second algorithm subcircuit 102 can be reused as a general algorithm by other processes. That is, the multiplexer MUX can send the input parameters stored in the second channel register 702 to the second algorithm subcircuit 102 in the algorithm circuit 20 under the instruction of the third calculation instruction.

[0092] Figure 4 Schematic diagram of a data decryption circuit provided by an embodiment of the present application. Figure 4 As shown, the data decryption circuit 30 may include: an HDCP cipher subcircuit 301 , a signal decoding subcircuit 302 and a decryption subcircuit 303 .

[0093] The HDCP cryptographic subcircuit 301 is used to calculate a data decryption password based on a receiving end authentication key. The signal decoding subcircuit 302 is used to decode a video stream received from the HDCP transmitter 03. The decryption subcircuit 303 is used to decrypt the decoded video stream using the data decryption password calculated by the HDCP cryptographic subcircuit 301.

[0094] For example, the signal decoding subcircuit 302 may be a transition minimized differential signal TMDS decoding circuit. Figure 4As shown, the HDCP transmitter 03 may include a data encryption circuit, which includes an HDCP cipher circuit, a TMDS encoder, and an encryption circuit. The HDCP cipher circuit is also called an HDCP cipher, which is used to generate a data encryption cipher based on the transmitting end authentication key, the encryption circuit is used to encrypt the video stream to be transmitted using the data encryption cipher, and the TMDS encoder is used to encode the encrypted video stream using the TMDS algorithm. Accordingly, the signal decoding subcircuit 302 can first decode the received video stream using the TMDS algorithm, and then the decryption subcircuit 303 decrypts the decoded video stream.

[0095] refer to Figure 4 It can be seen that the encryption circuit can be an XOR circuit, and the decryption subcircuit 303 can also be an XOR circuit. Among them, the HDCP cryptographic circuit in the data encryption circuit can generate a 24-bit pseudo-random number (pseudo-random-data) as a data encryption password, and the encryption circuit can perform bitwise XOR on the 24-bit data in the video stream and the 24-bit data encryption password. The data decryption password generated by the HDCP cryptographic subcircuit 301 can also be a 24-bit pseudo-random number, and the decryption subcircuit 303 can perform bitwise XOR on the 24-bit data in the decoded video stream and the 24-bit data decryption password, thereby restoring the original video stream.

[0096] Optionally, the HDCP password subcircuit 301 is used to periodically update the data decryption password based on the receiving end authentication key, and to output the password validity signal vld and the password reception signal acpt. For example, the HDCP password subcircuit 301 can update the data decryption password when the password reset (rekey) enable signal is at the second level. The password reset enable signal can be periodically at the second level, and the HDCP password subcircuit 301 can periodically update the data decryption password under the control of the password reset enable signal.

[0097] Furthermore, during the process of the HDCP cipher subcircuit 301 updating the data decryption cipher, the cipher valid signal vld outputted by the HDCP cipher subcircuit 301 is at the first level, and after the data decryption cipher is updated, the cipher valid signal vld outputted by the HDCP cipher subcircuit 301 is at the second level. During the data island period and the video data period of the video stream, the cipher receiving signal acpt is at the second level, and during the control period of the video stream, the cipher receiving signal acpt is at the first level. Figure 5It can be seen that the second level of the password validity signal vld and the password reception signal acpt can both be a high level, and the first level can both be a low level.

[0098] The decryption subcircuit 303 is further used to obtain the data decryption password output by the HDCP password subcircuit 301 when the password validity signal vld and the password reception signal acpt are both at the second level.

[0099] Based on the above timing design, it can be ensured that each 24-bit data decryption password generated by the HDCP cipher subcircuit 301 corresponds to each 24-bit data output by the signal decoding subcircuit 302, thereby ensuring correct decryption of the video stream.

[0100] It is understandable that the first level may also be referred to as an invalid level, and the second level may also be referred to as a valid level. Furthermore, the second level may be a high level relative to the first level.

[0101] Figure 6 Schematic diagram of a TMDS cycle of a video frame provided by an embodiment of the present application. Figure 6 As shown, each video frame may include a control period, a data island period and a video data period. Furthermore, the display process of each video frame may include a vertical blanking phase, a horizontal blanking phase and an active video phase. The vertical blanking phase and the horizontal blanking phase both include a plurality of staggered data island periods and control periods, and the active video phase includes a plurality of video data periods. Since the video stream needs to be decrypted in both the data island period and the video data period, and the video stream does not need to be decrypted in the control period, the above-mentioned password receiving signal acpt is at the second level in both the data island period and the video data period, and can be at the first level in the control period.

[0102] Furthermore, it is understandable that Figure 6 The VSYNC shown in the figure is a vertical synchronization signal, also known as a frame synchronization signal, indicating the start of scanning a frame. The HSYNC is a horizontal synchronization signal, also known as a line synchronization signal, indicating the start of scanning a line (i.e., a pixel row).

[0103] Optionally, in the embodiment of the present application, the authentication process between the HDCP receiver 01 and the HDCP transmitter 03 may include an initialization phase and an authentication phase. Figure 7As shown, the processor 02 may first perform reset de-assert and clock enable operations. Afterwards, the processor 02 may configure the first key information through the interface circuit 20 (e.g., the AXI circuit 201), and select an encryption algorithm through a second calculation instruction. For example, the processor 02 may select the HDCP1.4 algorithm or the HDCP2.3 algorithm.

[0104] In the authentication phase, the HDCP receiver 01 and the HDCP transmitter 03 can respectively calculate and exchange authentication keys to achieve authentication. Afterwards, in the data encryption phase, the HDCP receiver 01 and the HDCP transmitter 03 can respectively calculate the data encryption password and the data decryption password for encrypting and decrypting the video stream based on the calculated authentication key. The following takes the first authentication phase of the HDCP1.4 algorithm as an example to introduce the authentication process.

[0105] like Figure 8 As shown, the HDCP transmitter 03 (i.e., HDCP TX) can first read the configuration information Bcaps and Bstatus from the HDCP receiver 01 (i.e., HDCP RX) through the interface circuit 20 (e.g., I2C interface circuit 202). Afterwards, the HDCP transmitter 03 can write the second key information to the HDCP receiver 01 through the I2C interface circuit 202. The second key information may include three keys, namely, Ainfo, An, and AKSV. Among them, the length of Ainfo is 1 byte, An is a pseudo-random code with a length of 64 bits, and AKSV is the key selection vector (KSV) of the HDCP transmitter 03, and its length is 40 bits.

[0106] After receiving the second key information, the HDCP receiver 01 can update the second key information to the channel register group 70, and after updating a key in the second key information, an interrupt request can be sent to the processor 02 (such as CPU) through the interrupt circuit 40. Since the second key information includes three keys, the interrupt circuit 40 will send three interrupt requests to the processor 02. After receiving the three interrupt requests, the processor 02 can send a first calculation instruction to the HDCP receiver 01, for example, the first calculation instruction can be written into the instruction register 50 of the HDCP receiver 01.

[0107] Continue to refer Figure 8, after writing the second key information, the HDCP transmitter 03 can read the first key information from the HDCP receiver 01 through the interface circuit 20 (for example, the I2C interface circuit 202). As mentioned above, the first key information is written to the HDCP receiver 01 by the processor 02. In addition, the first key information may include BKSV and a device private key. Among them, BKSV is the KSV of the HDCP receiver 01, which is a 40-bit binary number. The device private key is a collection of 40 56-bit keys. In an embodiment of the present application, the HDCP transmitter 03 can read the BKSV in the first key information, and can also read the repeater bit in the Bcaps. The Bcaps may include a relay bit, for example, the 6th bit is a relay bit, and the relay bit is used to characterize whether the HDCP receiver 01 is an HDCP repeater. As Figure 8 As shown, after the HDCP receiver 01 detects that the HDCP transmitter 03 reads the relay bit and the BKSV in the first key information, it can send an interrupt request to the processor 02 through the interrupt circuit 40, and the processor 02 can perform a clear interrupt (clear IRQ) operation.

[0108] It is understandable that after the HDCP receiver 01 and the HDCP transmitter 03 exchange KSV, they need to first verify whether the other party's KSV is valid. If it is valid, continue to execute subsequent steps.

[0109] After the HDCP receiver 01 receives the first calculation instruction sent by the processor 02, it can calculate the receiving end authentication key based on the first key information and the second key information. The receiving end authentication key may include Ks', M0' and R0'. For example, the HDCP receiver 01 can first generate a shared key Km' based on its own device private key (i.e., Bkeys) and the KSV (i.e., AKSV) of the HDCP transmitter 03. Afterwards, the receiving end authentication key Ks', M0' and R0' are generated based on the shared key Km', the relay bit and the pseudo-random code An. In an embodiment of the present application, the HDCP receiver 01 can send R0' in the receiving end authentication key to the HDCP transmitter 03 for authentication by the HDCP transmitter 03.

[0110] Correspondingly, the HDCP transmitter 03 can also generate a shared key Km based on its own device private key (i.e., Akeys) and the KSV (i.e., BKSV) of the HDCP receiver 01. Afterwards, the transmitting authentication keys Ks, M0, and R0 are generated based on the shared key Km, the relay bit, and the pseudo-random code An. After the HDCP transmitter 03 reads R0' in the receiving authentication key of the HDCP receiver 01, it can verify whether R0' in the receiving authentication key is the same as R0 in the calculated transmitting authentication key. If R0' in the receiving authentication key is the same as R0 in the transmitting authentication key, the HDCP transmitter 03 can determine that the first authentication stage has passed, and can continue to execute subsequent authentication stages.

[0111] For example, if the HDCP receiver 01 is an HDCP repeater, the HDCP transmitter 03 and the HDCP receiver 01 can continue to perform the operations of the second authentication stage and the third authentication stage. If the HDCP receiver 01 is not an HDCP repeater, the HDCP transmitter 03 and the HDCP receiver 01 can directly perform the operations of the third authentication stage. In the embodiment of the present application, the HDCP receiver 01 is usually not an HDCP repeater, so the operations of the third authentication stage can be directly performed.

[0112] It is understandable that in the above first authentication stage, if Figure 8 As shown, after the HDCP receiver 01 calculates the receiving end authentication key Ks', M0' and R0', it can send an interrupt request to the processor 02 through the interrupt circuit 40, and the processor 02 can perform the clear interrupt operation. In addition, after the HDCP receiver 01 detects that the HDCP transmitter 03 reads R0' in the receiving end authentication key, it can also send an interrupt request to the processor 02 through the interrupt circuit 40, and the processor 02 can perform the clear interrupt operation.

[0113] In the third authentication phase (also called the content encryption phase) of the HDCP1.4 algorithm, the HDCP receiver 01 and the HDCP transmitter 03 can respectively calculate the new password initial values ​​Ki and Mi based on the receiving end authentication key calculated in the first authentication phase, and calculate the authentication key Ri, where i is the frame number of the video stream. Among them, the authentication key Ri can be used for link integrity check, and the authentication key Ri can be updated every 128 frames. For example, the HDCP transmitter 03 can periodically read (for example, once every 2 seconds) the authentication key Ri calculated by the HDCP receiver 01, and verify whether the authentication key Ri it reads is consistent with the authentication key Ri calculated by itself. If the two are consistent, it can be determined that the verification is successful.

[0114] In the third authentication stage, the HDCP transmitter 03 can also calculate the 24-bit data encryption password based on the Ks in the authentication key of the transmitting end, the pseudo-random code An, and the password initial values ​​Ki and Mi. Correspondingly, the HDCP receiver 01 can also calculate the 24-bit data decryption password based on the Ks' in the authentication key of the receiving end, the pseudo-random code An, and the password initial values ​​Ki and Mi. It can be understood that the third authentication stage can be performed by the cipher subcircuit 301, which is also called an HDCP cipher.

[0115] Example, reference Figure 5 , the cryptographic subcircuit 301 may be initialized based on the initialization signal init, for example, after detecting the pulse of the initialization signal init. Furthermore, the authentication key Ri may be updated based on the first calculation signal vb_calc, and the data decryption password may be updated based on the second calculation signal hb_calc. For example, the authentication key Ri may be updated after detecting the pulse of the first calculation signal vb_calc, and the data decryption password may be recalculated after detecting the pulse of the second calculation signal hb_calc. Figure 5 In the timing sequence shown, the second level (i.e., the effective level) is a high level. Figure 5 It can be seen that the password sub-circuit 301 can pull down the level of the password valid signal vld during the process of calculating the data decryption password. After updating the authentication key Ri, the password sub-circuit 301 can output a Ri update signal ri_upd pulse.

[0116] Optionally, the first calculation signal vb_calc can be generated based on the vertical synchronization signal VSYNC. The second calculation signal hb_calc can be generated based on a password reset (rekey) enable signal, for example, the second calculation signal hb_calc can be a rekey enable signal. The rekey enable signal is valid in the horizontal blanking phase.

[0117] Optionally, the HDCP receiver 01 provided in the embodiment of the present application may be implemented using a system on chip (SOC).

[0118] In summary, an embodiment of the present application provides an HDCP receiver, the interface circuit of which can receive the first key information and the first calculation instruction sent by the processor, and receive the second key information sent by the HDCP transmitter. The algorithm circuit of the HDCP receiver can calculate the first key information and the second key information based on the first calculation instruction using an encryption algorithm to obtain a receiving end authentication key for the HDCP transmitter to authenticate. The interrupt circuit of the HDCP receiver can send an interrupt request to the processor after each data exchange between the interface circuit and the HDCP transmitter, and after the algorithm circuit performs a calculation operation, so that the processor determines the authentication progress between the HDCP receiver and the HDCP transmitter and sends corresponding instructions. Since the HDCP receiver can calculate the receiving end authentication key under the instruction of the processor, that is, the receiving end authentication key can be calculated by the hardware circuit, there is no need for the processor to calculate the receiving end authentication key, thereby effectively reducing the load of the processor.

[0119] Fig. 9 is a schematic diagram of the structure of a display device provided in an embodiment of the present application. Fig. 9 As shown, the display device includes: a processor 02, and an HDCP receiver 01 as provided in the above embodiment.

[0120] The processor 02 is used to send the first key information to the HDCP receiver 01, receive the interrupt request sent by the HDCP receiver 01, and send a first calculation instruction to the HDCP receiver 01 based on the interrupt request. The first calculation instruction is used to instruct the HDCP receiver 01 to calculate the receiving end authentication key based on the first key information.

[0121] Optionally, the processor 02 may be a CPU, for example, a CPU with security properties (such as a firewall). The first key information may include a BKSV of the display device and a device private key of the display device.

[0122] Optionally, the processor 02 may also be used to send a second calculation instruction to the HDCP receiver 01. The second calculation instruction is used to instruct the HDCP receiver 01 to calculate the receiving end authentication key through the first algorithm subcircuit or the second algorithm subcircuit.

[0123] Optionally, the processor 02 may also be configured to send input parameters and a third calculation instruction to the HDCP receiver 01, and obtain a calculation result obtained by the HDCP receiver 01 by performing encryption calculation on the input parameters.

[0124] The third calculation instruction is used to instruct the HDCP receiver 01 to use the encryption algorithm to calculate the input parameter to obtain the calculation result. After the HDCP receiver 01 calculates the calculation result, it can send an interrupt request to the processor 02, and the processor 02 can read the calculation result from the HDCP receiver 01 based on the terminal request.

[0125] It is understandable that the above input parameters can be parameters that are unrelated to the HDCP authentication process, that is, the processor 02 can instruct the HDCP receiver 01 to use the encryption algorithm to perform encryption calculations on parameters in other processes to achieve reuse of the encryption algorithm in the HDCP receiver 01. Thus, the code utilization rate of the encryption algorithm in the HDCP receiver 01 is effectively improved.

[0126] Based on the above analysis, it can be known that the first calculation instruction sent by the processor 02 is an instruction for instructing the HDCP receiver 01 to calculate the receiving end authentication key. The second calculation instruction sent by the processor 02 is an instruction for selecting the version of the encryption algorithm, that is, the second calculation instruction is used to instruct the HDCP receiver 01 to use the first algorithm subcircuit or the second algorithm subcircuit to calculate the receiving end authentication key. The third calculation instruction sent by the processor 02 is an instruction for instructing the HDCP receiver 01 to use the encryption algorithm to perform encryption calculation on the input parameters, that is, the third calculation instruction is an instruction for multiplexing the encryption algorithm in the HDCP receiver 01.

[0127] In this application, the terms "first", "second", etc. are used to distinguish identical or similar items with basically the same effects and functions. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is there any limitation on quantity and execution order.

[0128] The above description is only an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. An HDCP receiver, characterized in that: Applicable to display devices; the HDCP receiver includes: an algorithm circuit, an interface circuit and a data decryption circuit; The algorithm circuit is used to calculate the receiving end authentication key; The interface circuit is used for the HDCP transmitter to read the receiving end authentication key, so that the HDCP transmitter authenticates the receiving end authentication key based on the transmitting end authentication key, and sends the video stream to the interface circuit after the authentication is passed; The data decryption circuit is used to calculate a data decryption password based on the receiving end authentication key, and decrypt the video stream based on the data decryption password.

2. The HDCP receiver according to claim 1, wherein: The display device also includes a processor; The interface circuit is further used to receive the first key information sent by the processor, receive the second key information sent by the HDCP transmitter, and be used for the HDCP transmitter to read the first key information so that the HDCP transmitter calculates the transmitting end authentication key based on the first key information; The algorithm circuit is used to calculate the first key information and the second key information using an encryption algorithm to obtain the receiving end authentication key.

3. The HDCP receiver according to claim 2, characterized in that The interface circuit includes: a high-performance expansion bus interface AXI circuit, and an internal integrated circuit I2C interface circuit; The AXI circuit is used to connect to the processor, and the I2C interface circuit is used to connect to the HDCP transmitter.

4. The HDCP receiver according to claim 2, wherein: The HDCP receiver further includes: an interrupt circuit; The interrupt circuit is used to send an interrupt request to the processor after the interface circuit interacts with the HDCP transmitter; The interface circuit is further configured to receive a first calculation instruction sent by the processor, where the first calculation instruction is sent by the processor based on the interrupt request; The algorithm circuit is used to calculate the first key information and the second key information using an encryption algorithm under the instruction of the first calculation instruction to obtain the receiving end authentication key.

5. The HDCP receiver according to claim 4, characterized in that: The HDCP receiver also includes: an instruction register, a key memory and a first channel register; The instruction register is used to store the first computing instruction sent by the processor; The key storage device is used to store the first key information sent by the processor; The first channel register is used to store the second key information and the receiving end authentication key.

6. The HDCP receiver according to claim 5, characterized in that: The algorithm circuit comprises: a first algorithm subcircuit and a second algorithm subcircuit, wherein the first algorithm subcircuit and the second algorithm subcircuit are configured with different versions of the encryption algorithm; The HDCP receiver further includes: a multiplexer, the multiplexer being connected to the instruction register, the first channel register, the first algorithm subcircuit and the second algorithm subcircuit respectively; The instruction register is further used to store a second computing instruction sent by the processor through the interface circuit; The multiplexer is used to obtain the second secret key information stored in the first channel register according to the first calculation instruction, and is used to transmit the obtained second secret key information to the first algorithm sub-circuit or the second algorithm sub-circuit according to the second calculation instruction.

7. The HDCP receiver according to claim 6, wherein: The HDCP receiver further comprises: a second channel register, and the multiplexer is further connected to the second channel register; The instruction register is further used to store a third computing instruction sent by the processor through the interface circuit; The second channel register is used to store input parameters sent by the processor through the interface circuit; The multiplexer is further configured to obtain the input parameter stored in the second channel register according to the third calculation instruction, and transmit the input parameter to the algorithm circuit; The algorithm circuit is further used to calculate the input parameters using the encryption algorithm and write the calculation results into the second channel register for reading by the processor.

8. The HDCP receiver according to any one of claims 1 to 7, characterized in that: The data decryption circuit includes: an HDCP cipher subcircuit, a signal decoding subcircuit and a decryption subcircuit; The HDCP cryptographic subcircuit is used to calculate a data decryption cryptogram based on the receiving end authentication key; The signal decoding subcircuit is used to decode the video stream; The decryption subcircuit is used to decrypt the decoded video stream using the data decryption password.

9. A display device, characterized in that: The display device comprises: a processor, and an HDCP receiver as claimed in any one of claims 1 to 8; The processor is configured to send first key information to the HDCP receiver, receive an interrupt request sent by the HDCP receiver, and send a first calculation instruction to the HDCP receiver according to the interrupt request; The first calculation instruction is used to instruct the HDCP receiver to calculate a receiving end authentication key based on the first key information.

10. The display device according to claim 9, characterized in that The processor is further used to send a second calculation instruction to the HDCP receiver, where the second calculation instruction is used to instruct the HDCP receiver to calculate the receiving end authentication key through the first algorithm subcircuit or the second algorithm subcircuit.

Images