Prefetching control method and device, processor and electronic equipment

Abstract

The embodiment of the invention discloses a prefetching control method and device, a processor and electronic equipment, relates to the technical field of computers, and can effectively reduce resource consumption while ensuring the running speed of a program. The method comprises the steps that in response to cache miss of a target memory access instruction, whether a target to-be-transmitted instruction exists in a transmitting queue or not is inquired, the target to-be-transmitted instruction comprises at least one source operand, only one source operand is not ready, and the target to-be-transmitted instruction is sent to the transmitting queue; the unready source operands are related to an execution result of the target memory access instruction; and according to a query result, determining whether to instruct a prefetcher to execute a prefetching association operation for the target memory access instruction, wherein the prefetching association operation comprises at least one of the following items: performing data prefetching by using the target memory access instruction, and performing data prefetching training on the prefetcher by using the target memory access instruction. The method and the device can be used for data prefetching.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a pre-fetch control method, device, processor and electronic equipment. Background Art

[0002] Data prefetching technology predicts the data addresses to be used in the future based on the historical patterns of cache (cache memory) accesses, initiates data acquisition requests in advance before the data is needed, and transfers data from memory or higher-level cache (such as L3) to lower-level cache (such as L1). If the prediction is accurate, the Miss Rate (miss rate or miss rate) of the lower-level cache can be effectively reduced.

[0003] However, in some cases, even if the data required for a certain instruction INSTA is pre-fetched, it is still necessary to wait when executing the subsequent instruction INSTB. This is because the execution of instruction INSTB may need to rely on the execution results of instruction INSTA and instruction INSTC. Although pre-fetching data for instruction INSTA can enable instruction INSTA to obtain the execution result as soon as possible, since the execution result of instruction INSTC may be obtained later, the execution of instruction INSTB is not accelerated by pre-fetching data for instruction INSTA. Such situations are very common in program running, but such pre-fetching operations often consume valuable resources (such as increasing power consumption, occupying additional bandwidth, etc.), but cannot effectively improve the execution speed of the program. Summary of the invention

[0004] In view of this, an embodiment of the present invention provides a pre-fetch control method, device, processor and electronic device, which can effectively reduce resource consumption while ensuring the program running speed.

[0005] In the first aspect, an embodiment of the present invention also provides a prefetch control method, comprising: in response to a cache miss of a target memory access instruction, querying whether there is a target to-be-issued instruction in a transmit queue, the target to-be-issued instruction comprising at least one source operand, wherein one and only one of the source operands is not ready, and the unready source operand is related to an execution result of the target memory access instruction; determining whether to instruct a prefetcher to perform a prefetch association operation for the target memory access instruction based on the query result, the prefetch association operation comprising at least one of the following: performing data prefetching using the target memory access instruction, and performing data prefetching training on the prefetcher using the target memory access instruction.

[0006] In one embodiment, in response to a cache miss in a target memory access instruction, querying whether there is a target to-be-issued instruction in the transmit queue includes: in response to a cache miss in a target memory access instruction, obtaining a register identifier of a destination physical register of the target memory access instruction to obtain a first identifier; comparing the register identifiers of the source physical registers of each queue instruction in the transmit queue with the first identifier respectively, and determining the queue instruction corresponding to the register identifier having the same comparison result as a first candidate instruction; and determining, among each of the first candidate instructions, the first candidate instruction having only one source operand that is not ready as the target to-be-issued instruction.

[0007] In one embodiment, in response to a cache miss occurring in a target memory access instruction, querying whether there is a target to-be-issued instruction in the transmit queue includes: in response to a cache miss occurring in a target memory access instruction, obtaining a register identifier of a destination physical register of the target memory access instruction to obtain a first identifier; searching the transmit queue for an instruction having only one source operand that is not ready to obtain a second candidate instruction; comparing the register identifier of the source physical register of each of the second candidate instructions with the first identifier, respectively, and determining the second candidate instruction corresponding to the register identifier having the same comparison result as the target to-be-issued instruction.

[0008] In one embodiment, the target memory access instruction is emitted from the emission queue; each queue instruction in the emission queue carries corresponding additional information, the additional information includes a reorder cache identifier of a dependent instruction of the queue instruction, and a source operand of the queue instruction is related to an execution result of the dependent instruction; in response to a cache miss in the target memory access instruction, querying whether there is a target to-be-emitted instruction in the emission queue includes: in response to a cache miss in the target memory access instruction, comparing the reorder cache identifier of the target memory access instruction with the reorder cache identifier in the additional information of each of the queue instructions in the emission queue, and determining the queue instruction corresponding to the reorder cache identifier with the same comparison result as a third candidate instruction; determining the third candidate instruction with only one source operand that is not ready as the target to-be-emitted instruction.

[0009] In one embodiment, the target memory access instruction is emitted from the emission queue; each queue instruction in the emission queue carries corresponding additional information, the additional information includes a reorder cache identifier of a dependent instruction of the queue instruction, and a source operand of the queue instruction is related to an execution result of the dependent instruction; in response to a cache miss in the target memory access instruction, querying whether there is a target to-be-issued instruction in the emission queue includes: in response to a cache miss in the target memory access instruction, searching the emission queue for an instruction with only one source operand that is not ready to be used, and obtaining a fourth alternative instruction; comparing the reorder cache identifier of the target memory access instruction with the reorder cache identifier in the additional information of each of the fourth alternative instructions, and determining the fourth alternative instruction corresponding to the reorder cache identifier having the same comparison result as the target to-be-issued instruction.

[0010] In one embodiment, determining whether to instruct the prefetcher to perform the prefetch associated operation for the target memory access instruction based on the query result includes: instructing the prefetcher to perform the prefetch associated operation for the target memory access instruction through a memory access unit when the target to-be-issued instruction exists in the transmit queue; or, instructing the prefetcher to perform the prefetch associated operation for the target memory access instruction through the memory access unit when the target to-be-issued instruction does not exist in the transmit queue, or, instructing the prefetcher to not perform the prefetch associated operation through the memory access unit, or, instructing the prefetcher to intercept the prefetch associated operation that has already been issued through the memory access unit.

[0011] In one embodiment, when the target to-be-issued instruction exists in the transmit queue, instructing the prefetcher to perform the prefetch-associated operation for the target memory access instruction through the memory access unit includes: when the target to-be-issued instruction exists in the transmit queue, sending a prefetch valid signal to the memory access unit, so that the memory access unit sends a first control signal to the prefetcher according to the prefetch valid signal, and the first control signal carries the memory address where the data to be accessed by the target memory access instruction is located.

[0012] In one implementation, the first control signal also carries the memory address where the target memory access instruction itself is located.

[0013] In one embodiment, the use of the target memory access instruction to prefetch data includes: predicting the memory address of future required data based on the memory address where a cache miss occurs for the target memory access instruction and historical memory access statistics of the target memory access instruction to obtain a predicted address; and prefetching the future required data based on the predicted address.

[0014] In one embodiment, the data prefetching training of the prefetcher using the target memory access instruction includes: using the memory address of the target memory access instruction where a cache miss occurs, to construct or update historical memory access statistics information so that the prefetcher performs address prefetching according to the historical memory access statistics information.

[0015] In one embodiment, determining whether to instruct the prefetcher to perform a prefetch association operation for the target memory access instruction based on the query result includes: determining whether to instruct the prefetcher to perform a prefetch association operation for the target memory access instruction based on the busyness of the processor and / or the busyness of the memory and the query result.

[0016] In a second aspect, an embodiment of the present invention provides a prefetch control device, comprising: a query module, configured to query whether there is a target to-be-issued instruction in a transmit queue in response to a cache miss in a target memory access instruction, the target to-be-issued instruction comprising at least one source operand, wherein one and only one of the source operands is not ready, and the unready source operand is related to an execution result of the target memory access instruction; a determination module, coupled to the query module, configured to determine whether to instruct a prefetcher to perform a prefetch association operation for the target memory access instruction based on the query result, the prefetch association operation comprising at least one of the following: prefetching data using the target memory access instruction, and training the prefetcher for data prefetching using the target memory access instruction.

[0017] In one embodiment, the query module is configured to: in response to a cache miss in a target memory access instruction, obtain the register identifier of the destination physical register of the target memory access instruction to obtain a first identifier; compare the register identifiers of the source physical registers of each queue instruction in the transmission queue with the first identifier respectively, and determine the queue instruction corresponding to the register identifier with the same comparison result as the first candidate instruction; and determine the first candidate instruction among each of the first candidate instructions that has only one source operand that is not ready as the target instruction to be transmitted.

[0018] In one embodiment, the query module is configured to: in response to a cache miss in a target memory access instruction, obtain the register identifier of the destination physical register of the target memory access instruction to obtain a first identifier; search the emission queue for an instruction with only one source operand that is not ready to obtain a second candidate instruction; compare the register identifier of the source physical register of each of the second candidate instructions with the first identifier, respectively, and determine the second candidate instruction corresponding to the register identifier with the same comparison result as the target instruction to be emitted.

[0019] In one embodiment, the target memory access instruction is emitted from the emission queue; each queue instruction in the emission queue carries corresponding additional information, and the additional information includes a reorder cache identifier of a dependent instruction of the queue instruction, and a source operand of the queue instruction is related to an execution result of the dependent instruction; the query module is configured to: in response to a cache miss in the target memory access instruction, compare the reorder cache identifier of the target memory access instruction with the reorder cache identifier in the additional information of each queue instruction in the emission queue, and determine the queue instruction corresponding to the reorder cache identifier with the same comparison result as a third candidate instruction; and determine the third candidate instruction with only one source operand that is not ready as the target instruction to be emitted.

[0020] In one embodiment, the target memory access instruction is emitted from the emission queue; each queue instruction in the emission queue carries corresponding additional information, and the additional information includes a reorder cache identifier (RID, ROB Identification) of a dependent instruction ROB (Re-Order Buffer) of the queue instruction, and a source operand of the queue instruction is related to an execution result of the dependent instruction; the query module is configured to: in response to a cache miss in the target memory access instruction, search the emission queue for an instruction with only one source operand that is not ready to obtain a fourth candidate instruction; compare the reorder cache identifier of the target memory access instruction with the reorder cache identifier in the additional information of each of the fourth candidate instructions, and determine the fourth candidate instruction corresponding to the reorder cache identifier with the same comparison result as the target instruction to be emitted.

[0021] In one embodiment, the determination module includes: a first indication submodule, configured to instruct the prefetcher to perform the prefetch associated operation for the target memory access instruction through a memory access unit when the target to-be-issued instruction exists in the transmit queue; or, a second indication submodule, configured to refuse to instruct the prefetcher to perform the prefetch associated operation for the target memory access instruction through the memory access unit when the target to-be-issued instruction does not exist in the transmit queue, or to instruct the prefetcher not to perform the prefetch associated operation through the memory access unit, or to instruct the prefetcher to intercept the prefetch associated operation that has been issued through the memory access unit.

[0022] In one embodiment, the first indication submodule is configured to send a prefetch enable signal to the memory access unit when the target to-be-issued instruction exists in the transmit queue, so that the memory access unit sends a first control signal to the prefetcher according to the prefetch enable signal, and the first control signal carries the memory address where the data to be accessed by the target memory access instruction is located.

[0023] In one implementation, the first control signal also carries the memory address where the target memory access instruction itself is located.

[0024] In one embodiment, the prefetcher is configured to: predict the memory address of future required data based on the memory address where a cache miss occurs for the target memory access instruction and historical memory access statistics of the target memory access instruction to obtain a predicted address; and prefetch the future required data based on the predicted address.

[0025] In one embodiment, the prefetcher is configured to: construct or update historical memory access statistics information using the memory address of the target memory access instruction where a cache miss occurs, so as to perform address prefetching according to the historical memory access statistics information.

[0026] In one embodiment, the determination module is configured to determine whether to instruct the prefetcher to perform a prefetch association operation for the target memory access instruction according to the busyness of the processor and / or the busyness of the memory and the query result.

[0027] In the third aspect, an embodiment of the present invention further provides a processor, comprising: a transmit queue, a memory access unit, a prefetcher and any one of the prefetch control devices provided by the embodiments of the present invention; the transmit queue, the prefetch control device, the memory access unit and the prefetcher are connected in series in sequence; the prefetch control device is configured to obtain information from the memory access unit that a cache miss occurs in the target memory access instruction, and to instruct the prefetcher to perform a prefetch association operation for the target memory access instruction through the memory access unit.

[0028] In a fourth aspect, an embodiment of the present invention further provides an electronic device, comprising a circuit board, a processor and a memory, wherein the processor and the memory are respectively arranged on the circuit board, and the processor is electrically connected to the memory for performing a read operation or a write operation on the memory, wherein the processor is any one of the processors provided in the embodiments of the present invention.

[0029] The prefetch control method, device, processor and electronic device provided by the embodiments of the present invention can query whether there is a target to-be-issued instruction in the transmission queue in response to a cache miss of the target memory access instruction, and determine whether to instruct the prefetcher to perform a prefetch association operation for the target memory access instruction based on the query result, and the prefetch association operation includes at least one of the following: using the target memory access instruction to prefetch data, and using the target memory access instruction to perform data prefetch training on the prefetcher. Since the target to-be-issued instruction includes at least one source operand, one and only one of the source operands is not ready, and the unready source operand is related to the execution result of the target memory access instruction, therefore, by querying whether there is a target to-be-issued instruction in the transmission queue, it is possible to determine whether the execution of the prefetch association operation on the target memory access instruction and the execution result obtained will trigger the execution of subsequent instructions more quickly, thereby speeding up the running speed of the program. That is to say, compared with the scheme in the prior art that performs prefetch-related operations on the target memory access instruction as long as a cache miss occurs, the scheme of the embodiment of the present invention can filter the prefetch-related operations to a certain extent, and only execute prefetch-related operations that are helpful in speeding up the program running speed, and temporarily not execute prefetch-related operations that cannot speed up the program running speed. Therefore, it can effectively reduce resource consumption while ensuring the program running speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0031] Figure 1 A flow chart of a pre-fetch control method provided by an embodiment of the present invention; Figure 2 A schematic diagram of a structure of a transmission queue in an embodiment of the present invention; Figure 3 A schematic diagram of historical memory access statistical information in an embodiment of the present invention; Figure 4 Another flow chart of the pre-fetch control method provided by the embodiment of the present invention; Figure 5 A schematic diagram of the structure of a pre-fetch control device provided by an embodiment of the present invention; Figure 6 Another structural schematic diagram of a pre-fetch control device provided by an embodiment of the present invention; Figure 7 A schematic diagram of the structure of a processor provided by an embodiment of the present invention; Figure 8 A schematic diagram of internal signal transmission and control in a processor provided by an embodiment of the present invention; Fig. 9 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0033] It should be clear that the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] To facilitate understanding, some professional terms involved in the embodiments of the present invention are briefly introduced first.

[0035] Issue Queue (IQ): used to store instructions that have been renamed by registers but have not been sent to FU (function unit) for execution. It is also commonly called RS (Reservation Station). The issue queue can select instructions whose source operands are ready according to certain rules and send them to FU for execution. This process is called issue.

[0036] Prefetcher: a component that performs data prefetching operations, which can be implemented by software or hardware. Unless otherwise specified, the prefetcher in the embodiments of the present invention generally refers to a prefetcher implemented based on hardware.

[0037] Hardware data prefetching: The hardware predicts the data addresses to be used in the future based on historical memory access information, initiates data acquisition requests in advance before the data is needed, and transfers data from memory or a higher-level cache (such as L3) to a lower-level cache (such as L1).

[0038] Load / store unit (LSU): The component responsible for processing the reading and writing operations of instructions and data.

[0039] Cache memory (cache): Cache is a small-capacity, high-speed memory located between the CPU and main memory. Its main function is to make up for the speed difference between the CPU and memory (such as main memory), thereby improving the overall performance of the system. Cache can have multiple levels, such as L1 Cache, L2 Cache, and L3 Cache. The lower the level of cache, the faster the access speed. For example, the fastest access speed of L1 Cache is 4 to 5 clock cycles, L2 Cache is 8 to 15 clock cycles, and L3 Cache is 30 to 50 clock cycles. Accessing the memory will take more clock cycles.

[0040] The technical solutions provided by the embodiments of the present invention are described in detail below.

[0041] In a first aspect, an embodiment of the present invention provides a pre-fetch control method, which can effectively reduce resource consumption while ensuring the program running speed.

[0042] like Figure 1 As shown, the pre-fetch control method provided by the embodiment of the present invention may include: S31, in response to a cache miss of a target memory access instruction, querying whether there is a target to-be-issued instruction in the issue queue, the target to-be-issued instruction including at least one source operand, wherein one and only one of the source operands is not ready, and the unready source operand is related to an execution result of the target memory access instruction; S32. Determine whether to instruct the prefetcher to perform a prefetch associated operation for the target memory access instruction according to the query result, wherein the prefetch associated operation includes at least one of the following: performing data prefetch using the target memory access instruction, and performing data prefetch training on the prefetcher using the target memory access instruction.

[0043] The prefetch control method provided by the embodiment of the present invention can query whether there is a target to-be-issued instruction in the emission queue in response to a cache miss of the target memory access instruction, and determine whether to instruct the prefetcher to perform a prefetch association operation for the target memory access instruction based on the query result, and the prefetch association operation includes at least one of the following: using the target memory access instruction to prefetch data, and using the target memory access instruction to perform data prefetch training on the prefetcher. Since the target to-be-issued instruction includes at least one source operand, one and only one of the source operands is not ready, and the unready source operand is related to the execution result of the target memory access instruction, therefore, by querying whether there is a target to-be-issued instruction in the emission queue, it is possible to determine whether the execution of the subsequent instructions will be triggered more quickly after the prefetch association operation is performed on the target memory access instruction and the execution result is obtained, thereby speeding up the running speed of the program. That is to say, compared with the scheme in the prior art that performs prefetch associated operations on the target memory access instruction as long as a cache miss occurs, the prefetch control method provided by the embodiment of the present invention can filter the prefetch associated operations to a certain extent, and only execute prefetch associated operations that are helpful in speeding up the program running speed, and temporarily not execute prefetch associated operations that cannot speed up the program running speed. Therefore, it can effectively reduce resource consumption while ensuring the program running speed.

[0044] It should be noted that in the embodiment of the present invention, for some queue instructions in the emission queue, there may be a situation where two or more source operands of a queue instruction are not ready, and these unready source operands depend on different target memory access instructions. In this case, the corresponding prefetch association operation may not be performed on each target memory access instruction. As the program runs, one or more source operands will eventually be ready, and only one source operand will be unready. At this time, the queue instruction becomes the above-mentioned target instruction to be emitted.

[0045] It should also be noted that, depending on the design of the processor, some processors can execute one memory access instruction in each clock cycle, and some processors can execute multiple memory access instructions in parallel in each clock cycle. The embodiment of the present invention is described by taking the case of executing one memory access instruction in each clock cycle as an example. For the case of executing multiple memory access instructions in parallel in each clock cycle, the execution of each memory access instruction can be performed with reference to the case of executing one memory access instruction in each clock cycle.

[0046] Specifically, the processor can store instructions or data into the memory, or read instructions or data from the memory through the memory access unit. The memory access involved in the embodiments of the present invention specifically refers to storing data into the memory or reading data from the memory. In the embodiments of the present invention, there is a preset correspondence between the cache line and the memory address, then a cache miss occurs in the target memory access instruction, which specifically refers to that when the memory access unit reads the source operand of the target memory access instruction from a certain level of cache according to the memory address where the source operand of the target memory access instruction is located, the source operand is not in the cache of that level, and accordingly, the memory address where the source operand is located is the memory address where the cache miss occurs.

[0047] In this regard, in one embodiment of the present invention, in response to a cache miss in a target memory access instruction, step S31 may include querying whether there is a target to-be-issued instruction in the emission queue: in response to a cache miss in a target memory access instruction, obtaining a register identifier of a destination physical register of the target memory access instruction to obtain a first identifier; comparing the register identifiers of source physical registers of each queue instruction in the emission queue with the first identifier, respectively, and determining the queue instruction corresponding to the register identifier with the same comparison result as the first candidate instruction; determining the first candidate instruction with only one source operand that is not ready among each of the first candidate instructions as the target to-be-issued instruction. Among them, the register identifier of the destination physical register can be used as the destination operand of an instruction, and the register identifier of the source physical register can be used as the source operand of an instruction.

[0048] For example, in one embodiment of the present invention, when a cache miss occurs when executing a target memory access instruction to perform a data read operation, the register identifier of the destination physical register of the target memory access instruction can be obtained, for example, the register identifier is R5, and the first identifier R5 is compared with the register identifier of the source physical register in each queue instruction in the emission queue 12. The destination physical register is used to store the execution result of the target memory access instruction. The register identifier R5 is the first identifier R5.

[0049] Exemplarily, in one example, the emission queue includes three queue instructions A, B, and C, wherein the register identifier of the source physical register of queue instruction A includes R1, the register identifier of the source physical register of queue instruction B includes R2 and R5, and the register identifier of the source physical register of queue instruction C includes R5. After comparison, it can be known that since the register identifiers of the physical registers of queue instruction B and queue instruction C both include R5, which is the same as the first identifier, it can be determined that the first candidate instruction includes queue instruction B and queue instruction C. If both source operands R2 and R5 of queue instruction B are not ready, and only one source operand R5 of queue instruction C is not ready, it can be determined that queue instruction C is the target instruction to be emitted. If the query result is that there is a target emission instruction in the emission queue, the prefetcher can be instructed to perform a prefetch association operation through the memory access unit. Here, the prefetcher and the memory access unit have different logical functions. Therefore, logically, the two are two different logical components, but in physical implementation, the two can be separated from each other or made together, and the embodiments of the present invention are not limited to this.

[0050] In this embodiment, register identification comparison can be performed first to obtain first candidate instructions, and then a first candidate instruction with only one source operand that is not ready is selected from each first candidate instruction to obtain a target instruction to be issued. However, the embodiments of the present invention are not limited thereto, and in other embodiments of the present invention, instructions with only one source operand that is not ready can also be screened out in the issue queue first, and then register identification comparison can be performed.

[0051] Specifically, in one embodiment of the present invention, step S31, in response to a cache miss occurring in a target memory access instruction, queries whether there is a target to-be-issued instruction in the transmit queue, may include: in response to a cache miss occurring in a target memory access instruction, obtaining a register identifier of a destination physical register of the target memory access instruction, and obtaining a first identifier; searching the transmit queue for an instruction having only one source operand that is not ready, and obtaining a second candidate instruction; comparing the register identifier of the source physical register of each of the second candidate instructions with the first identifier, respectively, and determining the second candidate instruction corresponding to the register identifier having the same comparison result as the target to-be-issued instruction.

[0052] For example, in one example, in response to a cache miss in a target memory access instruction, the register identifier R5 of the destination physical register of the target memory access instruction can be obtained to obtain the first identifier R5, and the instruction with only one source operand that is not ready is searched in the emission queue to obtain the second alternative instruction. For example, the emission queue includes three queue instructions A, B, and C, wherein the register identifier of the source physical register of queue instruction A includes R1, the register identifier of the source physical register of queue instruction B includes R2 and R5, and the register identifier of the source physical register of queue instruction C includes R5. If R1, R2, and R5 are all not ready, then queue instruction A and queue instruction C both have only one source operand that is not ready, and queue instruction B has two source operands that are not ready. Therefore, it can be determined that the second alternative instruction includes queue instruction A and queue instruction C. Next, the register identifiers of the source physical registers of queue instruction A and queue instruction C can be compared with the first identifier respectively. Since the register identifier of the source physical register of queue instruction A is R1, the register identifier of the source physical register of queue instruction C is R5, and the first identifier is R5, it can be determined that queue instruction C is the target instruction to be issued.

[0053] It should be noted that, although the target memory access instruction and each queue instruction in the emission queue are described separately in the aforementioned embodiment, it is understandable that the target memory access instruction is also stored in the emission queue before being executed, and is only emitted from the emission queue for execution when it meets the emission condition. Optionally, in an embodiment of the present invention, the processor may include one or more emission queues, and the target memory access instruction may be stored in the same emission queue as the target instruction to be emitted, or may be stored in a different emission queue from the target instruction to be emitted. The embodiment of the present invention does not limit this.

[0054] In the above embodiment, the register identifier of the destination physical register of the target memory access instruction is compared with the register identifier of the source physical register of each queue instruction in the issue queue, but the embodiment of the present invention is not limited thereto. In other embodiments of the present invention, other methods can also be used for comparison.

[0055] Specifically, in one embodiment of the present invention, a target memory access instruction is emitted from an emission queue; each queue instruction in the emission queue carries corresponding additional information, and the additional information includes a reorder cache identifier of a dependent instruction of the queue instruction, and a source operand of the queue instruction is related to an execution result of the dependent instruction; based on this, in response to a cache miss in the target memory access instruction, the reorder cache identifier of the target memory access instruction can be compared with the reorder cache identifier in the additional information of each of the queue instructions in the emission queue, and the queue instruction corresponding to the reorder cache identifier with the same comparison result can be determined as a third candidate instruction; among each of the third candidate instructions, the third candidate instruction with only one source operand that is not ready is determined as the target instruction to be emitted.

[0056] In one embodiment of the present invention, after the instruction is fetched and decoded, in addition to entering the transmit queue, the instruction will also enter the reorder buffer (ROB). Each instruction will have a corresponding reorder buffer identifier in the reorder buffer, and an instruction can be uniquely identified based on the reorder buffer identifier. For example, the reorder buffer identifier corresponding to instruction A1 is sn3, and the reorder buffer identifier corresponding to instruction A2 is sn10, etc. Based on this, the reorder buffer identifier of the target memory access instruction can be compared with the reorder buffer identifier in the additional information of the instructions in each queue in the transmit queue. For example, Figure 2 As shown, in one example, the reorder cache identifier of the target memory access instruction F is sn10, and in the emission queue, the reorder cache identifier in the additional information of the queue instruction D is sn10. Since it can be determined that the reorder cache identifier of the target memory access instruction F is the same as the reorder cache identifier in the additional information of the queue instruction D, both are sn10, it can be determined that the queue instruction D is the third candidate instruction. After the third candidate instruction is determined, the third candidate instruction with only one source operand that is not ready can be determined as the target instruction to be emitted. The basic principle has been explained in the previous text and will not be repeated here.

[0057] In this embodiment, a reorder cache identifier comparison can be performed first to obtain a third candidate instruction, and then a third candidate instruction with only one source operand that is not ready is selected from each third candidate instruction to obtain a target instruction to be issued. However, the embodiments of the present invention are not limited thereto, and in other embodiments of the present invention, instructions with only one source operand that is not ready can also be screened out in the issue queue first, and then a reorder cache identifier comparison can be performed.

[0058] Specifically, in one embodiment of the present invention, a target memory access instruction is emitted from the emission queue; each queue instruction in the emission queue carries corresponding additional information, the additional information including a reorder cache identifier of a dependent instruction of the queue instruction, and a source operand of the queue instruction is related to an execution result of the dependent instruction; based on this, in response to a cache miss in the target memory access instruction, an instruction having only one source operand that is not ready can be searched in the emission queue to obtain a fourth alternative instruction; the reorder cache identifier of the target memory access instruction is compared with the reorder cache identifier in the additional information of each of the fourth alternative instructions, and the fourth alternative instruction corresponding to the reorder cache identifier having the same comparison result is determined as the target instruction to be emitted.

[0059] The above has described step S31 in detail, and the following will describe step S32 in detail.

[0060] In one embodiment of the present invention, step S32 determines whether to instruct the prefetcher to perform a prefetch association operation for the target memory access instruction according to the query result, which may include: In the case where there is a target to-be-issued instruction in the transmit queue, instructing the prefetcher to perform the prefetch association operation for the target memory access instruction through the memory access unit; or, When there is no target instruction to be issued in the emission queue, the prefetcher is refused to be instructed to perform the prefetch associated operation for the target memory access instruction through the memory access unit, or the prefetcher is instructed not to perform the prefetch associated operation through the memory access unit, or the prefetcher is instructed to intercept the prefetch associated operation that has been issued through the memory access unit.

[0061] That is to say, different instruction operations can be performed according to different query results. In one example, if the query result is that there is a target emission instruction in the emission queue, it means that after performing the prefetch association operation on the target memory access instruction, the target memory access instruction can be executed faster and the execution result can be obtained faster, and the execution result can make the unready source operand of the target emission instruction become ready faster, thereby quickly triggering the execution of the target emission instruction. In this way, the execution of the prefetch association operation can effectively improve the execution speed of the program.

[0062] In a specific implementation, when the target to-be-issued instruction exists in the emission queue, a pre-fetch valid signal can be sent to the memory access unit, so that the memory access unit sends a first control signal to the pre-fetcher according to the pre-fetch valid signal, and the first control signal carries the memory address where the data to be accessed by the target memory access instruction (e.g., the source data of the target memory access instruction) is located. Based on this, the pre-fetcher can perform a pre-fetch association operation according to the received first control signal, for example, it can use the target memory access instruction to pre-fetch data, and it can also use the target memory access instruction to perform data pre-fetch training.

[0063] Exemplarily, in one example, using the target memory access instruction to perform data prefetching may include: predicting the memory address of future required data based on the memory address where a cache miss occurs for the target memory access instruction and historical memory access statistics of the target memory access instruction to obtain a predicted address; and prefetching the future required data based on the predicted address.

[0064] Illustratively, in another example, using the target memory access instruction to perform data prefetching may include: using the memory address of the target memory access instruction where a cache miss occurs, to construct or update historical memory access statistics information, so as to perform address prefetching according to the historical memory access statistics information.

[0065] For example, based on the Stream Prefetch algorithm, a historical memory access statistics can be as follows: Figure 3 As shown. Each row represents a piece of historical memory access statistics, where the instruction PC is the address stored in the program counter PC, representing the memory address where the target memory access instruction is located. The start address is the memory address corresponding to the cache line where a cache miss occurs when the target memory access instruction accesses the memory. The number of cache lines is the number of cache lines where cache misses occur consecutively starting from the start address. Confidence is the number of times the scenario corresponding to this piece of historical memory access statistics occurs repeatedly during subsequent program execution. The larger the value, the better the repeatability of the scenario identified by this piece of historical memory access statistics.

[0066] When PC 0x0A is executed and the start address 0X1F502000 is accessed and a cache miss occurs, if the prefetcher is instructed to perform a prefetch association operation (for example, a prefetch operation is performed on the source data required by PC 0x0A), it is considered that the hit sequence number 0 represents the historical memory access statistics. If the confidence exceeds 2 at this time, it is predicted that the scenario that will occur in the future will be consistent with the information saved in sequence number 0, which will trigger data prefetching and start issuing prefetch requests to fetch the data in the 9 cache lines after 0X1F502000 from the memory or a higher-level cache to a lower-level cache in advance.

[0067] In an embodiment of the present invention, the prefetcher can record the memory addresses where cache misses occurred during previous program executions, find out the patterns therefrom, and form historical memory access statistics. In this way, during subsequent program executions, once a cache miss occurs again, and the historical memory access statistics include the memory address where the cache miss occurred, the prefetcher can determine which memory addresses will be accessed after the memory address where the cache miss occurred based on the historical access statistics, and prefetch the data in these memory addresses into a lower-level cache memory.

[0068] Furthermore, in some embodiments, in addition to the memory address where the cache miss occurs, the first control signal may also carry the memory address where the target memory access instruction itself is located, that is, the address stored in the program counter PC. Based on this, the historical memory access statistics maintained by the prefetcher may also include the memory address where the target memory access instruction itself is located, so that the prefetch address can be predicted by two dimensions: the memory address where the target memory access instruction itself is located and the memory address where the cache miss occurs, thereby effectively improving the accuracy of prefetching.

[0069] This embodiment is illustrated by taking stream prefetching as an example, but the embodiments of the present invention are not limited to this. In other embodiments of the present invention, the prefetch control device provided by the embodiments of the present invention can also be applied to prefetchers implemented based on other prefetching algorithms, such as Stride, Region, Address Correlated and other algorithms, and the embodiments of the present invention are not limited to this.

[0070] It should be noted that, in the embodiments of the present invention, the so-called pre-fetching may include transferring data from the memory or any higher-level cache memory to a lower-level cache memory, for example, transferring data from the memory to L3, or transferring data from L3 to L2, or transferring data from the memory to L1, etc.

[0071] Optionally, in another example, if the query result is that the target transmit instruction does not exist in the transmit queue, it means that even if the prefetch association operation is performed on the target memory access instruction, so that the target memory access instruction is executed faster and the execution result is obtained faster, the execution result will not trigger the fast execution of any queue instruction in the transmit queue, which will only waste precious resources. Therefore, the corresponding prefetch association operation can be blocked in a variety of ways, such as refusing to instruct the prefetcher to perform the prefetch association operation on the target memory access instruction, or instructing the prefetcher not to perform the prefetch association operation, or instructing the prefetcher to intercept the prefetch association operation that has been issued, thereby effectively saving resources.

[0072] In the aforementioned embodiment, whether to instruct the prefetcher to perform a prefetch-related operation on the target memory access instruction is determined based on the query result, but the embodiments of the present invention are not limited thereto. In other embodiments of the present invention, it is also possible to determine whether to instruct the prefetcher to perform a prefetch-related operation on the target memory access instruction in combination with the status of other components. For example, in one embodiment of the present invention, it can be configured to determine whether to instruct the prefetcher to perform a prefetch-related operation on the target memory access instruction based on the busyness of the processor and / or the busyness of the memory and the query result.

[0073] Specifically, when the busyness of the processor or memory is relatively low and the query result is that the target instruction to be issued exists, the prefetcher can be instructed to perform a prefetch association operation for the target memory access instruction; when the busyness of the processor or memory is relatively high and the query result is that the target instruction to be issued does not exist, the prefetcher is not instructed to perform a prefetch association operation for the target memory access instruction. When the busyness of the processor or memory is relatively low and the query result is that the target instruction to be issued does not exist, and when the busyness of the processor or memory is relatively high and the query result is that the target instruction to be issued exists, arbitration can be performed according to specific circumstances and needs.

[0074] The pre-fetch control method provided by the embodiment of the present invention is described in detail below through a specific embodiment.

[0075] like Figure 4 As shown, the pre-fetch control method provided by the embodiment of the present invention may include: S401, in response to a cache miss occurring in a target memory access instruction, obtaining a register identifier of a destination physical register of the target memory access instruction to obtain a first identifier; S402, searching the issue queue for an instruction with only one source operand that is not ready, and obtaining a second candidate instruction; S403, comparing the register identifier of the source physical register of each second candidate instruction with the first identifier respectively, and determining the second candidate instruction corresponding to the register identifier having the same comparison result as the target instruction to be issued; S404: Is there a target instruction to be transmitted in the transmission queue? If yes, execute step S405; if no, execute step S406.

[0076] S405 , sending a pre-fetch enable signal to the memory access unit, so that the memory access unit sends a first control signal to the pre-fetcher according to the pre-fetch enable signal, wherein the first control signal carries a memory address where data to be accessed by the target memory access instruction is located.

[0077] S406: Refuse to instruct the prefetcher to perform the prefetch associated operation for the target memory access instruction through the memory access unit, or instruct the prefetcher not to perform the prefetch associated operation through the memory access unit, or instruct the prefetcher to intercept the prefetch associated operation that has been issued through the memory access unit.

[0078] In a second aspect, an embodiment of the present invention provides a pre-fetch control device that can effectively reduce resource consumption while ensuring program running speed.

[0079] like Figure 5 As shown, an embodiment of the present invention provides a pre-fetch control device 1, comprising: A query module 11 is configured to query whether there is a target to-be-issued instruction in the emission queue 12 in response to a cache miss of the target memory access instruction, wherein the target to-be-issued instruction includes at least one source operand, wherein one and only one of the source operands is not ready, and the unready source operand is related to the execution result of the target memory access instruction; The determination module 13 is coupled to the query module 11 and is configured to determine whether to instruct a prefetcher (not shown) to perform a prefetch association operation for the target memory access instruction based on the query result, and the prefetch association operation includes at least one of the following: performing data prefetching using the target memory access instruction and performing data prefetching training on the prefetcher using the target memory access instruction.

[0080] The prefetch control device 1 provided by the embodiment of the present invention includes a query module 11 and a determination module 13, wherein the query module 11 is configured to query whether there is a target to-be-issued instruction in the emission queue 12 in response to a cache miss of the target memory access instruction; the determination module 13 is coupled to the query module 11 and is configured to determine whether to instruct the prefetcher to perform a prefetch association operation for the target memory access instruction according to the query result, and the prefetch association operation includes at least one of the following: using the target memory access instruction to prefetch data, and using the target memory access instruction to perform data prefetch training on the prefetcher. Since the target to-be-issued instruction includes at least one source operand, one and only one of the source operands is not ready, and the unready source operand is related to the execution result of the target memory access instruction, therefore, by querying whether there is a target to-be-issued instruction in the emission queue, it is possible to determine whether the execution of the subsequent instructions will be triggered faster after the prefetch association operation is performed on the target memory access instruction and the execution result is obtained, thereby accelerating the running speed of the program. That is to say, compared with the scheme in the prior art that performs prefetch associated operations on the target memory access instruction as long as a cache miss occurs, the prefetch control device 1 provided in the embodiment of the present invention can filter the prefetch associated operations to a certain extent, and only executes prefetch associated operations that are helpful in speeding up the program running speed, and temporarily does not execute prefetch associated operations that cannot speed up the program running speed. Therefore, it can effectively reduce resource consumption while ensuring the program running speed.

[0081] It should be noted that in the embodiment of the present invention, for some queue instructions in the emission queue, there may be a situation where two or more source operands of a queue instruction are not ready, and these unready source operands depend on different target memory access instructions. In this case, the corresponding prefetch association operation may not be performed on each target memory access instruction. As the program runs, one or more source operands will eventually be ready, and only one source operand will be unready. At this time, the queue instruction becomes the above-mentioned target instruction to be emitted.

[0082] It should also be noted that, depending on the design of the processor, some processors can execute one memory access instruction in each clock cycle, and some processors can execute multiple memory access instructions in parallel in each clock cycle. The embodiment of the present invention is described by taking the case of executing one memory access instruction in each clock cycle as an example. For the case of executing multiple memory access instructions in parallel in each clock cycle, the execution of each memory access instruction can be performed with reference to the case of executing one memory access instruction in each clock cycle.

[0083] Specifically, the processor can store instructions or data into the memory, or read instructions or data from the memory through the memory access unit. The memory access involved in the embodiments of the present invention specifically refers to storing data into the memory or reading data from the memory. In the embodiments of the present invention, there is a preset correspondence between the cache line and the memory address, then a cache miss occurs in the target memory access instruction, which specifically refers to that when the memory access unit reads the source operand of the target memory access instruction from a certain level of cache according to the memory address where the source operand of the target memory access instruction is located, the source operand is not in the cache of that level, and accordingly, the memory address where the source operand is located is the memory address where the cache miss occurs.

[0084] In this regard, in one embodiment of the present invention, the query module 11 can be configured as follows: in response to a cache miss in a target memory access instruction, obtain the register identifier of the destination physical register of the target memory access instruction to obtain a first identifier; compare the register identifiers of the source physical registers of each queue instruction in the emission queue with the first identifier respectively, and determine the queue instruction corresponding to the register identifier with the same comparison result as the first candidate instruction; and determine the first candidate instruction with only one source operand that is not ready among each of the first candidate instructions as the target instruction to be emitted. Among them, the register identifier of the destination physical register can be used as the destination operand of an instruction, and the register identifier of the source physical register can be used as the source operand of an instruction.

[0085] For example, Figure 6 As shown, in one embodiment of the present invention, when a cache miss occurs when the memory access unit 15 executes a target memory access instruction to perform a data read operation, the memory access unit 15 may send a register identifier of the destination physical register of the target memory access instruction to the query module 11, for example, the register identifier is R5. The destination physical register is used to store the execution result of the target memory access instruction. The query module 11 may obtain the register identifier R5, i.e., the first identifier R5, and compare the first identifier R5 with the register identifiers of the source physical registers in each queue instruction in the emission queue 12.

[0086] Exemplarily, in one example, the emission queue 12 includes three queue instructions A, B, and C, wherein the register identifier of the source physical register of the queue instruction A includes R1, the register identifier of the source physical register of the queue instruction B includes R2 and R5, and the register identifier of the source physical register of the queue instruction C includes R5. After comparison, it can be known that since the register identifiers of the physical registers of the queue instructions B and C both include R5, which is the same as the first identifier, it can be determined that the first candidate instruction includes the queue instruction B and the queue instruction C. If both source operands R2 and R5 of the queue instruction B are not ready, and only one source operand R5 of the queue instruction C is not ready, it can be determined that the queue instruction C is the target instruction to be emitted. If the query result of the query module 11 is that there is a target emission instruction in the emission queue 12, the determination module 13 can instruct the prefetcher 14 to perform a prefetch association operation through the memory access unit 15. Here, the prefetcher 14 and the memory access unit 15 have different logical functions. Therefore, logically, the two are two different logical components. However, in physical implementation, the two can be separated from each other or made together, and the embodiments of the present invention do not limit this.

[0087] In this embodiment, the query module 11 may first perform a register identification comparison to obtain a first candidate instruction, and then select a first candidate instruction with only one source operand that is not ready from each first candidate instruction to obtain a target instruction to be issued. However, the embodiments of the present invention are not limited thereto. In other embodiments of the present invention, instructions with only one source operand that is not ready may be first screened out from the issue queue 12, and then a register identification comparison may be performed.

[0088] Specifically, in one embodiment of the present invention, the query module 11 can be configured to: in response to a cache miss in a target memory access instruction, obtain the register identifier of the destination physical register of the target memory access instruction to obtain a first identifier; search the emission queue for an instruction with only one source operand that is not ready to obtain a second candidate instruction; compare the register identifier of the source physical register of each of the second candidate instructions with the first identifier, respectively, and determine the second candidate instruction corresponding to the register identifier with the same comparison result as the target instruction to be emitted.

[0089] For example, in one example, in response to a cache miss in the target memory access instruction, the query module 11 can obtain the register identifier R5 of the destination physical register of the target memory access instruction, obtain the first identifier R5, search the emission queue 12 for an instruction with only one source operand that is not ready, and obtain the second alternative instruction. For example, the emission queue 12 includes three queue instructions A, B, and C, wherein the register identifier of the source physical register of queue instruction A includes R1, the register identifier of the source physical register of queue instruction B includes R2 and R5, and the register identifier of the source physical register of queue instruction C includes R5. If R1, R2, and R5 are all not ready, then queue instruction A and queue instruction C both have only one source operand that is not ready, and queue instruction B has two source operands that are not ready. Therefore, it can be determined that the second alternative instruction includes queue instruction A and queue instruction C. Next, the register identifiers of the source physical registers of queue instruction A and queue instruction C can be compared with the first identifier respectively. Since the register identifier of the source physical register of queue instruction A is R1, the register identifier of the source physical register of queue instruction C is R5, and the first identifier is R5, it can be determined that queue instruction C is the target instruction to be issued.

[0090] It should be noted that, although the target memory access instruction and each queue instruction in the emission queue 12 are described separately in the aforementioned embodiment, it can be understood that the target memory access instruction is also stored in the emission queue before being executed, and is only emitted from the emission queue 12 for execution when it meets the emission condition. Optionally, in an embodiment of the present invention, the processor may include one or more emission queues 12, and the target memory access instruction may be stored in the same emission queue 12 as the target instruction to be emitted, or may be stored in a different emission queue 12 from the target instruction to be emitted. The embodiment of the present invention does not limit this.

[0091] In the above embodiment, the register identifier of the destination physical register of the target memory access instruction is compared with the register identifier of the source physical register of each queue instruction in the issue queue, but the embodiment of the present invention is not limited thereto. In other embodiments of the present invention, other methods can also be used for comparison.

[0092] Specifically, in one embodiment of the present invention, the target memory access instruction is emitted from the emission queue 12; each queue instruction in the emission queue 12 carries corresponding additional information, and the additional information includes dependent instructions of the queue instruction, and the source operand of the queue instruction is related to the execution result of the dependent instruction; based on this, the query module 11 can be configured as follows: in response to a cache miss in the target memory access instruction, the reorder cache identifier of the target memory access instruction is compared with the reorder cache identifier in the additional information of each of the queue instructions in the emission queue, and the queue instruction corresponding to the reorder cache identifier with the same comparison result is determined as the third candidate instruction; among each of the third candidate instructions, the third candidate instruction with only one source operand that is not ready is determined as the target instruction to be emitted.

[0093] In one embodiment of the present invention, after the instruction is fetched and decoded, in addition to entering the emission queue 12, the instruction will also enter the reorder cache. Each instruction will have a corresponding reorder cache identifier in the reorder cache, and an instruction can be uniquely identified based on the reorder cache identifier. For example, the reorder cache identifier corresponding to instruction A1 is sn3, and the reorder cache identifier corresponding to instruction A2 is sn10, etc. Based on this, the query module 11 can compare the reorder cache identifier of the target memory access instruction with the reorder cache identifier in the additional information of each queue instruction in the emission queue 12. For example, in one example, the reorder cache identifier of the target memory access instruction F is sn10, and in the emission queue 12, the reorder cache identifier in the additional information of the queue instruction D is sn10. Since it can be determined that the reorder cache identifier of the target memory access instruction F is the same as the reorder cache identifier in the additional information of the queue instruction D, both of which are sn10, it can be determined that the queue instruction D is the third candidate instruction. After the third candidate instruction is determined, the third candidate instruction with only one unready source operand can be determined as the target instruction to be issued. The basic principle has been explained in the previous text and will not be repeated here.

[0094] In this embodiment, the query module 11 may first perform a reorder cache identifier comparison to obtain a third candidate instruction, and then select a third candidate instruction with only one source operand that is not ready from each third candidate instruction to obtain a target instruction to be issued. However, the embodiments of the present invention are not limited thereto. In other embodiments of the present invention, instructions with only one source operand that is not ready may be first screened out in the issue queue 12, and then a reorder cache identifier comparison may be performed.

[0095] Specifically, in one embodiment of the present invention, the target memory access instruction is emitted from the emission queue; each queue instruction in the emission queue carries corresponding additional information, and the additional information includes a reorder cache identifier of a dependent instruction of the queue instruction, and a source operand of the queue instruction is related to the execution result of the dependent instruction; based on this, the query module 11 can be configured to: in response to a cache miss in the target memory access instruction, search the emission queue for an instruction with only one source operand that is not ready to obtain a fourth alternative instruction; compare the reorder cache identifier of the target memory access instruction with the reorder cache identifier in the additional information of each of the fourth alternative instructions, and determine the fourth alternative instruction corresponding to the reorder cache identifier with the same comparison result as the target instruction to be emitted.

[0096] The query module 11 is described in detail above, and the determination module 13 is described in detail below.

[0097] In one embodiment of the present invention, the determination module 13 may include: A first indication submodule is configured to, when there is a target to-be-issued instruction in the emission queue 12, indicate the prefetcher 14 to perform the prefetch association operation for the target memory access instruction through the memory access unit 15; or, The second indication submodule is configured to refuse to instruct the prefetcher 14 to perform the prefetch associated operation for the target memory access instruction through the memory access unit 15 when there is no target to-be-issued instruction in the emission queue 12, or to instruct the prefetcher 14 not to perform the prefetch associated operation through the memory access unit 15, or to instruct the prefetcher 14 to intercept the prefetch associated operation that has been issued through the memory access unit 15.

[0098] That is to say, the determination module 13 can perform different operations according to the query results of the query module 11. In one example, if the query result is that there is a target issue instruction in the issue queue 12, it means that after performing the prefetch association operation on the target memory access instruction, the target memory access instruction can be executed faster and the execution result can be obtained faster, and the execution result can make the unready source operand of the target issue instruction become ready faster, thereby quickly triggering the execution of the target issue instruction. In this way, the execution of the prefetch association operation can effectively improve the execution speed of the program.

[0099] In a specific implementation, the first indication submodule can be configured to send a pre-fetch valid signal to the memory access unit 15 when the target to-be-issued instruction exists in the emission queue 12, so that the memory access unit 15 sends a first control signal to the pre-fetcher 14 according to the pre-fetch valid signal, and the first control signal carries the memory address where the data to be accessed by the target memory access instruction (e.g., the source data of the target memory access instruction) is located. Based on this, the pre-fetcher 14 can perform a pre-fetch association operation according to the received first control signal, for example, it can use the target memory access instruction to pre-fetch data, and it can also use the target memory access instruction to perform data pre-fetch training.

[0100] Exemplarily, in one example, the prefetcher 14 can be configured to: predict the memory address of future required data based on the memory address where a cache miss occurs for the target memory access instruction and historical memory access statistics of the target memory access instruction to obtain a predicted address; and prefetch the future required data based on the predicted address.

[0101] Illustratively, in another example, the prefetcher 14 may also be configured to: construct or update historical memory access statistics information using the memory address where a cache miss occurs for the target memory access instruction, so as to perform address prefetching according to the historical memory access statistics information.

[0102] Furthermore, in some embodiments, in addition to the memory address where the cache miss occurs, the first control signal may also carry the memory address where the target memory access instruction itself is located, that is, the address stored in the program counter PC. Based on this, the historical memory access statistics maintained by the prefetcher 14 may also include the memory address where the target memory access instruction itself is located, so that the prefetch address can be predicted by two dimensions: the memory address where the target memory access instruction itself is located and the memory address where the cache miss occurs, thereby effectively improving the accuracy of prefetching.

[0103] This embodiment is illustrated by taking stream prefetching as an example, but the embodiments of the present invention are not limited to this. In other embodiments of the present invention, the prefetch control device provided by the embodiments of the present invention can also be applied to prefetchers implemented based on other prefetching algorithms, such as Stride, Region, Address Correlated and other algorithms, and the embodiments of the present invention are not limited to this.

[0104] It should be noted that, in the embodiments of the present invention, the so-called pre-fetching may include transferring data from the memory or any higher-level cache memory to a lower-level cache memory, for example, transferring data from the memory to L3, or transferring data from L3 to L2, or transferring data from the memory to L1, etc.

[0105] Optionally, in another example, if the query result is that the target transmit instruction does not exist in the transmit queue 12, it means that even if the prefetch association operation is performed on the target memory access instruction, so that the target memory access instruction is executed faster and the execution result is obtained faster, the execution result will not trigger the fast execution of any queue instruction in the transmit queue 12, which will only waste precious resources. Therefore, the corresponding prefetch association operation can be blocked in a variety of ways, such as refusing to instruct the prefetcher 14 to perform the prefetch association operation on the target memory access instruction, or instructing the prefetcher 14 not to perform the prefetch association operation, or instructing the prefetcher 14 to intercept the prefetch association operation that has been issued, thereby effectively saving resources.

[0106] In the aforementioned embodiment, the determination module 13 determines whether to instruct the prefetcher to perform a prefetch association operation on the target memory access instruction based on the query result of the query module 11, but the embodiments of the present invention are not limited to this. In other embodiments of the present invention, it is also possible to determine whether to instruct the prefetcher to perform a prefetch association operation on the target memory access instruction in combination with the status of other components. For example, in one embodiment of the present invention, the determination module 13 can be configured to determine whether to instruct the prefetcher to perform a prefetch association operation on the target memory access instruction based on the busyness of the processor and / or the busyness of the memory and the query result.

[0107] Specifically, when the busyness of the processor or memory is relatively low and the query result is that the target instruction to be issued exists, the prefetcher can be instructed to perform a prefetch association operation for the target memory access instruction; when the busyness of the processor or memory is relatively high and the query result is that the target instruction to be issued does not exist, the prefetcher is not instructed to perform a prefetch association operation for the target memory access instruction. When the busyness of the processor or memory is relatively low and the query result is that the target instruction to be issued does not exist, and when the busyness of the processor or memory is relatively high and the query result is that the target instruction to be issued exists, arbitration can be performed according to specific circumstances and needs.

[0108] Thirdly, Figure 7 As shown, an embodiment of the present invention further provides a processor 5, the processor comprising: a transmission queue 12, a memory access unit 15, a prefetcher 14 and any one of the prefetch control devices 1 provided in the above embodiments; The transmission queue 12, the prefetch control device 1, the memory access unit 15 and the prefetcher 14 are connected in series in sequence; The prefetch control device 1 is configured to learn that a cache miss occurs in a target memory access instruction through the memory access unit 15 , and instruct the prefetcher 14 to perform a prefetch association operation for the target memory access instruction through the memory access unit 15 .

[0109] Since the processor provided in the embodiments of the present invention includes any one of the prefetch control devices 1 provided in the aforementioned embodiments, corresponding beneficial technical effects can also be achieved, which have been described in detail above and will not be repeated here.

[0110] Exemplarily, in an embodiment of the present invention, the signal transmission relationship between the components inside the processor and the schematic diagram of the prefetch control method performed by the prefetch control device can be as follows: Figure 8 See Figure 8 ,lie in Figure 8 The four boxes on the left represent the four hardware components in the processor, and the arrows therein represent the signal transmission between the components. The serial numbers 1, 2, 3, and 4 represent the order of signal transmission. Specifically, after a cache miss occurs in the memory access unit, the register identifier of the destination physical register of the target memory access instruction can be sent to the prefetch control device (i.e., the signal transmission represented by serial number 1). Then, the prefetch control device can receive the register identifier of the source physical register of each queue instruction sent by the transmit queue (IQ) (i.e., the signal transmission represented by serial number 2), and execute Figure 8 The control flow shown in the right half. In this control flow, the prefetch control device can assign a value (such as true or false) to the prefetch valid signal Valid, and send the assigned Valid to the memory access unit (i.e., the signal transmission represented by sequence number 3). If Valid is true, a first control signal can be sent to the prefetcher, and the first control signal carries the memory address where the cache miss occurs, so that the prefetcher performs the corresponding prefetch associated operation. If Valid is false, the memory access unit does not need to send the first control signal to the prefetcher.

[0111] Fourthly, Fig. 9 As shown, an embodiment of the present invention further provides an electronic device 6, which includes a circuit board 61, a processor 62 and a memory 63. The processor 62 and the memory 63 are respectively arranged on the circuit board 61, and the processor 62 is electrically connected to the memory 63 for performing a read operation or a write operation on the memory 63. The processor 62 is any processor provided in the aforementioned embodiments, and therefore can also achieve corresponding beneficial technical effects, which have been described in detail above and will not be repeated here.

[0112] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0113] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0114] In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0115] For the convenience of description, the above device is described by dividing the functions into various units / modules. Of course, when implementing the present invention, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.

[0116] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0117] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A pre-fetch control method, characterized in that: include: In response to a cache miss of a target memory access instruction, querying whether there is a target to-be-issued instruction in an issue queue, the target to-be-issued instruction including at least one source operand, wherein one and only one of the source operands is not ready, and the unready source operand is related to an execution result of the target memory access instruction; Determine whether to instruct the prefetcher to perform a prefetch association operation for the target memory access instruction according to the query result, wherein the prefetch association operation includes at least one of the following: prefetching data using the target memory access instruction, and training the prefetcher for data prefetching using the target memory access instruction.

2. The method according to claim 1, characterized in that In response to a cache miss of the target memory access instruction, querying whether there is a target to-be-issued instruction in the transmit queue comprises: In response to a cache miss occurring in a target memory access instruction, acquiring a register identifier of a destination physical register of the target memory access instruction to obtain a first identifier; Compare the register identifiers of the source physical registers of each queue instruction in the transmit queue with the first identifier respectively, and determine the queue instructions corresponding to the register identifiers having the same comparison results as the first candidate instructions; Among the first candidate instructions, only one first candidate instruction with an unready source operand is determined as the target to-be-issued instruction.

3. The method according to claim 1, characterized in that In response to a cache miss of the target memory access instruction, querying whether there is a target to-be-issued instruction in the transmit queue comprises: In response to a cache miss occurring in a target memory access instruction, acquiring a register identifier of a destination physical register of the target memory access instruction to obtain a first identifier; Searching the issue queue for an instruction with only one source operand that is not ready to be executed, and obtaining a second candidate instruction; The register identifiers of the source physical registers of each of the second candidate instructions are compared with the first identifiers respectively, and the second candidate instructions corresponding to the register identifiers having the same comparison results are determined as the target instructions to be issued.

4. The method according to claim 1, characterized in that: The target memory access instruction is emitted from the emission queue; Each queue instruction in the transmit queue carries corresponding additional information, wherein the additional information includes a reorder cache identifier of a dependent instruction of the queue instruction, and a source operand of the queue instruction is related to an execution result of the dependent instruction; In response to a cache miss of the target memory access instruction, querying whether there is a target to-be-issued instruction in the transmit queue comprises: In response to a cache miss of a target memory access instruction, a reorder cache identifier of the target memory access instruction is compared with a reorder cache identifier in the additional information of each queue instruction in the transmit queue, and a queue instruction corresponding to a reorder cache identifier having the same comparison result is determined as a third candidate instruction; Among the third candidate instructions, only one third candidate instruction with an unready source operand is determined as the target to-be-issued instruction.

5. The method according to claim 1, characterized in that The target memory access instruction is emitted from the emission queue; Each queue instruction in the transmit queue carries corresponding additional information, wherein the additional information includes a reorder cache identifier of a dependent instruction of the queue instruction, and a source operand of the queue instruction is related to an execution result of the dependent instruction; In response to a cache miss of the target memory access instruction, querying whether there is a target to-be-issued instruction in the transmit queue comprises: In response to a cache miss of the target memory access instruction, searching the issue queue for an instruction with only one source operand that is not ready to be used, to obtain a fourth candidate instruction; The reorder cache identifier of the target memory access instruction is compared with the reorder cache identifier in the additional information of each of the fourth candidate instructions, and the fourth candidate instruction corresponding to the reorder cache identifier having the same comparison result is determined as the target instruction to be issued.

6. The method according to any one of claims 1 to 5, characterized in that: The determining, according to the query result, whether to instruct the prefetcher to perform a prefetch association operation for the target memory access instruction comprises: In a case where the target to-be-issued instruction exists in the transmit queue, instructing the prefetcher to perform the prefetch association operation for the target memory access instruction through a memory access unit; or, In the case that the target to-be-issued instruction does not exist in the transmit queue, the prefetcher is refused to be instructed through the memory access unit to perform the prefetch associated operation for the target memory access instruction, or the prefetcher is instructed through the memory access unit not to perform the prefetch associated operation, or the prefetcher is instructed through the memory access unit to intercept the prefetch associated operation that has been issued.

7. The method according to claim 6, characterized in that In the case where the target to-be-issued instruction exists in the transmit queue, instructing the prefetcher to perform the prefetch association operation for the target memory access instruction through the memory access unit includes: When the target instruction to be issued exists in the emission queue, a prefetch enable signal is sent to the memory access unit, so that the memory access unit sends a first control signal to the prefetcher according to the prefetch enable signal, and the first control signal carries the memory address where the data to be accessed by the target memory access instruction is located.

8. The method according to claim 7, characterized in that The first control signal also carries the memory address where the target memory access instruction itself is located.

9. The method according to any one of claims 1 to 5, characterized in that The using the target memory access instruction to perform data prefetching comprises: Predicting the memory address of future required data according to the memory address where the cache miss occurs for the target memory access instruction and the historical memory access statistics of the target memory access instruction to obtain a predicted address; According to the predicted address, data required in the future is pre-fetched.

10. The method according to any one of claims 1 to 5, characterized in that The performing data prefetching training on the prefetcher by using the target memory access instruction comprises: The memory address where the cache miss occurs of the target memory access instruction is used to construct or update historical memory access statistics information, so that the prefetcher performs address prefetching according to the historical memory access statistics information.

11. The method according to any one of claims 1 to 5, characterized in that The determining, according to the query result, whether to instruct the prefetcher to perform a prefetch association operation for the target memory access instruction comprises: According to the busyness of the processor and / or the busyness of the memory and the query result, it is determined whether to instruct the prefetcher to perform a prefetch association operation for the target memory access instruction.

12. A pre-fetch control device, characterized in that: include: A query module is configured to query whether there is a target to-be-issued instruction in the transmit queue in response to a cache miss of the target memory access instruction, wherein the target to-be-issued instruction includes at least one source operand, wherein one and only one of the source operands is not ready, and the unready source operand is related to an execution result of the target memory access instruction; A determination module is coupled to the query module and is configured to determine whether to instruct the prefetcher to perform a prefetch association operation for the target memory access instruction based on the query result, and the prefetch association operation includes at least one of the following: using the target memory access instruction to prefetch data, and using the target memory access instruction to train the prefetcher to prefetch data.

13. The pre-fetch control device according to claim 12, characterized in that: The query module is configured as follows: In response to a cache miss occurring in a target memory access instruction, acquiring a register identifier of a destination physical register of the target memory access instruction to obtain a first identifier; Compare the register identifiers of the source physical registers of each queue instruction in the transmit queue with the first identifier respectively, and determine the queue instructions corresponding to the register identifiers having the same comparison results as the first candidate instructions; Among the first candidate instructions, only one first candidate instruction with an unready source operand is determined as the target to-be-issued instruction.

14. The pre-fetch control device according to claim 12, characterized in that: The query module is configured as follows: In response to a cache miss occurring in a target memory access instruction, acquiring a register identifier of a destination physical register of the target memory access instruction to obtain a first identifier; Searching the issue queue for an instruction with only one source operand that is not ready to be executed, and obtaining a second candidate instruction; The register identifiers of the source physical registers of each of the second candidate instructions are compared with the first identifiers respectively, and the second candidate instructions corresponding to the register identifiers having the same comparison results are determined as the target instructions to be issued.

15. The pre-fetch control device according to claim 12, characterized in that: The target memory access instruction is emitted from the emission queue; Each queue instruction in the transmit queue carries corresponding additional information, wherein the additional information includes a reorder cache identifier of a dependent instruction of the queue instruction, and a source operand of the queue instruction is related to an execution result of the dependent instruction; The query module is configured as follows: In response to a cache miss of a target memory access instruction, a reorder cache identifier of the target memory access instruction is compared with a reorder cache identifier in the additional information of each queue instruction in the transmit queue, and a queue instruction corresponding to a reorder cache identifier having the same comparison result is determined as a third candidate instruction; Among the third candidate instructions, only one third candidate instruction with an unready source operand is determined as the target to-be-issued instruction.

16. The pre-fetch control device according to claim 12, characterized in that: The target memory access instruction is emitted from the emission queue; Each queue instruction in the transmit queue carries corresponding additional information, wherein the additional information includes a reorder cache identifier of a dependent instruction of the queue instruction, and a source operand of the queue instruction is related to an execution result of the dependent instruction; The query module is configured as follows: In response to a cache miss of the target memory access instruction, searching the issue queue for an instruction with only one source operand that is not ready to be used, to obtain a fourth candidate instruction; The reorder cache identifier of the target memory access instruction is compared with the reorder cache identifier in the additional information of each of the fourth candidate instructions, and the fourth candidate instruction corresponding to the reorder cache identifier having the same comparison result is determined as the target instruction to be issued.

17. The pre-fetch control device according to any one of claims 12 to 16, characterized in that: The determination module comprises: A first indication submodule is configured to, when the target to-be-issued instruction exists in the emission queue, instruct the prefetcher to perform the prefetch association operation on the target memory access instruction through a memory access unit; or, The second indication submodule is configured to refuse to instruct the prefetcher to perform the prefetch associated operation for the target memory access instruction through the memory access unit when the target to-be-issued instruction does not exist in the transmission queue, or to instruct the prefetcher through the memory access unit not to perform the prefetch associated operation, or to instruct the prefetcher to intercept the prefetch associated operation that has been issued through the memory access unit.

18. The pre-fetch control device according to claim 17, characterized in that: The first indication submodule is configured to send a prefetch enable signal to the memory access unit when the target to-be-issued instruction exists in the transmission queue, so that the memory access unit sends a first control signal to the prefetcher according to the prefetch enable signal, and the first control signal carries the memory address where the data to be accessed by the target memory access instruction is located.

19. The pre-fetch control device according to claim 18, characterized in that: The first control signal also carries the memory address where the target memory access instruction itself is located.

20. The pre-fetch control device according to any one of claims 12 to 16, characterized in that: The prefetcher is configured to: Predicting the memory address of future required data according to the memory address where the cache miss occurs for the target memory access instruction and the historical memory access statistics of the target memory access instruction to obtain a predicted address; According to the predicted address, data required in the future is pre-fetched.

21. The pre-fetch control device according to any one of claims 12 to 16, characterized in that: The prefetcher is configured to: The memory address where the cache miss occurs of the target memory access instruction is used to construct or update historical memory access statistical information, so as to perform address prefetching according to the historical memory access statistical information.

22. The pre-fetch control device according to any one of claims 12 to 16, characterized in that: The determination module is configured to determine whether to instruct the prefetcher to perform a prefetch association operation for the target memory access instruction according to the busyness of the processor and / or the busyness of the memory and the query result.

23. A processor, characterized in that: The processor comprises: a transmission queue, a memory access unit, a prefetcher, and a prefetch control device as claimed in any one of claims 12 to 22; The transmission queue, the pre-fetch control device, the memory access unit and the pre-fetcher are connected in series in sequence; The prefetch control device is configured to learn, through the memory access unit, that a cache miss occurs in the target memory access instruction, and to instruct the prefetcher to perform a prefetch association operation for the target memory access instruction through the memory access unit.

24. An electronic device, characterized in that: The electronic device includes a circuit board, a processor and a memory, wherein the processor and the memory are respectively arranged on the circuit board, and the processor is electrically connected to the memory for performing a read operation or a write operation on the memory, wherein the processor is the processor described in claim 23.

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