Interrupt processing verification method, computer equipment and storage medium

Abstract

The invention provides an interrupt processing verification method, computer equipment and a storage medium, and the method comprises the steps: respectively running an interrupt processing program and a main program through a core reference model, and obtaining a first reference track corresponding to the interrupt processing program and a second reference track corresponding to the main program; obtaining an execution state track after the interrupt is inserted; intercepting a first execution track corresponding to the interrupt processing program in the execution state tracks, and shearing and splicing the execution state tracks before and after the first execution track into a second execution track corresponding to the main program; and comparing the first execution track with the first reference track, and comparing the second execution track with the second reference track. According to the scheme, the interrupt can be inserted in any beat in the program execution process, whether program execution has errors after the interrupt is inserted or not is judged, beat-level comparison can be carried out, the error position can be accurately restored when errors occur, and therefore the asynchronism of interrupt occurrence is supported, and the completeness of interrupt processing verification is guaranteed.

Description

Technical Field

[0001] The present invention relates to the technical field of interrupt verification, and in particular to an interrupt processing verification method, computer equipment and storage medium. Background Art

[0002] High-performance DSP cores, designed for computationally intensive signal processing, typically utilize a Very Long Instruction Word (VLIW) architecture. In this architecture, a single instruction word contains multiple instructions that can be executed in parallel, leveraging a combination of hardware and software to improve program execution efficiency. When verifying DSP cores with instruction delay slots, interrupts are asynchronous events that can occur at any time. Therefore, interrupts can be inserted into the instruction delay slot. If an instruction in the delay slot references the target register of the interrupted instruction, this can result in incorrect execution. Summary of the Invention

[0003] The purpose of the present invention is to provide an interrupt processing verification method, computer equipment and storage medium, which can insert an interrupt at any beat during program execution and determine whether the interrupt is an error. When an error occurs, beat-level comparison can be performed and the error location can be accurately restored, thereby supporting the asynchrony of interrupt occurrence and ensuring the completeness of interrupt processing verification.

[0004] The technical solutions provided by the present invention are as follows:

[0005] The present invention provides an interrupt processing verification method, comprising the steps of:

[0006] Run the interrupt processing program and the main program respectively through the core reference model to obtain a first reference trajectory corresponding to the interrupt processing program and a second reference trajectory corresponding to the main program;

[0007] Obtaining an execution status trace of the execution program after the interrupt handler is inserted into the main program;

[0008] intercepting a first execution trajectory corresponding to the interrupt handling program from the execution status trajectory, and cutting and splicing the execution status trajectories before and after the first execution trajectory into a second execution trajectory corresponding to the main program;

[0009] The first execution trajectory is compared with the first reference trajectory, and the second execution trajectory is compared with the second reference trajectory to determine whether an error occurs in program execution after the interrupt is inserted.

[0010] In order to realize real-time verification of DSP core, this application constructs a core reference model and obtains the reference execution traces of the interrupt handler and the main program respectively. Then, according to the execution status trace of the execution program after the interrupt is inserted, the actual running traces of the interrupt handler and the main program are intercepted respectively, and compared with the reference execution traces to determine whether the program execution is erroneous after the interrupt is inserted. In addition, beat-level comparison can be performed and the error location can be accurately restored when an error occurs, thereby supporting the asynchrony of interrupts and realizing beat-level core precision verification.

[0011] In some embodiments, when the interrupt handler is inserted into the main program, the beat of the main program corresponding to the insertion of the interrupt handler is marked as an interrupt insertion point;

[0012] According to the number of running beats of the interrupt handling program, the beat of the main program corresponding to when the interrupt handling program starts to execute is marked as the interrupt entry point; the beat of the main program corresponding to when the interrupt handling program finishes running is marked as the interrupt exit point;

[0013] The first execution trace corresponding to the interrupt handling program in the execution status trace is intercepted according to the interrupt entry point and the interrupt exit point.

[0014] In some embodiments, further comprising:

[0015] Determining whether the interrupt insertion point is within a delay slot of at least one instruction in the main program;

[0016] If the judgment is no, then directly respond to the interrupt processing program, and the interrupt insertion point is the interrupt entry point;

[0017] If the judgment is yes, the instruction corresponding to the last beat position in the delay slot of each instruction where the interrupt insertion point is located is taken as the first instruction, the end position of the delay slot corresponding to the first instruction is taken as the interrupt entry point, and the first beat number between the interrupt insertion point corresponding to the first instruction and the interrupt entry point is calculated; after the interrupt insertion point corresponding to the main program, a first no-operation instruction is inserted into other instructions except the first instruction, and the end point of the first no-operation instruction corresponds to the interrupt entry point, so that the interrupt handler is executed only after all the instructions that have been run before the interrupt insertion point in the main program are executed.

[0018] This solution marks the insertion beat and exit beat of the interrupt handler when it is inserted, which is used for subsequent real-time beat-level verification. At the same time, before the interrupt handler runs, if it is determined that the insertion point is in the delay slot of at least one instruction in the main program, corresponding no-operation instructions are inserted into other instructions respectively, so that all parallel instructions that have been running in the main program before the interrupt insertion point can be executed, preventing the interrupt handler from interfering with the core main program and ensuring the completeness and real-time performance of the interrupt handling verification.

[0019] In some embodiments, further comprising:

[0020] An instruction list is preset in the core reference model, and the instruction list is used to record the beat number, delay slot number, current execution beat number, and target register number of each instruction when it enters during operation; the delay slot number and target register number are inherent attributes of the instruction, and the current execution beat number is initialized to 0 and increases by 1 for each execution beat during operation;

[0021] Setting a flight instruction set, the flight instruction set consisting of all instructions in the instruction list whose number of delay slots is not equal to the number of current execution beats, adding a newly issued instruction to the flight instruction set whenever a newly issued instruction is issued, and removing the executed instruction from the flight instruction set whenever an instruction is executed;

[0022] When an interrupt is inserted, the flight instruction set is saved in the form of a snapshot, and the difference between the number of delay slots of all instructions in the flight instruction set corresponding to the insertion of the interrupt handler and the current execution beat number is calculated, and the maximum value is taken as the beat number of the first no-operation instruction.

[0023] In some implementations, intercepting the first execution trace corresponding to the interrupt handler in the execution state trace specifically includes:

[0024] If the in-flight instruction set snapshot is empty when the interrupt is inserted, then the interrupt insertion point is the same as the interrupt entry point, and the execution state trajectory from the interrupt entry point to the interrupt exit point can be directly intercepted as the first execution trajectory;

[0025] If the flight instruction set snapshot is not empty, for each current instruction in the flight instruction set snapshot, calculate the difference between the first beat number corresponding to each current instruction and the current execution beat number corresponding to it, and use it as the first delay beat number. Then, cut the data of the target register corresponding to each current instruction from the interrupt entry point forward by the first delay beat number of data; for registers that are not target registers in the flight instruction set snapshot, cut the data of the first beat number of data from the interrupt entry point forward, and obtain the execution status trajectory of the main program before the interrupt entry point.

[0026] After the cutting is completed, the execution state trajectory from the interrupt entry point to the interrupt exit point is intercepted as the first execution trajectory.

[0027] In some embodiments, cutting and splicing the execution state traces before and after the first execution trace into a second execution trace corresponding to the main program specifically includes:

[0028] At the interruption exit point, determining whether the flight instruction set snapshot recorded at the interruption insertion point is an empty set;

[0029] If the flight instruction set snapshot is empty, directly intercepting the execution status trajectory of the main program after the interrupt exit point;

[0030] If the in-flight instruction set snapshot is not empty, for each current instruction in the in-flight instruction set snapshot, calculate the difference between the number of delay slots corresponding to each current instruction and the number of current execution beats as the second delay beat number, and then cut the target register corresponding to each current instruction from the interrupt exit point backward by the second delay beat number of data to obtain the execution status trajectory of the main program after the interrupt exit point;

[0031] The execution status trace of the main program before the interrupt entry point and the execution status trace of the main program after the interrupt exit point are spliced ​​together to obtain the second execution trace.

[0032] In some embodiments, further comprising:

[0033] When there are continuous interrupts and the interrupts are not nested, marking the beat of the main program corresponding to when the interrupt handling program starts executing as the first interrupt entry point according to the beat number corresponding to the first no-operation instruction;

[0034] When a second interrupt handler is received during the execution of a first interrupt handler and the priority of the second interrupt handler is not higher than that of the first interrupt handler, the beat of the main program corresponding to the completion of the first interrupt handler is used as the second interrupt entry point; or

[0035] When it is determined that a second interrupt processing program exists within a first preset time after the execution of the interrupt processing program, the beat of the main program corresponding to the insertion of the second interrupt processing program is used as the second interrupt entry point.

[0036] In some embodiments, further comprising:

[0037] When there are continuous interrupts and the interrupts are nested, marking the beat of the main program corresponding to when the interrupt handling program starts executing as the first interrupt entry point according to the beat number corresponding to the first no-operation instruction;

[0038] When a third interrupt handler is received during the execution of the first interrupt handler, and the priority of the third interrupt handler is higher than that of the first interrupt handler, the execution of the first interrupt handler is interrupted, and the beat of the main program corresponding to the insertion of the third interrupt handler is used as the third interrupt entry point. When the execution of the third interrupt handler is completed, the execution of the first interrupt handler continues.

[0039] In a second aspect, the present application provides a computer device comprising a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above-mentioned interrupt processing verification method.

[0040] In a third aspect, the present application provides a computer storage medium having a computer program or instruction stored thereon, which, when executed by a processor, implements the steps of the interrupt processing verification method according to any one of claims 1 to 8.

[0041] The interrupt processing verification method based on instruction delay slots and the computer device provided by the present invention have at least the following technical effects:

[0042] (1) This solution constructs a core reference model and obtains reference execution traces of the interrupt handler and the main program respectively. Then, based on the execution status trace of the program after the interrupt is inserted, the actual running traces of the interrupt handler and the main program are intercepted and compared with the reference execution traces. This allows us to determine whether the program execution has errors after the interrupt is inserted. In addition, we can perform beat-level comparison and accurately restore the error location when an error occurs, thereby supporting the asynchrony of interrupts and achieving beat-level core precision verification.

[0043] (2) This solution marks the insertion beat and exit beat of the interrupt handler when it is inserted, which is used for subsequent real-time beat-level verification. At the same time, several no-operation instructions are inserted before and after the interrupt handler runs, so that all parallel instructions that have been running in the main program before the interrupt insertion point are completed, preventing the interrupt handler from interfering with the core main program and ensuring the completeness and real-time performance of the interrupt handling verification.

[0044] (3) For continuous interrupts and interrupts that are not nested, the present application first executes the first interrupt handler, then the second interrupt handler, and finally the main program instructions, thereby avoiding register errors caused by dense interrupt insertion and expanding the application of the interrupt handler insertion method;

[0045] (4) For continuous interrupts and nested interrupt insertion, the present application interrupts the first interrupt handler and preferentially executes the second interrupt handler with a higher priority. After the second interrupt handler is executed, the first interrupt handler is continued. This is equivalent to treating the main program after the first interrupt handler is inserted as a new main program, which is interrupted by the second interrupt handler, thereby avoiding register errors caused by nested interrupt insertion and expanding the application of the interrupt handler insertion method;

[0046] (5) This application identifies the no-operation instructions from the interrupt entry point to the interrupt exit point based on the flight instruction set that stores the target register number, and deletes the data corresponding to the no-operation instructions, thereby obtaining the accurate first execution trajectory of the interrupt handler; at the same time, according to the interrupt exit point and the flight instruction set, the data corresponding to the no-operation instructions in the main program are cut off, so that after the execution trajectory of the interrupt handler is intercepted, the second execution trajectory corresponding to the main program can be spliced ​​for subsequent verification, thereby ensuring the reliability of the interrupt verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The preferred implementation scheme will be described below in a clear and understandable manner with reference to the accompanying drawings to further illustrate the above-mentioned characteristics, technical features, advantages and implementation methods of this solution.

[0048] Figure 1 It is a schematic diagram of the overall process of an embodiment of the present invention;

[0049] Figure 2 Schematic diagram of an interrupt handling program and a main program according to an embodiment of the present invention;

[0050] Figure 3 This is a schematic diagram of the main program after the interrupt processing program is inserted into the embodiment of the present invention;

[0051] Figure 4 This is a schematic diagram of interrupt insertion when there are continuous interrupts and the interrupts are not nested according to an embodiment of the present invention;

[0052] Figure 5 This is a schematic diagram of the splicing of the main program running trajectory after interrupt insertion when there are continuous interrupts and the interrupts are not nested in an embodiment of the present invention;

[0053] Figure 6 This is a schematic diagram of inserting when there are continuous interruptions and the interruptions are nested according to an embodiment of the present invention;

[0054] Figure 7 It is a schematic diagram of splicing the running tracks of the main program and the first interrupt handling program after interrupt insertion when there are continuous interrupts and interrupt nesting in an embodiment of the present invention. DETAILED DESCRIPTION

[0055] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the specific embodiments of the present invention will be described below with reference to the accompanying drawings. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings and other embodiments can be obtained based on these drawings without inventive work.

[0056] To simplify the drawings, only the parts relevant to the present invention are schematically shown in each figure. They do not represent the actual structure of the product. Furthermore, to simplify the drawings and facilitate understanding, in some figures, only one of the components with the same structure or function is schematically depicted or labeled. As used herein, "one" not only means "only one" but also "more than one."

[0057] High-performance DSPs typically utilize a very-long instruction word (VLIW) architecture, where a single instruction word contains multiple instructions that can be run in parallel. This integration of hardware and software enhances instruction-level parallelism. At the software level, the compiler analyzes and organizes the source code, packaging instructions that can be run in parallel into a fixed-length instruction word. The DSP core is equipped with instruction fetch and decode components and vector execution components of corresponding widths, enabling simultaneous dispatch of multiple instructions within an instruction word, thereby improving program execution efficiency.

[0058] Each instruction has a different execution cycle. Some instructions execute in just one clock cycle, while others require multiple clock cycles. The instruction execution cycle is referred to as the instruction execution delay slot. Accessing the instruction's target register within the delay slot only yields the old value. The value written to the target register by the instruction becomes visible after the delay slot expires. If an instruction depends on the result of a previous instruction, the compiler must place it outside the delay slot of the dependent instruction, before the next change.

[0059] Interrupts are asynchronous events that can occur at any time, and therefore may be inserted into the instruction delay slot. It should be noted that if an interrupt is inserted into the instruction delay slot, the interrupted program instruction will still be executed. When the interrupt is processed and the main program returns, the interrupted instruction has already been executed, and the instructions in the delay slot can already see the register values ​​updated by the interrupted instruction. If the instruction in the delay slot references the target register of the interrupted handler, it may cause an execution error. To avoid this situation, the following processing should be performed:

[0060] 1. If an instruction in a delay slot references its target register, the program containing this instruction sequence does not support interrupts and interrupts must be disabled before entering the program.

[0061] 2. There is no instruction in the instruction delay slot that references its target register. Even if there is, it is only temporarily used and does not affect the correctness of program execution.

[0062] When the program responds to an interrupt, a no-operation instruction Nop will be inserted into the instruction pipeline to flush out all the remaining instructions in the pipeline, preventing the interrupt program instructions and the interrupted program instructions from running in parallel, causing register read and write competition, and causing errors or exceptions.

[0063] One embodiment of the present invention, as Figure 1 As shown, an interrupt processing verification method is provided, comprising the steps of:

[0064] S100, respectively running an interrupt handler and a main program through a core reference model to obtain a first reference trajectory corresponding to the interrupt handler and a second reference trajectory corresponding to the main program;

[0065] S200, obtaining an execution status trace of the execution program after the interrupt handling program is inserted into the main program;

[0066] S300: intercepting a first execution trace corresponding to the interrupt handling program in the execution status trace, and cutting and splicing the execution status traces before and after the first execution trace into a second execution trace corresponding to the main program;

[0067] S400: Compare the first execution trajectory with the first reference trajectory, and compare the second execution trajectory with the second reference trajectory to determine whether an error occurs in program execution after the interrupt is inserted.

[0068] In a specific implementation, the core reference model is a DSP core reference model; in order to support real-time verification of the DSP core and accurately determine and find the location and instructions of the error, an instruction simulator is usually used as a reference model for operation and comparison. For the same program, it is first run on the instruction simulator. Whenever a core status register is updated, the values ​​of all core status registers are saved as a LOG log file. Each line represents the set of all core status register values ​​in that clock cycle as a reference trajectory. Then run the program in the DSP core simulation environment, and when the core status is updated, capture the values ​​of all core status registers as the actual running status results, and compare them line by line with the recorded reference trajectory. When the core status register value run out of the simulation environment is inconsistent with the generated reference trajectory in a certain clock cycle, it is considered that an error has occurred at that moment, and the simulation is terminated and the error information is printed.

[0069] The above method can accurately locate the location of the first error, facilitating debugging and troubleshooting. However, when an interrupt request is received and the core responds to the interrupt, the core inserts a multi-cycle Nop and waits for the pipeline to empty before executing the interrupt routine. After completion, the program returns to the breakpoint and continues execution.

[0070] Because the core reference model cannot handle interrupts like a real core, it is impossible to directly generate a reference trajectory for comparison. Instead, we can generate the original main program execution log and interrupt handler execution log separately. However, the insertion of the interrupt program disrupts the original core state recording method. Even if we obtain the core state log files of the main program and interrupt handler execution, we cannot debug and check errors using the state comparison method used in real-time verification. In other words, accurate real-time verification is impossible from the time when the interrupt is inserted to the return breakpoint.

[0071] In this embodiment, the present application constructs a core reference model to obtain the reference execution trajectories of the interrupt handler and the main program respectively, and then intercepts the actual running trajectories of the interrupt handler and the main program according to the execution status trajectory of the execution program after the interrupt is inserted, and compares them with the reference execution trajectory, so as to determine whether the program execution is erroneous after the interrupt is inserted, and can perform beat-level comparison and accurately restore the error location when an error occurs, thereby supporting the asynchrony of the interrupt and realizing beat-level core precision verification.

[0072] In one embodiment, based on the aforementioned embodiment, when an interrupt handler is inserted into a main program, the beat of the main program corresponding to the time the interrupt handler is inserted is marked as the interrupt insertion point; based on the number of running beats of the interrupt handler, the beat of the main program corresponding to when the interrupt handler starts executing is marked as the interrupt entry point; the beat of the main program corresponding to when the interrupt handler completes running is marked as the interrupt exit point; and based on the interrupt entry point and the interrupt exit point, the first execution track corresponding to the interrupt handler in the execution status track is intercepted. By recording and marking the beat of the main program when the interrupt is inserted, the beat level of the actual running track can be compared with that of the reference execution track, thereby accurately restoring the error location when an interrupt error occurs.

[0073] Preferably, the method further includes: determining whether the interrupt insertion point is in a delay slot of at least one instruction in the main program;

[0074] If the judgment is no, the interrupt handler is responded to directly, and the interrupt insertion point is the interrupt entry point;

[0075] If the judgment is yes, the instruction corresponding to the last beat position in the delay slot of each instruction where the interrupt insertion point is located is taken as the first instruction, the end position of the delay slot corresponding to the first instruction is taken as the interrupt entry point, and the first beat number between the interrupt insertion point corresponding to the first instruction and the interrupt entry point is calculated; after the interrupt insertion point corresponding to the main program, the first no-operation instruction is inserted into other instructions except the first instruction, and the end point of the first no-operation instruction corresponds to the interrupt entry point, so that the interrupt handler is executed only after all the instructions that have been running before the interrupt insertion point in the main program are executed.

[0076] In this embodiment, a determination is first made as to whether an instruction's delay slot corresponds to the interrupt handler when it is inserted. If not, the interrupt handler can be connected, and the interrupt insertion point becomes the interrupt entry point. If so, to ensure that all instructions running before the interrupt insertion point in the main program are executed before the interrupt handler is executed, the instruction corresponding to the last tick position in the delay slots of the instructions where the interrupt insertion point is located is first set as the first instruction, and the end position of the delay slot corresponding to the first instruction is set as the interrupt entry point. When this instruction is executed, all instructions are executed. Therefore, after the interrupt insertion point corresponding to the main program, a first no-operation instruction can be inserted in the instructions other than the first instruction. The end point of the first no-operation instruction corresponds to the interrupt entry point. The delay slot of each instruction is different, and the number of ticks corresponding to the first no-operation instruction is also different. Since the number of ticks (i.e., the operating cycle) of the interrupt handler is known, the interrupt exit point can be determined based on the tick number of the interrupt insertion point, indicating the end of the interrupt handler execution, thereby completing the insertion of the interrupt handler and recording the marker points of each stage of the interrupt handler execution.

[0077] The present invention marks the interrupt insertion point and the interrupt exit point of the interrupt handler when the interrupt handler is inserted, so as to intercept the execution trajectory of the interrupt handler subsequently and realize real-time beat-level verification. At the same time, before the interrupt handler is run, if it is determined that the insertion point is in the delay slot of at least one instruction in the main program, corresponding no-operation instructions are respectively inserted into other instructions, so that all parallel instructions that have been run by the main program before the interrupt insertion point can be executed completely, thereby preventing the interrupt handler from interfering with the core main program and ensuring the completeness and real-time performance of the interrupt handling verification.

[0078] Figure 2 Schematic diagram of an interrupt handling program and a main program according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the main program after the interrupt handler is inserted into the embodiment of the present invention; Figure 2 and Figure 3 The interruption insertion method of the present application is described in detail.

[0079] Assume that the current VLIW core with instruction delay slots has an issue width of 4, that is, there are four parallel instructions. A square represents a clock cycle, and a continuous rectangle represents an instruction. The rectangle represents an instruction that requires multiple clock cycles to execute. The processor status will be updated after each instruction is executed.

[0080] When the interrupt program is inserted at the position shown in the figure, there are still unexecuted instructions. In order to ensure the execution order of instructions, a no-operation instruction Nop needs to be inserted into the instruction pipeline before the interrupt program is executed to ensure that all instructions before the interrupt insertion point are executed. Then the interrupt handler is executed. When the interrupt exits, it returns to the breakpoint to continue execution. After the interrupt handler is inserted, the core execution time-space diagram is as follows Figure 2 As shown in Figure 2, this is also the core execution state trajectory observed by the simulation verification environment. In order to make an accurate comparison with the reference trajectory at the beat level during verification, it is necessary to Figure 2 The core execution state trace shown is restored to Figure 1 The execution trajectories of the interrupt program and the main program are shown and compared respectively.

[0081] Figure 4 This is a schematic diagram of interrupt insertion when there are continuous interrupts and the interrupts are not nested according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the main program running track splicing when there are continuous interrupts and the interrupts are not nested in the embodiment of the present invention. Figure 4 As shown, the interrupt insertion method of the present application is also applicable to interrupt insertion when there are continuous interrupts and the interrupts are not nested, that is, the main program enters interrupt INT2 soon after returning from interrupt INT1. At this time, the instruction in the main program MAIN delay slot is interrupted again by interrupt INT2.

[0082] When there are continuous interrupts and the interrupts are not nested, marking the beat of the main program corresponding to when the interrupt handling program starts executing as the first interrupt entry point according to the beat number corresponding to the first no-operation instruction;

[0083] When a second interrupt handler is received while a first interrupt handler is being executed and the priority of the second interrupt handler is not higher than that of the first interrupt handler, the beat of the main program corresponding to the completion of the first interrupt handler is used as the second interrupt entry point; or, when it is determined that a second interrupt handler exists within a first preset time after the execution of the interrupt handler, the beat of the main program corresponding to the insertion of the second interrupt handler is used as the second interrupt entry point.

[0084] During continuous interrupts, multiple interrupts may occur in the same instruction delay slot. Essentially, since the instruction delay slot has been calculated in advance when entering the interrupt, in this case, only one snapshot of the flight instruction set needs to be recorded and maintained.

[0085] In a specific implementation, when a second interrupt handler (INT2) is received while a first interrupt handler (INT1) is being executed, and the priority of the second interrupt handler is not higher than that of the first interrupt handler, or when it is determined that a second interrupt handler exists within a first preset time after the execution of the interrupt handler, the beat of the main program corresponding to when the first interrupt handler is completed is used as the second interrupt entry point, or the beat of the main program corresponding to when the second interrupt handler is inserted is used as the second interrupt entry point.

[0086] For interrupt insertion when there are continuous interrupts and the interrupts are not nested, this application first executes the first interrupt handler, waits for the first interrupt handler to be completed, and then executes the second interrupt handler; after the second interrupt handler is completed, it continues to execute the unfinished instructions of the main program after the first interrupt, and finally executes the original instructions of the main program, thereby avoiding register errors caused by dense interrupt insertion and expanding the application of the interrupt handler insertion method.

[0087] It is worth mentioning that the insertion method of this application is also applicable to the interrupt insertion when there are continuous interrupts and the interrupts are not nested, which is composed of three or more interrupt handlers. The processing method is similar to the above-mentioned interrupt insertion method when there are continuous interrupts and the interrupts are not nested, and will not be repeated here.

[0088] Figure 6 This is a schematic diagram of interrupt insertion when there are continuous interrupts and interrupts are nested according to an embodiment of the present invention; Figure 7 This is a schematic diagram of the splicing of the running tracks of the main program and the first interrupt handling program after the interrupt is inserted when there are continuous interrupts and the interrupts are nested in the embodiment of the present invention. Figure 6As shown, the interrupt insertion method of the present application is also applicable to interrupt insertion when there are continuous interrupts and interrupts are nested, that is, during the execution of interrupt 1, interrupt 2 with a higher priority occurs.

[0089] When there are continuous interrupts and the interrupts are nested, the beat of the main program corresponding to the start of the interrupt handling program is marked as the first interrupt entry point according to the beat number corresponding to the corresponding no-operation instruction;

[0090] When a third interrupt handler is received during the execution of the first interrupt handler, and the priority of the third interrupt handler is higher than that of the first interrupt handler, the execution of the first interrupt handler is interrupted, and the beat of the main program corresponding to the insertion of the third interrupt handler is used as the third interrupt entry point. When the execution of the third interrupt handler is completed, the execution of the first interrupt handler continues.

[0091] When interrupts are nested, it is necessary to record multiple snapshots of the flight instruction set. The number of recorded snapshots is equal to the nesting depth, and they are processed in a last-in-first-out order. The execution status trajectory of each interrupt handler is cut in turn, and then the execution status trajectory of the main program is spliced ​​together and compared with the reference status trajectory in turn.

[0092] In a specific implementation, when a third interrupt handler (INT2) is received while the first interrupt handler (INT1) is being executed, and the priority of the third interrupt handler is higher than that of the first interrupt handler, the execution of the first interrupt handler is interrupted, and the beat of the main program corresponding to the insertion of the third interrupt handler is used as the third interrupt entry point. When the execution of the third interrupt handler is completed, the execution of the first interrupt handler continues.

[0093] When interrupts are inserted continuously and nested, the present invention interrupts the first interrupt handler, prioritizes the execution of the second interrupt handler with a higher priority, and resumes the execution of the first interrupt handler after the second interrupt handler completes. This is equivalent to treating the main program after the first interrupt handler is inserted as a new main program, which is interrupted by the second interrupt handler. This avoids register errors caused by nested interrupt insertions and expands the application of the interrupt handler insertion method.

[0094] It is worth mentioning that the insertion method of this application is also applicable to interrupt insertion when there are continuous interrupts and nested interrupts consisting of three or more interrupt handlers. The processing method is similar to the above-mentioned interrupt insertion method when there are continuous interrupts and nested interrupts, and will not be repeated here.

[0095] After the interrupt is inserted, in order to accurately compare the interrupt handler with the reference trace at the beat level during verification, it is necessary to obtain the execution traces of the interrupt handler and the main program based on the current main program execution results and compare them separately. To achieve this goal, it is necessary to set up a core reference model in a simulation verification environment to verify the interrupt handler.

[0096] In one embodiment, based on the above embodiment, the present invention further includes:

[0097] The core reference model has a pre-set instruction list, which records the number of ticks, delay slots, current execution ticks, and target register number of each instruction during execution. The delay slots and target register number are inherent attributes of the instruction. The current execution tick number is initialized to 0 and increases by 1 with each execution tick during execution.

[0098] Set the flight instruction set. The flight instruction set consists of all instructions in the instruction list whose delay slot number is not equal to the current execution beat number. Whenever a new instruction is issued, it is added to the flight instruction set. Whenever an instruction is executed, the executed instruction is removed from the flight instruction set.

[0099] When an interrupt is inserted, the flight instruction set is saved in the form of a snapshot, and the difference between the number of delay slots of all instructions in the flight instruction set corresponding to the insertion of the interrupt handler and the current execution beat number is calculated, and the maximum value is taken as the beat number of the first no-operation instruction.

[0100] In a specific implementation, intercepting a first execution trace corresponding to the interrupt handler in the execution state trace specifically includes:

[0101] If the flight instruction set snapshot is empty when the interrupt is inserted, the interrupt insertion point and the interrupt entry point are the same. The execution state trajectory from the interrupt entry point to the interrupt exit point can be directly intercepted as the first execution trajectory;

[0102] If the flight instruction set snapshot is not empty, for each current instruction in the flight instruction set snapshot, calculate the difference between the first beat number corresponding to each current instruction and the current execution beat number corresponding to it, and use it as the first delay beat number. Then, cut the data of the target register corresponding to each current instruction from the interrupt entry point forward by the first delay beat number of data. For registers that are not target registers in the flight instruction set snapshot, cut the data of the first beat number from the interrupt entry point forward, and obtain the execution status trace of the main program before the interrupt entry point.

[0103] After the cutting is completed, the execution state trajectory from the interrupt entry point to the interrupt exit point is intercepted as the first execution trajectory.

[0104] In a specific implementation, cutting and splicing the execution state traces before and after the first execution trace into a second execution trace corresponding to the main program specifically includes:

[0105] At the interruption exit point, determine whether the flight instruction set snapshot recorded at the interruption insertion point is an empty set;

[0106] If the flight instruction set snapshot is empty, the execution status trace of the main program after the interrupt exit point is directly captured;

[0107] If the flight instruction set snapshot is not empty, for each current instruction in the flight instruction set snapshot, calculate the difference between the number of delay slots corresponding to each current instruction and the current execution beat number, and use this as the second delay beat number. Then, cut the target register corresponding to each current instruction from the interrupt exit point backward by the second delay beat number of data to obtain the execution status trace of the main program after the interrupt exit point.

[0108] The execution status trace of the main program before the interrupt entry point and the execution status trace of the main program after the interrupt exit point are spliced ​​together to obtain a second execution trace.

[0109] In one embodiment, the present invention further provides a computer device comprising a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the interrupt processing verification method of the aforementioned embodiment.

[0110] In one embodiment, the present application provides a computer storage medium having a computer program or instructions stored thereon, which implements the steps of the interrupt handling verification method of the aforementioned embodiment when the computer program or instructions are executed by a processor.

[0111] It should be noted that the above embodiments can be freely combined as needed. The above description is only a preferred embodiment of the present invention. It should be pointed out that those skilled in the art can make several improvements and modifications without departing from the principles of the present invention, and such improvements and modifications should also be considered within the scope of protection of the present invention.

[0112] It should be noted that the above embodiments can be freely combined as needed. The above description is only a preferred embodiment of the present invention. It should be pointed out that those skilled in the art can make several improvements and modifications without departing from the principles of the present invention, and such improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. An interrupt processing verification method, characterized in that: Includes steps: Run the interrupt processing program and the main program respectively through the core reference model to obtain a first reference trajectory corresponding to the interrupt processing program and a second reference trajectory corresponding to the main program; Acquire the execution status trace of the execution program after the interrupt handling program is inserted into the main program; intercepting a first execution trajectory corresponding to the interrupt handling program in the execution status trajectory, and cutting and splicing the execution status trajectories before and after the first execution trajectory into a second execution trajectory corresponding to the main program; The first execution trajectory is compared with the first reference trajectory, and the second execution trajectory is compared with the second reference trajectory to determine whether an error occurs in program execution after the interrupt is inserted.

2. The interrupt processing verification method according to claim 1, characterized in that: When inserting the interrupt processing program into the main program, marking the beat of the main program corresponding to the insertion of the interrupt processing program as an interrupt insertion point; According to the running beat number of the interrupt processing program, marking the beat of the main program corresponding to when the interrupt processing program starts to be executed as an interrupt entry point; Marking the beat of the main program corresponding to the completion of the interrupt handling program as an interrupt exit point; The first execution trajectory corresponding to the interrupt processing program in the execution state trajectory is intercepted according to the interrupt entry point and the interrupt exit point.

3. The interrupt processing verification method according to claim 2, characterized in that: Also includes: Determining whether the interrupt insertion point is in a delay slot of at least one instruction in the main program; If the judgment is no, the interrupt processing program is directly responded to, and the interrupt insertion point is the interrupt entry point; If the judgment is yes, the instruction corresponding to the last beat position in the delay slot of each instruction where the interrupt insertion point is located is taken as the first instruction, the end position of the delay slot corresponding to the first instruction is taken as the interrupt entry point, and the first beat number between the interrupt insertion point corresponding to the first instruction and the interrupt entry point is calculated; after the interrupt insertion point corresponding to the main program, a first no-operation instruction is inserted into other instructions except the first instruction, and the end point of the first no-operation instruction corresponds to the interrupt entry point, so that the interrupt handler is executed after all the instructions that have been running before the interrupt insertion point in the main program are executed.

4. The interrupt processing verification method according to claim 3, characterized in that: Also includes: An instruction list is preset in the core reference model, and the instruction list is used to record the number of beats, the number of delay slots, the current execution beat number and the target register number when each instruction enters during the running process; the number of delay slots and the target register number are inherent attributes of the instruction, the current execution beat number is initialized to 0, and the current execution beat number is increased by 1 for each execution beat during the running process; A flight instruction set is set, wherein the flight instruction set is composed of all instructions in the instruction list whose delay slot number is not equal to the current execution beat number, and each time a new instruction is issued, the newly issued instruction is added to the flight instruction set, and each time an instruction is executed, the executed instruction is removed from the flight instruction set; When an interrupt is inserted, the flight instruction set is saved in the form of a snapshot, and the difference between the number of delay slots of all instructions in the flight instruction set corresponding to the insertion of the interrupt handler and the current execution beat number is calculated, and the maximum value is taken as the beat number of the first no-operation instruction.

5. The interrupt processing verification method according to claim 4, characterized in that: The step of intercepting the first execution trajectory corresponding to the interrupt handling program in the execution state trajectory specifically includes: If the in-flight instruction set snapshot is empty when the interrupt is inserted, the interrupt insertion point is the same as the interrupt entry point, and the execution state trajectory from the interrupt entry point to the interrupt exit point can be directly intercepted as the first execution trajectory; If the flight instruction set snapshot is not empty, for each current instruction in the flight instruction set snapshot, calculate the difference between the first beat number corresponding to each current instruction and the current execution beat number corresponding to it, as the first delay beat number, and then cut the data of the target register corresponding to each current instruction from the interrupt entry point forward by the first delay beat number of data; for the register that does not belong to the target register in the flight instruction set snapshot, cut the data of the first beat number of data from the interrupt entry point forward, and obtain the execution status track of the main program before the interrupt entry point; After the cutting is completed, the execution state trajectory from the interrupt entry point to the interrupt exit point is intercepted as the first execution trajectory.

6. The interrupt processing verification method according to claim 5, characterized in that: Cutting and splicing the execution state tracks before and after the first execution track into a second execution track corresponding to the main program specifically includes: At the interruption exit point, determining whether the flight instruction set snapshot recorded at the interruption insertion point is an empty set; If the flight instruction set snapshot is empty, directly intercepting the execution status track of the main program after the interrupt exit point; If the flight instruction set snapshot is not empty, for each instruction in the flight instruction set snapshot, calculate the difference between the number of delay slots and the number of execution beats at the interrupt insertion point as the second delay beat number, and cut the target register from the interrupt exit point backward by the second delay beat data to obtain the execution status track of the main program after the interrupt exit point; The execution status trace of the main program before the interrupt entry point and the execution status trace of the main program after the interrupt exit point are spliced ​​to obtain the second execution trace.

7. The interrupt processing verification method according to claim 3, characterized in that: Also includes: When there are continuous interrupts and the interrupts are not nested, marking the beat of the main program corresponding to when the interrupt handling program starts to execute as the first interrupt entry point according to the beat number corresponding to the first no-operation instruction; When a second interrupt handler is received during the execution of a first interrupt handler and the priority of the second interrupt handler is not higher than that of the first interrupt handler, the beat of the main program corresponding to the completion of the first interrupt handler is used as the second interrupt entry point; or, When it is determined that there is a second interrupt processing program within the first preset time after the execution of the interrupt processing program, the beat of the main program corresponding to the insertion of the second interrupt processing program is used as the second interrupt entry point.

8. The interruption processing verification method according to claim 3, characterized in that: Also includes: When there are continuous interrupts and the interrupts are nested, marking the beat of the main program corresponding to when the interrupt handling program starts to execute as the first interrupt entry point according to the beat number corresponding to the first no-operation instruction; When a third interrupt handler is received during the execution of the first interrupt handler, and the priority of the third interrupt handler is higher than that of the first interrupt handler, the execution of the first interrupt handler is interrupted, and the beat of the main program corresponding to the insertion of the third interrupt handler is used as the third interrupt entry point. When the execution of the third interrupt handler is completed, the execution of the first interrupt handler continues.

9. A computer device comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the steps of the interrupt processing verification method according to any one of claims 1 to 8.

10. A computer storage medium having a computer program or instruction stored thereon, characterized in that: When the computer program or instruction is executed by a processor, the steps of the interrupt processing verification method according to any one of claims 1 to 8 are implemented.

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