Serial port equipment high availability method and system based on waveform triggering

Abstract

The invention discloses a high availability method and system for serial port equipment based on waveform triggering, and relates to the technical field of industrial control. The method comprises the following steps: monitoring the serial port equipment in real time, reading and recording the level change of the serial port equipment through an FPGA (Field Programmable Gate Array) circuit, and calculating a data processing cycle threshold value; a data packet of a periodic waveform is sent to the serial port device through an FPGA circuit, a data processing period threshold value is adjusted according to the data processing condition of the serial port device, and a feedback waveform of the serial port device is waited to be received; estimating the maximum value of the data packet processing time of one periodic waveform according to the processing capability of the equipment; and according to the maximum value of the data packet processing time and the data processing cycle threshold value, detecting whether an equipment fault occurs, and if the equipment fault occurs, switching to a bypass mode to work. According to the method and the device, the bypass mode can be ensured to be started with the maximum universality without depending on the survival of the operating system, and the device can still be ensured to smoothly enter the bypass mode under the extreme condition that the operating system crashes.

Description

Technical Field

[0001] The present invention relates to the field of industrial control technology, and in particular to a waveform-triggered serial port device high-availability method and device. Background Art

[0002] Serial communication is a very common serial communication method between devices. Because it is simple and convenient, most electronic devices support this communication method. Electronic engineers also often use this communication method to output debugging information when debugging equipment.

[0003] There are many serial port-based industrial control devices at industrial sites, which are used to transmit industrial control data. Since industrial equipment has a high demand for high availability, a reliable high availability solution is needed to ensure that data transmission at the industrial site is not affected when field equipment fails.

[0004] Traditional serial port devices, such as switches and firewalls, have fault bypass functions, that is, when a device fails, on-site communication is ensured to be available through direct conduction. However, the bypass is often triggered after a program crash, and the operating system must be available before it can be used. If the operating system is unavailable, it often fails to switch into bypass mode.

[0005] Based on this, the present invention proposes a high-availability method and apparatus for serial port devices based on waveform triggering. Summary of the invention

[0006] The present invention provides a high availability method for serial port devices based on waveform triggering, comprising:

[0007] Monitor serial port devices in real time, read and record the level changes of serial port devices through FPGA circuits;

[0008] Calculate the data processing cycle threshold according to the level change of the serial port device;

[0009] Send a data packet with a periodic waveform to the serial port device through the FPGA circuit, adjust the data processing cycle threshold according to the data processing status of the lower-layer serial port device, and wait for the feedback waveform received from the lower-layer serial port device;

[0010] Estimate the maximum data packet processing time of a cycle waveform based on the device processing capability;

[0011] According to the maximum value of the data packet processing time and the data processing cycle threshold, it is detected whether a device failure occurs. If a device failure occurs, it switches to the bypass mode.

[0012] In the above-mentioned method for high availability of serial port devices based on waveform triggering, a low-pass filter is added to the FPGA circuit to filter out high-frequency level signals.

[0013] As described above, a waveform-triggered serial port device high availability method is described, in which the level changes of the serial port device are read and recorded through an FPGA circuit, specifically including: obtaining the level changes of the TX pin and RX pin of the serial port device, and recording the level change time T1 of the RX pin and the level change time T2 of the TX pin.

[0014] A waveform-triggered serial port device high availability method as described above, wherein the data processing cycle threshold is adjusted according to the data processing status of the lower-layer serial port device, specifically including: if the serial port device is a firewall device, and the firewall device blocks the message, it is necessary to inform the FPGA circuit, reset the time T1, and recalculate the data processing cycle threshold to ensure that in this case, it is not misjudged as an abnormality; if the firewall device needs to temporarily cache the data packet, it is necessary to inform the FPGA circuit, reset the time T1, and recalculate the data processing cycle threshold to ensure that in this case, it is not misjudged as an abnormality.

[0015] In the above-mentioned method for high availability of serial port devices based on waveform triggering, the data processing cycle threshold T=T2-T1 is calculated.

[0016] The method for high availability of a serial port device based on waveform triggering as described above, wherein the maximum processing time of a data packet is estimated according to the processing capability of the device, specifically comprising the following sub-steps:

[0017] Determine the hardware specifications and performance indicators of the equipment;

[0018] Send a test data packet with a periodic waveform, analyze the process and algorithm of data packet processing, and record the test results;

[0019] By using a pre-set data analysis model and analyzing the test results, the maximum packet flow intensity and rate that the device can handle in a stable state are determined, as well as the maximum packet processing time DT.

[0020] As described above, a waveform-triggered serial port device high availability method, wherein the situation in which a device failure occurs specifically includes: if the serial port device does not lose packets, and the data processing cycle threshold T is greater than the maximum data packet processing time DT, then the serial port device is abnormal; if the FPGA circuit does not receive the waveform sent by the device software within a continuous period of the maximum data packet processing time DT, then it is considered that the lower-layer serial port device is abnormal and switches to bypass mode.

[0021] The present invention also provides a high-availability system for serial port devices based on waveform triggering, comprising: an upper-layer computer and a lower-layer serial port device, wherein the upper-layer computer and the lower-layer serial port device are connected via a serial port line, and the upper-layer computer exchanges data with the lower-layer serial port device via an FPGA circuit; the upper-layer computer executes any one of the above-mentioned methods for high-availability serial port devices based on waveform triggering.

[0022] The present invention also provides a computer storage medium, comprising: at least one memory and at least one processor;

[0023] The memory is used to store one or more program instructions;

[0024] The processor is used to run one or more program instructions to execute any of the above-mentioned methods for high availability of serial port devices based on waveform triggering.

[0025] The beneficial effects achieved by the present invention are as follows: the present invention can ensure the activation of the bypass mode with maximum universality without relying on the survival of the operating system, and can still ensure that the device smoothly enters the bypass mode in the extreme case of an operating system crash. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0027] Figure 1 This is a flow chart of a method for high availability of a serial port device based on waveform triggering provided in Example 1 of the present application;

[0028] Figure 2 This is a schematic diagram of a high-availability system of serial port devices based on waveform triggering provided in Example 2 of the present application. DETAILED DESCRIPTION

[0029] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0030] Embodiment 1

[0031] like Figure 1 As shown, the first embodiment of the present application provides a high availability method for serial port devices based on waveform triggering, including:

[0032] Step 110, the computer monitors the serial port device in real time, and reads and records the level change of the serial port device through the FPGA circuit;

[0033] Specifically, when an upper-layer computer communicates with a lower-layer serial port device (such as a switch or a firewall), a serial port line is usually used to connect the computer to the other device, and data transmission is performed through specific settings and programs.

[0034] Serial communication generally includes at least two signal lines, including the TX pin and the RX pin. The TX pin refers to the data transmission pin in the serial communication. The TX pin is used to send data to an external device. When the transmitter is activated and does not send data, the TX pin is usually at a high level. When sending data, the TX pin will send the data bit by bit according to a specific timing; the RX pin refers to the data receiving pin in the serial communication. The RX pin is used to receive data from an external device. The level change of the RX pin depends on the data transmission status. When there is no data transmission, that is, the RX pin is in an idle state, the RX pin is usually at a high level. When data transmission starts, starting from the data start bit, the RX pin will change from a high level to a low level, marking the start of data transmission. After the data transmission is completed, the RX pin will change from a low level to the initial idle low level state.

[0035] In an embodiment of the present application, the upper-level computer is connected to the serial port device through an FPGA circuit, and the level change of the RX pin of the serial port device is read through the FPGA circuit. When the input level changes, the reading time T1 is recorded; and the level change of the TX of the serial port is read through the FPGA circuit. When there is a level change, the reading time T2 is recorded.

[0036] In addition to the level changes caused by data transmission, the level changes of the TX pin and RX pin of the serial port device may also be caused by high-frequency level signals, and high-frequency signals are generally not data level signals, but interference signals. Therefore, in order to accurately filter the data transmission signal, preferably, a low-pass filter is added to the FPGA circuit to filter out the high-frequency level signal. At this time, it can be considered that the level changes of the TX pin and RX pin of the serial port device are data data transmission.

[0037] Step 120, calculating a data processing cycle threshold according to a level change of the serial port device;

[0038] After receiving the data from the serial port, the switch or firewall will have a processing time period. Therefore, when the level change of the serial port device is obtained, the reading time of the TX pin and the RX pin are recorded as T1 and T2 respectively. T1 and T2 are the data sending time and data receiving time respectively. A data processing cycle threshold T=T2-T1 is set. The calculated T is the data processing time.

[0039] Step 130, the computer sends a data packet with a periodic waveform to the lower-layer serial port device through the FPGA circuit, adjusts the data processing cycle threshold according to the data processing status of the lower-layer serial port device, and waits to receive the feedback waveform of the lower-layer serial port device;

[0040] Specifically, the computer software sends a periodic waveform to the FPGA as a normal signal of the computer. A periodic waveform refers to a signal whose instantaneous amplitude changes repeatedly over time. This signal has an obvious characteristic, that is, its waveform will repeat periodically. This repetition can be a sine signal, a pulse signal, etc.

[0041] The data processing cycle threshold is adjusted according to the data processing status of the lower-layer serial port device, including the following situations:

[0042] ① If the lower-layer serial port device is a firewall device and the firewall device blocks the message, the FPGA circuit needs to be informed to reset the time T1 to ensure that it is not misjudged as an abnormality in this case;

[0043] ② If the firewall device needs to temporarily cache data packets, it needs to inform the FPGA circuit to reset time T1 to ensure that it is not misjudged as an abnormality in this case.

[0044] After resetting data T1, the data processing cycle threshold value T is updated according to the data processing cycle threshold value calculation formula T=T2-T1, and the updated data processing cycle threshold value T is used as a new basis for judging subsequent equipment failures.

[0045] Step 140, the computer estimates the maximum value of the data packet processing time of a periodic waveform according to the processing capacity of the device;

[0046] In the embodiment of the present application, estimating the maximum processing time of a data packet according to the processing capability of the device specifically includes the following sub-steps:

[0047] Step 141, determine the hardware specifications and performance indicators of the device;

[0048] Among them, the hardware specifications of the device include but are not limited to processor model, main frequency, number of cores and architecture, and the performance indicators of the device include but are not limited to memory capacity, bandwidth, storage performance, etc.

[0049] Step 142: Send a test data packet with a periodic waveform, analyze the flow and algorithm of data packet processing, and record the test results;

[0050] Specifically, parse the format and protocol of the data packet, and determine the computational effort and time complexity required for a device with the above hardware specifications and performance indicators to parse the data packet; if operations such as processing, conversion, encryption, decryption, or compression are required on the data in the data packet, analyze the computational complexity and time requirements of these operations; if the data packet needs to be forwarded to other network nodes, consider performance parameters such as the bandwidth, transmission efficiency, and transmission delay of the network interface to evaluate the computational effort and time required for these operations.

[0051] Step 143: Use a pre-set data analysis model to analyze the test results to determine the maximum data packet flow intensity and rate that the device can handle in a stable state, and determine the maximum data packet processing time DT.

[0052] Return to see Figure 1 , step 150, based on the maximum value of the data packet processing time and the data processing cycle threshold, detect whether a device failure occurs, if a device failure occurs, switch to bypass mode.

[0053] In the embodiment of the present application, if the FPGA circuit receives the feedback waveform of the lower-layer serial port device, and the data processing cycle threshold T is within the maximum value of the data packet processing time DT, it is considered that the lower-layer serial port device is working normally. The situation where the device fails specifically includes:

[0054] ① If there is no packet loss in the lower-layer firewall and other devices, and the data processing cycle threshold T is greater than the maximum packet processing time DT, it means that there may be an abnormality and the bypass mode is switched to work.

[0055] For example, if the signal generated by the upper-layer computer only reaches the receiving port of the lower-layer serial port device, the system has already crashed and cannot be processed and sent out normally. If no feedback waveform message is detected within two waveform cycles, it is considered that the lower-layer serial port device is abnormal and switches to bypass mode.

[0056] ② If the FPGA circuit does not receive the waveform sent by the device software within a maximum packet processing time DT period, it is considered that the lower-layer serial port device is abnormal and switches to bypass mode.

[0057] Embodiment 2

[0058] like Figure 2As shown, embodiment 2 of the present invention provides a high-availability system for serial port devices based on waveform triggering, including: an upper-layer computer 21 and a lower-layer serial port device 22, the upper-layer computer 21 and the lower-layer serial port device 22 are connected via a serial port line, and the upper-layer computer 21 exchanges data with the lower-layer serial port device 22 via an FPGA circuit 23.

[0059] The upper computer 21 includes:

[0060] The monitoring module 211 is used to monitor the serial port device in real time and read and record the level change of the serial port device through the FPGA circuit;

[0061] The calculation module 212 is used to calculate the data processing cycle threshold according to the level change of the serial port device; and estimate the maximum value of the data packet processing time of a cycle waveform according to the processing capability of the device;

[0062] The periodic waveform sending module 213 is used to send a data packet of a periodic waveform to the serial port device through the FPGA circuit, adjust the data processing cycle threshold according to the data processing status of the lower-layer serial port device, and wait to receive the feedback waveform of the lower-layer serial port device;

[0063] The fault detection module 214 is used to detect whether a device fault occurs according to the maximum value of the data packet processing time and the data processing cycle threshold, and if a device fault occurs, switch to the bypass mode.

[0064] Corresponding to the above embodiment, an embodiment of the present invention provides a computer storage medium, including: at least one memory and at least one processor;

[0065] The memory is used to store one or more program instructions;

[0066] The processor is used for running one or more program instructions to execute a high availability method of serial port device based on waveform triggering.

[0067] Corresponding to the above-mentioned embodiments, an embodiment of the present invention provides a computer-readable storage medium, wherein the computer storage medium contains one or more program instructions, and the one or more program instructions are used by a processor to execute a waveform-triggered serial port device high-availability method.

[0068] The embodiment disclosed in the present invention provides a computer-readable storage medium, in which computer program instructions are stored. When the computer program instructions are executed on a computer, the computer executes the above-mentioned waveform-triggered serial port device high-availability method.

[0069] In the embodiment of the present invention, the processor may be an integrated circuit chip having the ability to process signals. The processor may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0070] The methods, steps and logic block diagrams disclosed in the embodiments of the present invention can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the embodiments of the present invention can be directly embodied as a hardware decoding processor for execution, or can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The processor reads the information in the storage medium and completes the steps of the above method in combination with its hardware.

[0071] The storage medium may be a memory, which may be, for example, a volatile memory or a nonvolatile memory, or may include both volatile and nonvolatile memory.

[0072] Among them, the non-volatile memory can be a read-only memory (ROM), a programmable ROM (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory.

[0073] The volatile memory may be a random access memory (RAM) which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDRSDRAM), enhanced synchronous DRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM bus DRAM (DRRAM).

[0074] The storage media described in the embodiments of the present invention are intended to include, but are not limited to, these and any other suitable types of memory.

[0075] Those skilled in the art will appreciate that in one or more of the above examples, the functions described in the present invention can be implemented using a combination of hardware and software. When software is used, the corresponding functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any media that facilitates the transmission of computer programs from one place to another. Storage media can be any available media that can be accessed by general or special-purpose computers.

[0076] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made on the basis of the technical solution of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for high availability of serial port devices based on waveform triggering, characterized in that: include: Monitor serial port devices in real time, read and record the level changes of serial port devices through FPGA circuits; Calculate the data processing cycle threshold according to the level change of the serial port device; Send a data packet with a periodic waveform to the serial port device through the FPGA circuit, adjust the data processing cycle threshold according to the data processing status of the serial port device, and wait for the feedback waveform received from the serial port device; Estimate the maximum data packet processing time of a cycle waveform based on the device processing capability; According to the maximum value of the data packet processing time and the data processing cycle threshold, it is detected whether a device failure occurs. If a device failure occurs, it switches to the bypass mode.

2. A waveform-triggered serial port device high availability method as claimed in claim 1, characterized in that: Add a low-pass filter in the FPGA circuit to filter out high-frequency level signals.

3. A waveform-triggered serial port device high availability method as claimed in claim 1, characterized in that: The level changes of the serial port device are read and recorded through the FPGA circuit, specifically including: obtaining the level changes of the TX pin and the RX pin of the serial port device, and recording the level change time T1 of the RX pin and the level change time T2 of the TX pin.

4. A waveform-triggered serial port device high availability method as claimed in claim 3, characterized in that: The data processing cycle threshold is adjusted according to the data processing status of the lower-level serial port device, specifically including: if the serial port device is a firewall device and the firewall device blocks the message, the FPGA circuit needs to be informed to reset the time T1 and recalculate the data processing cycle threshold to ensure that it is not misjudged as an abnormality in this case; if the firewall device needs to temporarily cache the data packet, the FPGA circuit needs to be informed to reset the time T1 and recalculate the data processing cycle threshold to ensure that it is not misjudged as an abnormality in this case.

5. A waveform-triggered serial port device high availability method as claimed in claim 4, characterized in that: Calculate the data processing cycle threshold T=T2-T1.

6. A waveform-triggered serial port device high availability method as claimed in claim 5, characterized in that: Estimate the maximum processing time of a data packet based on the device processing capability, including the following sub-steps: Determine the hardware specifications and performance indicators of the equipment; Send a test data packet with a periodic waveform, analyze the process and algorithm of data packet processing, and record the test results; By using a pre-set data analysis model and analyzing the test results, the maximum packet flow intensity and rate that the device can handle in a stable state are determined, as well as the maximum packet processing time DT.

7. A waveform-triggered serial port device high availability method as claimed in claim 6, characterized in that: The situations in which device failure occurs include: if the serial port device does not lose packets and the data processing cycle threshold T is greater than the maximum data packet processing time DT, then the serial port device is abnormal; if the FPGA circuit does not receive the waveform sent by the device software within a continuous period of the maximum data packet processing time DT, then the lower-layer serial port device is considered to be abnormal and switches to bypass mode.

8. A high-availability system for serial port devices based on waveform triggering, characterized in that: include: An upper-layer computer and a lower-layer serial port device, the upper-layer computer and the lower-layer serial port device are connected via a serial port line, and the upper-layer computer exchanges data with the lower-layer serial port device via an FPGA circuit; the upper-layer computer executes a waveform-triggered serial port device high-availability method as described in any one of claims 1-7.

9. A computer storage medium comprising: at least one memory and at least one processor; The memory is used to store one or more program instructions; A processor is used to run one or more program instructions to execute a waveform-triggered serial port device high-availability method as described in any one of claims 1-7.

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