DRAM (dynamic random access memory) speed reducer for FPGA (field programmable gate array) prototype verification and data writing and reading method

Abstract

The invention discloses a DRAM (Dynamic Random Access Memory) speed reducer for FPGA (Field Programmable Gate Array) prototype verification and a data writing and reading method. The speed reducer comprises a DFI interface module which is used for carrying out data communication with a memory controller designed by a chip to be verified in an FPGA prototype verification platform; the first data caching module is used for performing data caching in the data reading and writing process of a memory controller designed by a chip to be verified and DRAM particles; the first AXI bus conversion module is used for realizing data conversion between the first data storage module and the AXI bus switch; the AXI bus switch is used for realizing AXI bus communication between the memory controller designed by the chip to be verified and the DRAM particles; the FPGA DRAM memory controller is used for controlling a memory controller IP of DRAM particles and providing a user interface of an AXI bus; and the FPGA DRAM PHY is used for controlling the physical layer IP of the DRAM particles and realizing data communication with the DRAM particles. And a buffer speed reduction function is provided between the FPGA prototype verification platform and the DRAM chip, so that the FPGA prototype verification at a low rate is matched with the DRAM chip at a high rate.

Description

Technical Field

[0001] The present invention relates to the field of FPGA prototype verification technology, and in particular to a DRAM speed reducer, data writing and reading method for FPGA prototype verification. Background Art

[0002] In the chip design industry, the cost of taping out a designed chip is very high. Before taping out, the code must be verified to be fully functional, all errors in the front-end logic RTL (Register Transfer Level) design and architecture design must be eliminated, and the driver software and application software must be tested before the chip is taped out. Using an FPGA prototype verification platform is the most advanced method for chip verification. The FPGA prototype verification platform can run the functions of the entire chip at a speed close to the actual chip's working speed. Compared with the speed defects of software simulation work, FPGA prototype verification is more likely to discover defects and errors in RTL design, making it an important method for large-scale chip verification. In addition, the FPGA prototype verification platform can be repeatedly erased and written, and can adapt to repeated iterations of chip design verification.

[0003] DRAM is the most commonly used memory and is an important part of FPGA prototype verification. In the prototype verification process, the use of DRAM can support chip startup, operating system startup, driver verification, application software verification, etc. in the early stage of chip design, thus improving the efficiency of chip system development and verification.

[0004] When using FPGA prototype verification, the corresponding DRAM PHY model is usually provided by suppliers such as Synopsys. Chip designers only need to connect the Memory Controller to the DRAM PHY model through the DFI (DDR PHY interface) to run and verify the entire chip design code on the FPGA prototype verification platform. This solution not only requires the use of commercial FPGA prototype verification equipment, but also requires the purchase of corresponding supporting software, which is costly. Summary of the invention

[0005] The technical problem to be solved by the present invention is that when an FPGA prototype verification platform is currently used to perform chip design code verification work, it is necessary to purchase supporting software for the FPGA prototype verification equipment, which makes the chip design code verification cost relatively high.

[0006] In order to solve the above technical problems, the present invention provides a DRAM speed reducer for FPGA prototype verification, characterized in that it includes a DFI interface module, a first data cache module, a first AXI bus conversion module, an AXI bus switch, an FPGA DRAM memory controller and an FPGA DRAM PHY connected in sequence;

[0007] Wherein, the DFI interface module is used to communicate data with the memory controller of the chip design to be verified in the FPGA prototype verification platform;

[0008] The first data cache module is used to cache data during the process of reading and writing data between the memory controller and the DRAM particles of the chip design to be verified;

[0009] The first AXI bus conversion module is used to implement data conversion between the first data storage module and the AXI bus switch;

[0010] The AXI bus switch is used to provide an AXI bus communication interconnection IP to implement AXI bus communication between the memory controller of the chip design to be verified and the DRAM particles;

[0011] The FPGA DRAM memory controller is used to control the memory controller IP of the DRAM particles and provide a user interface of the AXI bus;

[0012] The FPGA DRAM PHY is used to control the physical layer IP of the DRAM particle to achieve data communication with the DRAM particle.

[0013] Preferably, the first data cache module includes a first-in-first-out memory FIFO 0, a first-in-first-out memory FIFO 1, a first-in-first-out memory FIFO 2 and a first-in-first-out memory FIFO 3;

[0014] Wherein, the first-in-first-out memory FIFO 0 is used to store the address written into DRAM by the memory controller of the chip design to be verified;

[0015] The first-in-first-out memory FIFO 1 is used to store the data written into DRAM by the memory controller of the chip design to be verified;

[0016] The first-in-first-out memory FIFO 2 is used to store the address of the memory controller of the chip design to be verified reading the DRAM;

[0017] The first-in-first-out memory FIFO 3 is used to store the data read by the memory controller of the chip design to be verified from the DRAM.

[0018] Preferably, the DFI interface module is a DDR type interface, a DDR2 type interface, a DDR3 type interface, a DDR4 type interface, a DDR5 type interface, a LPDDR3 type interface, a LPDDR4 type interface, a LPDDR5 type interface, a HBM2 type interface, a HBM3 type interface, a GDDR5 type interface or a GDDR6 type interface.

[0019] Preferably, the DRAM particles are DDR3, DDR4, LPDDR3 or LPDDR4.

[0020] Preferably, the DRAM decelerator verified by the FPGA prototype further comprises a PCIe control module, a system bus control module, a second data cache module and a second AXI bus conversion module connected in sequence, and the second AXI bus conversion module is connected to the AXI bus switch;

[0021] Wherein, the PCIe control module is used to realize data conversion between the external server PCIe bus and the system bus;

[0022] The system bus control module is used to realize data communication with the system bus, decode and execute instructions sent by the system bus, and complete data communication with the second data cache module;

[0023] The second data cache module is used to cache data during the process of data reading and writing between the external server and the DRAM particles;

[0024] The second AXI bus conversion module is used to implement data conversion between the second data storage module and the AXI bus switch.

[0025] Preferably, the second data cache module includes a first-in-first-out memory FIFO 4 and a first-in-first-out memory FIFO 5;

[0026] Wherein, the first-in-first-out memory FIFO 4 is used to store the data written by the system bus into the DRAM particles;

[0027] The first-in-first-out memory FIFO 5 is used to store the data read by the system bus from the DRAM particles.

[0028] In order to solve the above technical problems, the present invention also provides a DRAM data writing method based on the FPGA prototype-verified DRAM speed reducer of the FPGA prototype-verified method, comprising:

[0029] The memory controller of the chip design to be verified in the FPGA prototype verification platform generates a write instruction from the write address and the write data, and sends the write instruction to the DFI interface module;

[0030] The DFI interface module decodes the write instruction to obtain the write address and the write data, and stores the write address in the first-in-first-out memory FIFO 0 of the first data cache module, and stores the write data in the first-in-first-out memory FIFO 1 of the first data cache module;

[0031] When the first AXI bus conversion module detects that both the first-in-first-out memory FIFO 0 and the first-in-first-out memory FIFO 1 have data, the first AXI bus conversion module reads the write address from the first-in-first-out memory FIFO 0, reads the write data from the first-in-first-out memory FIFO 1, and transmits the write address and the write data to the AXI bus switch;

[0032] The AXI bus switch forwards the write address and write data to the FPGA DRAM memory controller;

[0033] The FPGA DRAM memory controller forwards the write address and write data to the FPGA DRAM PHY module;

[0034] The FPGA DRAM PHY module writes the write data into the write address of the DRAM particle

[0035] Preferably, when the memory controller of the chip design to be verified in the FPGA prototype verification platform and the external server simultaneously transmit write addresses and write data to the AXI bus switch, the AXI bus switch arbitrates the memory controller of the chip design to be verified in the FPGA prototype verification platform and the external server to obtain a write arbitration result, and based on the write arbitration result, transmits the corresponding write addresses and write data in sequence to the FPGA DRAM memory controller.

[0036] In order to solve the above technical problems, the present invention also provides a DRAM data reading method based on the FPGA prototype-verified DRAM speed reducer of the FPGA prototype-verified method, comprising:

[0037] The memory controller of the chip design to be verified in the FPGA prototype verification platform generates a read instruction from the read address, and sends the read instruction to the DFI interface module;

[0038] The DFI interface module decodes the read instruction to obtain the read address, and stores the read address in the first-in-first-out memory FIFO 2 of the first data cache module;

[0039] When the first AXI bus conversion module detects that there is data in the first-in-first-out memory FIFO 2, it reads the read address from the first-in-first-out memory FIFO 2 and sends an instruction to read the data in the read address to the AXI bus switch;

[0040] The AXI bus switch forwards the instruction to read the data in the read address to the FPGA DRAM memory controller;

[0041] The FPGA DRAM memory controller forwards the instruction to read the data in the read address to the FPGA DRAM PHY module;

[0042] The FPGA DRAM PHY module reads data from the read address of the DRAM particle based on the instruction to read the data in the read address to obtain read data, and transmits the read data to the FPGA DRAM memory controller;

[0043] The FPGA DRAM memory controller transmits the read data to the AXI bus switch, the AXI bus switch forwards the data to the first AXI bus conversion module, and the first AXI bus conversion module writes the read data into the first-in-first-out memory FIFO 3 of the first data cache module;

[0044] The DFI interface module reads the read data from the first-in-first-out memory FIFO 3, and transmits the read data to the memory controller of the chip design to be verified in the FPGA prototype verification platform.

[0045] Preferably, when the memory controller of the chip design to be verified in the FPGA prototype verification platform and the external server simultaneously transmit read addresses to the AXI bus switch, the AXI bus switch arbitrates the memory controller of the chip design to be verified in the FPGA prototype verification platform and the external server to obtain a read arbitration result, and based on the read arbitration result, transmits the corresponding read addresses in sequence to the FPGA DRAM memory controller.

[0046] Compared with the prior art, one or more embodiments of the above scheme may have the following advantages or beneficial effects:

[0047] The DRAM decelerator for FPGA prototype verification provided by the embodiment of the present invention can directly perform protocol conversion at the DFI interface through the module structure when performing FPGA prototype verification, without accessing the DRAMPHY model provided by the merchant; that is, no matter what type of DRAM is used in the FPGA prototype verification platform, it is only necessary to remove the PHY in the chip design and directly connect the DFI interface to the IP generated by the present invention; it also means that using a DRAM particle entity can support FPGA prototype verification of multiple DRAM chips. The present invention provides a buffer deceleration function between the FPGA prototype verification platform and the DRAM chip, so that the low-speed FPGA prototype verification matches the high-speed DRAM chip; at the same time, it also provides a system bus channel, which is used as a backdoor during FPGA prototype verification, so as to facilitate debugging during FPGA prototype verification.

[0048] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0050] Figure 1 A schematic diagram of the structure of a DRAM speed reducer for FPGA prototype verification according to the first embodiment of the present invention is shown;

[0051] Figure 2 A schematic diagram showing the flow of a method for writing DRAM data for FPGA prototype verification according to a second embodiment of the present invention is shown;

[0052] Figure 3 A schematic flow chart of a DRAM data reading method for FPGA prototype verification according to a third embodiment of the present invention is shown. DETAILED DESCRIPTION

[0053] The following will describe the implementation methods of the present invention in detail with reference to the accompanying drawings and embodiments, so that the implementation process of how the present invention applies technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly. It should be noted that as long as there is no conflict, the various embodiments of the present invention and the various features in the embodiments can be combined with each other, and the technical solutions formed are all within the protection scope of the present invention.

[0054] Embodiment 1

[0055] In order to solve the technical problems existing in the prior art, an embodiment of the present invention provides a DRAM speed reducer for FPGA prototype verification.

[0056] Figure 1 FIG. 1 shows a schematic diagram of the structure of a DRAM speed reducer for FPGA prototype verification according to an embodiment of the present invention; FIG. Figure 1 As shown, the DRAM speed reducer verified by the FPGA prototype of the embodiment of the present invention includes a DFI interface module, a first data cache module, a first AXI bus conversion module, an AXI bus switch, an FPGA DRAM memory controller, an FPGA DRAM PHY, a PCIe control module, a system bus control module, a second data cache module and a second AXI bus conversion module.

[0057] Among them, the DFI interface module, the first data cache module, the first AXI bus conversion module, the AXI bus switch, the FPGA DRAM memory controller and the FPGA DRAM PHY are connected in sequence, the PCIe control module, the system bus control module, the second data cache module and the second AXI bus conversion module are also connected in sequence, and the second AXI bus conversion module is connected to the AXI bus switch.

[0058] The DFI interface module is mainly used to communicate data with the memory controller of the chip design to be verified in the FPGA prototype verification platform, complete the function of interacting with the DFI interface of the memory controller of the chip design to be verified, realize decoding of the instructions sent by the DFI interface and execution of valid instructions, and communicate with the data in the first data cache module. Further, during the data writing process, the DFI interface module is used to receive the write instruction transmitted by the DFI port of the memory controller of the chip design to be verified in the FPGA prototype verification platform, and perform DFI standard protocol parsing on the write instruction, obtain the write address and write data, and transmit the write address and write data to the first data cache module. During the data reading process, it is used to receive the read instruction transmitted by the DFI port of the memory controller of the chip design to be verified in the FPGA prototype verification platform, and perform DFI standard protocol parsing on the read instruction, obtain the read address, and transmit the read address to the first data cache module; during the data reading process, it is used to read the read data from the first data cache module, and transmit the read data to the DFI port of the memory controller of the chip design to be verified in the FPGA prototype verification platform.

[0059] It should be noted that the DFI interface module can be designed as a DDR type interface, DDR2 type interface, DDR3 type interface, DDR4 type interface, DDR5 type interface, LPDDR3 type interface, LPDDR4 type interface, LPDDR5 type interface, HBM2 type interface, HBM3 type interface, GDDR5 type interface or GDDR6 type interface, etc. based on design requirements.

[0060] Correspondingly, the DRAM particle types used in the verification process of the FPGA prototype verification platform may include but are not limited to DDR3, DDR4, LPDDR3, LPDDR4, etc.

[0061] The first data cache module is mainly used to implement data caching during the data reading process or data writing process between the memory controller of the chip design to be verified and the DRAM particles. Specifically, it includes first-in-first-out memory FIFO 0, first-in-first-out memory FIFO 1, first-in-first-out memory FIFO 2 and first-in-first-out memory FIFO 3. First-in-first-out memory FIFO 0 is mainly used to store the address written by the memory controller of the chip design to be verified to the DRAM. First-in-first-out memory FIFO 1 is mainly used to store the data written by the memory controller of the chip design to be verified to the DRAM. First-in-first-out memory FIFO 2 is mainly used to store the address read by the memory controller of the chip design to be verified to the DRAM. First-in-first-out memory FIFO 3 is mainly used to store the data read by the memory controller of the chip design to be verified to the DRAM.

[0062] In this embodiment, all FIFOs play a role of buffering, thereby matching the difference in data rates on both sides. During the FPGA prototype verification process, the clock frequency of the DFI interface is generally less than 10 MHz, while the clock frequency of the DRAM particles operated by the FPGA DRAM PHY is as high as several hundred MHz, so the FIFO plays a role of speed reduction here.

[0063] The first AXI bus conversion module is mainly used to realize data conversion between the first data storage module and the AXI bus switch. Further, it realizes data conversion between the first-in-first-out memory FIFO 0 to FIFO 3 and the AXI bus switch. Further, during the data writing process, the first AXI bus conversion module is used to read the write address in the first-in-first-out memory FIFO 0 and the write data in the first-in-first-out memory FIFO 1 when it is identified that there is data in both the first-in-first-out memory FIFO 0 and the first-in-first-out memory FIFO 1, convert the write address into the write address data in the AXI bus write address channel, and send it to the AXI bus switch; at the same time, convert the write data into the write data in the AXI bus write data channel, and send it to the AXI bus switch. During the data reading process, when it is identified that there is data in the first-in-first-out memory FIFO 2, read the read address in the first-in-first-out memory FIFO 2, convert the read address into the read address data in the AXI bus read address channel, and send it to the AXI bus switch; and read the read data in the read data channel read from the AXI bus switch, and store it in the first-in-first-out memory FIFO 3.

[0064] The AXI bus switch is mainly used to provide the AXI bus communication interconnection IP, and realize the AXI bus communication between the memory controller and the DRAM particles of the chip design to be verified. That is, it is used for one or more hosts to read and write data with one or more slaves through the AXI bus, realizing AXI bus communication and reducing the complexity of mutual communication. The AXI bus switch can realize the clock domain conversion internally without too much external intervention, and further realize the reading of data from the first-in-first-out memory FIFO. In the present invention, the AXI bus switch is used to realize the interconnection of two host modules (i.e., the FPGA prototype verification platform and the external server) and one slave module (i.e., the DRAM particles). Preferably, the AXI bus switch can use the AXI SmartConnect provided by Xilinx.

[0065] AXI SmartConnect is an IP provided by Xilinx for AXI bus communication interconnection. It is used for one or more hosts to read and write data with one or more slaves through the AXI bus. It truly realizes AXI bus communication and reduces the complexity of mutual communication. Clock domain conversion is implemented internally without excessive external intervention. FIFO can be implemented internally, eliminating the need for FIFO, Register, bit width conversion, and protocol conversion in many scenarios. AXISmartConnect is a plug-and-play replacement for the AXI Interconnect v2 core. SmartConnect is more tightly integrated into the Vivado design environment to automatically configure and adapt the connected AXI master-slave IP with minimal user intervention. In this application, AXI SmartConnect is used to interconnect 2 hosts and 1 slave.

[0066] FPGA DRAM memory controller is mainly used to control the memory controller IP of DRAM particles, and provide the user interface of AXI bus to facilitate other modules to access external DRAM particles. FPGA DRAM memory controller can be provided by FPGA chip suppliers.

[0067] FPGA DRAM PHY is mainly used to control the physical layer IP of DRAM particles and realize data communication with DRAM particles. FPGA DRAM PHY can also be provided by FPGA chip suppliers.

[0068] The FPGA DRAM memory controller and FPGA DRAM PHY can be MIG provided by Xilinx. MIG combines the two modules of FPGA DRAM memory controller and FPGA DRAM PHY into one IP.

[0069] The PCIe control module is connected to the external server and is mainly used to realize data conversion between the PCIe bus of the external server and the system bus. Preferably, the PCIe control module can select Xilinx's AXI Bridge for PCI Express Gen3 Subsystem or UltraScale FPGA Gen3 Integrated Block for PCI Express.

[0070] The system bus control module is mainly used to realize the data communication function with the system bus, decode the instructions sent by the system bus and execute the effective instructions, and complete the data communication with the second data cache module. Further, it completes the address exchange and data information transmission with the first-in-first-out memory FIFO 4 and the first-in-first-out memory FIFO 5. The system bus is a self-defined bus type and can be in any form.

[0071] The second data cache module is mainly used to cache data during the data reading and writing process between the external server and the DRAM particles. Further, the second data cache module includes a first-in-first-out memory FIFO 4 and a first-in-first-out memory FIFO 5. Among them, the first-in-first-out memory FIFO 4 is mainly used to store the data written by the system bus to the DRAM particles; the first-in-first-out memory FIFO 5 is mainly used to store the data read by the system bus from the DRAM particles.

[0072] The second AXI bus conversion module is mainly used to realize data conversion between the second data storage module and the AXI bus switch. That is, to realize data conversion between the first-in-first-out memory FIFO 4 and the first-in-first-out memory FIFO 5 and the AXI host bus respectively. Further, during the data writing process, the second AXI bus conversion module is used to read the write address and write data in the first-in-first-out memory FIFO 4 when it is identified that there is data in the first-in-first-out memory FIFO 4, convert the write address into the write address data in the AXI bus write address channel, and send it to the AXI bus switch; at the same time, convert the write data into the write data in the AXI bus write data channel, and send it to the AXI bus switch. During the data reading process, when it is identified that there is data in the first-in-first-out memory FIFO 4, read the read address in the first-in-first-out memory FIFO 4, convert the read address into the read address data in the AXI bus read address channel, and send it to the AXI bus switch; and read the read data in the read data channel read from the AXI bus switch, and store it in the first-in-first-out memory FIFO 5.

[0073] When using different DRAM particle types in chip design, only the DFI interface module needs to be modified in the DRAM speed reducer of FPGA prototype verification, and other modules do not need to be changed after the design and debugging are completed once.

[0074] For example, assuming that the DRAM type used in the chip design waiting for FPGA prototype verification is HBM2, the user only needs to modify the DFI interface module in the DRAM decelerator of the FPGA prototype verification to a DFI interface module for HBM2. In this way, the address and data that the user originally wrote to HBM2 through the memory controller are written to the DRAM particles through the designed DRAM decelerator of the FPGA prototype verification. The read address of the data that the user originally read from HBM2 through the memory controller will be given to the DRAM particles through the designed DRAM decelerator of the FPGA prototype verification, and the data read from the DRAM particles will also be sent to the memory controller of the FPGA prototype verification platform through the designed DRAM decelerator of the FPGA prototype verification. The above-mentioned DRAM particles can be DDR3, DDR4, LPDDR3 or LPDDR4, etc.

[0075] The present invention has two channels for accessing external DRAM particles: a DFI interface channel and a system bus channel. The DFI interface channel is used during FPGA prototype verification, and is connected to the memory controller in the chip design to be verified, and the highest clock frequency is generally less than 10MHz. The system bus channel is used as a backdoor during FPGA prototype verification, and is connected to the system bus converted from a computer or server through a PCIe interface, and the highest clock frequency can be as high as 100MHz. For example, the bootloader (boot program) and kernel (operating system kernel) can be downloaded to a specific address segment of DRAM in advance through the backdoor, and the operating system can be started directly from DRAM. In addition, data at certain addresses in DRAM can be read at any time through the backdoor during the debugging process.

[0076] The DRAM decelerator for FPGA prototype verification provided by the embodiment of the present invention, through the module structure provided, can directly perform protocol conversion at the DFI interface during FPGA prototype verification, without the need to access the DRAM PHY model provided by the merchant; that is, no matter what type of DRAM is used in the FPGA prototype verification platform, it is only necessary to remove the PHY in the chip design and directly connect the DFI interface to the IP generated by the present invention; it also means that using a DRAM particle entity can support FPGA prototype verification of multiple DRAM chips. The present invention provides a buffer deceleration function between the FPGA prototype verification platform and the DRAM chip, so that the low-speed FPGA prototype verification matches the high-speed DRAM chip; it also provides a system bus channel, which is used as a backdoor during FPGA prototype verification, so as to facilitate debugging during FPGA prototype verification.

[0077] Embodiment 2

[0078] In order to solve the technical problems existing in the prior art, an embodiment of the present invention provides a DRAM data writing method for FPGA prototype verification.

[0079] The DRAM data writing method for FPGA prototype verification in this embodiment is implemented based on the DRAM reducer for FPGA prototype verification disclosed in the first embodiment.

[0080] Figure 2 FIG. 1 is a flow chart showing a method for writing DRAM data in a second FPGA prototype verification according to an embodiment of the present invention; Figure 2 As shown, the DRAM data writing method for FPGA prototype verification according to an embodiment of the present invention includes the following steps.

[0081] Step S201: The memory controller of the chip design to be verified in the FPGA prototype verification platform generates a write instruction from a write address and write data, and sends the write instruction to the DFI interface module.

[0082] Step S202: The DFI interface module decodes the write instruction to obtain a write address and write data, and stores the write address in FIFO 0 of the first data cache module, and stores the write data in FIFO 1 of the first data cache module.

[0083] Step S203, when the first AXI bus conversion module detects that both the first-in-first-out memory FIFO 0 and the first-in-first-out memory FIFO 1 have data, it reads the write address from the first-in-first-out memory FIFO 0, reads the write data from the first-in-first-out memory FIFO 1, and transmits the write address and the write data to the AXI bus switch.

[0084] Step S204: The AXI bus switch forwards the write address and write data to the FPGA DRAM memory controller.

[0085] When the memory controller of the chip design to be verified in the FPGA prototype verification platform and the external server transmit write addresses and write data to the AXI bus switch at the same time, the AXI bus switch needs to arbitrate the memory controller of the chip design to be verified in the FPGA prototype verification platform and the external server to obtain a write arbitration result, and then transmit the write address and write data corresponding to the memory controller of the chip design to be verified in the FPGA prototype verification platform and the write address and write data corresponding to the external server to the FPGA DRAM memory controller according to the write arbitration result to realize the writing of the corresponding write data.

[0086] Step S205: The FPGA DRAM memory controller forwards the write address and write data to the FPGA DRAM PHY module.

[0087] Step S206: The FPGA DRAM PHY module writes the write data into the write address of the DRAM particle.

[0088] The DRAM data writing method for FPGA prototype verification provided by the embodiment of the present invention provides a buffer speed reduction function between the FPGA prototype verification platform and the DRAM chip, so that the low-speed FPGA prototype verification matches the high-speed DRAM chip; at the same time, it also provides a system bus channel, which is used as a backdoor during FPGA prototype verification, so as to facilitate debugging during FPGA prototype verification.

[0089] Embodiment 3

[0090] In order to solve the technical problems existing in the prior art, an embodiment of the present invention provides a DRAM data reading method for FPGA prototype verification.

[0091] The DRAM data reading method verified by FPGA prototype in this embodiment is also implemented based on the DRAM reducer verified by FPGA prototype disclosed in the first embodiment.

[0092] Figure 3 FIG. 1 is a flow chart showing a DRAM data reading method for FPGA prototype verification in Embodiment 3 of the present invention; FIG. Figure 3 As shown, the DRAM data reading method for FPGA prototype verification according to an embodiment of the present invention includes the following steps.

[0093] Step S301: the memory controller of the chip design to be verified in the FPGA prototype verification platform generates a read instruction from a read address and sends the read instruction to the DFI interface module.

[0094] Step S302: The DFI interface module decodes the read instruction to obtain a read address, and stores the read address in a first-in-first-out memory FIFO 2 of the first data cache module.

[0095] Step S303: When the first AXI bus conversion module detects that there is data in the FIFO 2, it reads a read address from the FIFO 2 and sends a command to read the data in the read address to the AXI bus switch.

[0096] Step S304: The AXI bus switch forwards the instruction to read the data in the read address to the FPGA DRAM memory controller.

[0097] When the memory controller of the chip design to be verified in the FPGA prototype verification platform and the external server transmit read addresses to the AXI bus switch at the same time, the AXI bus switch needs to arbitrate the memory controller of the chip design to be verified in the FPGA prototype verification platform and the external server to obtain a read arbitration result, and then transmit the read address corresponding to the memory controller of the chip design to be verified in the FPGA prototype verification platform and the read address corresponding to the external server to the FPGA DRAM memory controller according to the read arbitration result to realize the reading of the corresponding read data.

[0098] Step S305, the FPGA DRAM memory controller forwards the instruction to read the data in the read address to the FPGA DRAM PHY module.

[0099] Step S306, the FPGA DRAM PHY module reads data from the read address of the DRAM particle based on the instruction to read the data in the read address to obtain the read data, and transmits the read data to the FPGA DRAM memory controller.

[0100] Step S307, the FPGA DRAM memory controller transmits the read data to the AXI bus switch, the AXI bus switch forwards it to the first AXI bus conversion module, and the first AXI bus conversion module writes the read data into the first-in-first-out memory FIFO 3 of the first data cache module.

[0101] Step S308, the DFI interface module reads the read data from the first-in-first-out memory FIFO 3, and transmits the read data to the memory controller of the chip design to be verified in the FPGA prototype verification platform.

[0102] The DRAM data reading method for FPGA prototype verification provided by the embodiment of the present invention provides a buffer speed reduction function between the FPGA prototype verification platform and the DRAM chip, so that the low-speed FPGA prototype verification matches the high-speed DRAM chip; at the same time, it also provides a system bus channel, which is used as a backdoor during FPGA prototype verification, so as to facilitate debugging during FPGA prototype verification.

[0103] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted for facilitating the understanding of the present invention and are not intended to limit the present invention. Any technician in the technical field to which the present invention belongs can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in the present invention, but the protection scope of the present invention shall still be subject to the scope defined in the attached claims.

Claims

1. A DRAM speed reducer for FPGA prototype verification, characterized in that: It includes a DFI interface module, a first data cache module, a first AXI bus conversion module, an AXI bus switch, an FPGA DRAM memory controller and an FPGA DRAM PHY which are connected in sequence; Wherein, the DFI interface module is used to receive data communication with the memory controller of the chip design to be verified in the FPGA prototype verification platform; The first data cache module is used to cache data during the process of reading and writing data between the memory controller and the DRAM particles of the chip design to be verified; The first AXI bus conversion module is used to implement data conversion between the first data storage module and the AXI bus switch; The AXI bus switch is used to provide an AXI bus communication interconnection IP to implement AXI bus communication between the memory controller of the chip design to be verified and the DRAM particles; The FPGA DRAM memory controller is used to control the memory controller IP of the DRAM particles and provide a user interface of the AXI bus; The FPGADRAM PHY is used to control the physical layer IP of the DRAM particle to achieve data communication with the DRAM particle.

2. The decelerator according to claim 1, characterized in that: The first data cache module includes a first-in-first-out memory FIFO 0, a first-in-first-out memory FIFO 1, a first-in-first-out memory FIFO 2 and a first-in-first-out memory FIFO 3; Wherein, the first-in-first-out memory FIFO 0 is used to store the address written into DRAM by the memory controller of the chip design to be verified; The first-in-first-out memory FIFO 1 is used to store the data written into DRAM by the memory controller of the chip design to be verified; The first-in-first-out memory FIFO 2 is used to store the address of the memory controller of the chip design to be verified reading the DRAM; The first-in-first-out memory FIFO 3 is used to store the data read by the memory controller of the chip design to be verified from the DRAM.

3. The decelerator according to claim 1, characterized in that: The DFI interface module is a DDR type interface, a DDR2 type interface, a DDR3 type interface, a DDR4 type interface, a DDR5 type interface, a LPDDR3 type interface, a LPDDR4 type interface, a LPDDR5 type interface, a HBM2 type interface, a HBM3 type interface, a GDDR5 type interface or a GDDR6 type interface.

4. The decelerator according to claim 3, characterized in that: The DRAM particles are DDR3, DDR4, LPDDR3 or LPDDR4.

5. The decelerator according to claim 1, characterized in that: It also includes a PCIe control module, a system bus control module, a second data cache module, and a second AXI bus conversion module connected in sequence, wherein the second AXI bus conversion module is connected to the AXI bus switch; Wherein, the PCIe control module is used to realize data conversion between the external server PCIe bus and the system bus; The system bus control module is used to realize data communication with the system bus, decode and execute instructions sent by the system bus, and complete data communication with the second data cache module; The second data cache module is used to cache data during the process of data reading and writing between the external server and the DRAM particles; The second AXI bus conversion module is used to implement data conversion between the second data storage module and the AXI bus switch.

6. The decelerator according to claim 5, characterized in that: The second data cache module includes a first-in-first-out memory FIFO 4 and a first-in-first-out memory FIFO 5; Wherein, the first-in-first-out memory FIFO 4 is used to store the data written by the system bus into the DRAM particles; The first-in-first-out memory FIFO 5 is used to store the data read by the system bus from the DRAM particles.

7. A DRAM data writing method based on the FPGA prototype-verified DRAM speed reducer of any one of claims 1 to 6, comprising: The memory controller of the chip design to be verified in the FPGA prototype verification platform generates a write instruction from the write address and the write data, and sends the write instruction to the DFI interface module; The DFI interface module decodes the write instruction to obtain the write address and the write data, and stores the write address in the first-in-first-out memory FIFO 0 of the first data cache module, and stores the write data in the first-in-first-out memory FIFO 1 of the first data cache module; When the first AXI bus conversion module detects that both the first-in-first-out memory FIFO 0 and the first-in-first-out memory FIFO 1 have data, the first AXI bus conversion module reads the write address from the first-in-first-out memory FIFO 0, reads the write data from the first-in-first-out memory FIFO 1, and transmits the write address and the write data to the AXI bus switch; The AXI bus switch forwards the write address and write data to the FPGA DRAM memory controller; The FPGA DRAM memory controller forwards the write address and write data to the FPGA DRAM PHY module; The FPGA DRAM PHY module writes the write data into the write address of the DRAM particle.

8. The writing method according to claim 7, characterized in that: When the memory controller of the chip design to be verified in the FPGA prototype verification platform and the external server simultaneously transmit write addresses and write data to the AXI bus switch, the AXI bus switch arbitrates the memory controller of the chip design to be verified in the FPGA prototype verification platform and the external server to obtain a write arbitration result, and based on the write arbitration result, transmits the corresponding write addresses and write data in sequence to the FPGA DRAM memory controller.

9. A DRAM data reading method based on the FPGA prototype-verified DRAM speed reducer of any one of claims 1 to 6, comprising: The memory controller of the chip design to be verified in the FPGA prototype verification platform generates a read instruction from the read address, and sends the read instruction to the DFI interface module; The DFI interface module decodes the read instruction to obtain the read address, and stores the read address in the first-in-first-out memory FIFO 2 of the first data cache module; When the first AXI bus conversion module detects that there is data in the first-in-first-out memory FIFO 2, it reads the read address from the first-in-first-out memory FIFO 2 and sends an instruction to read the data in the read address to the AXI bus switch; The AXI bus switch forwards the instruction to read the data in the read address to the FPGA DRAM memory controller; The FPGA DRAM memory controller forwards the instruction to read the data in the read address to the FPGA DRAM PHY module; The FPGA DRAM PHY module reads data from the read address of the DRAM particle based on the instruction to read the data in the read address to obtain the read data, and transmits the read data to the FPGA DRAM memory controller; The FPGA DRAM memory controller transmits the read data to the AXI bus switch, and the AXI bus switch forwards the data to the first AXI bus conversion module, and the first AXI bus conversion module writes the read data into the first-in-first-out memory FIFO 3 of the first data cache module; The DFI interface module reads the read data from the first-in-first-out memory FIFO 3 and transmits the read data to the memory controller of the chip design to be verified.

10. The reading method according to claim 9, characterized in that: When the memory controller of the chip design to be verified in the FPGA prototype verification platform and the external server simultaneously transmit read addresses to the AXI bus switch, the AXI bus switch arbitrates the memory controller in the FPGA prototype verification platform and the external server to obtain a read arbitration result, and based on the read arbitration result, transmits the corresponding read addresses in sequence to the memory controller of the chip design to be verified in the FPGA prototype verification platform.

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