Topology circuit for converter with wide voltage range

Abstract

The invention provides a topology circuit for a converter with a wide voltage range, which is characterized by comprising a half-bridge driving circuit and a QR control circuit, the half-bridge drive circuit comprises a first transistor (Q1), a second transistor (Q2), a first blocking capacitor (C1), a second blocking capacitor (C2), a main transformer (T1), a first secondary side rectifier diode (D2), a second secondary side rectifier diode (D3), an energy storage inductor (L1) and a smoothing capacitor (C4). The QR control circuit comprises a control chip (U1), and the control chip (U1) is connected with the half-bridge drive circuit and is externally connected with a measuring chip (U2) at the same time. According to the topological circuit for the converter with the wide voltage range, the zvs soft switching conduction capability can be realized on the premise of adjusting the wide voltage range, the application range of the converter is expanded, and the adaptability of the topological circuit in application is expanded.

Description

Technical Field

[0001] The invention relates to a topological circuit for a converter with a wide voltage range. Background Art

[0002] Usually, quasi-resonant (QR) technology is only used in flyback topology and its derivative topologies (such as BOOST, BUCK-BOOST). The principle is that when the energy stored in the main transformer (energy storage inductor) is released and transferred within a cycle, the topological inductance and parasitic capacitance (mainly the output junction capacitance coss of MOS) will generate a voltage oscillation with the bus voltage as the center line between the drain and source of the topological switch MOS due to underdamping. The voltage bottom of this oscillation is detected to trigger the opening time of the MOS in the next switching cycle to ensure that the MOS is turned on at the lowest drain-source voltage (Vds), achieving a near zero voltage turn-on (zvs) effect to achieve the purpose of reducing the voltage / current superposition loss when the MOS is turned on.

[0003] ZVS is a forced conduction technology that uses high-frequency plasma to create a high-current channel, allowing current to flow from one device to another. In a ZVS system, a flyback transformer (often called a ZVS transformer) is used to generate high-frequency current. When power is input to the ZVS transformer, it generates a high-frequency, high-voltage sine wave. When this sine wave is input to the two poles of another circuit (often called a "load circuit"), it generates high-frequency plasma, allowing current to flow from one pole to the other.

[0004] ZVS technology can be used in many different applications, such as power tools, heaters, and lighting. Its advantage is that it can provide high current output while keeping the efficiency of current flow high.

[0005] Because the flyback converter needs to rely on the energy storage inductor to store energy in the Ton period of the switching cycle, and then transfer and output energy in the Toff period, and because the transformer (inductor) flux only works in the first quadrant (unidirectional magnetization), the magnetic core utilization is low. The above two factors determine that the flyback topology is only suitable for small power converters.

[0006] Another commonly used topology for switching power supplies, the half-bridge converter, is a derivative of the forward topology. This type of topology transfers energy during the Ton and Toff periods of the entire switching cycle, and the transformer's magnetic flux works in the first and third bidirectional magnetizations, with high core utilization, so the half-bridge topology is usually suitable for high-power converters in design. However, when the traditional half-bridge topology is controlled using PWM (pulse width modulation), it is difficult to achieve the reduction of switching losses of switching elements through zvs. The dedicated zvs half-bridge topology (such as the common LLC topology) can only be adjusted and controlled through the PFM (frequency modulation) method with a fixed 50% duty cycle. The disadvantage of PFM control is also obvious: it is impossible to obtain a wide range of voltage regulation. This makes the LLC topology very limited in application. Summary of the invention

[0007] In view of this, the present invention provides a topology circuit for a converter with a wide voltage range, which can achieve voltage adjustment in a wide voltage range and realize ZVS soft switching by combining QR technology and traditional board bridge technology.

[0008] The present invention provides a topological circuit for a converter with a wide voltage range, and the specific structure includes:

[0009] A half-bridge drive circuit and a QR control circuit; the half-bridge drive circuit comprises a first transistor Q1, a second transistor Q2, a first DC blocking capacitor C1, a second DC blocking capacitor C2, a main transformer T1, a first secondary-side rectifier diode D2, a second secondary-side rectifier diode D3, an energy storage inductor L1 and a smoothing capacitor C4; the first transistor Q1 and the second transistor Q2 are respectively connected to the same side of the main transformer T1, and are respectively set as the upper tube and the lower tube of the half-bridge drive circuit; the first DC blocking capacitor C1 and the second DC blocking capacitor C2 are respectively connected in parallel with the first transistor Q1 and the second transistor Q2; the first secondary-side rectifier diode D2 and the second secondary-side rectifier diode D3 are connected to the other side of the main transformer T1, and the energy storage inductor L1 and the smoothing capacitor C4 are connected in parallel with each other and are connected in series to one side of the first secondary-side rectifier diode D2;

[0010] The QR control circuit includes a control chip U1, which is connected to the half-bridge drive circuit and is externally connected to a measurement chip U2;

[0011] The measuring chip U2 is connected to the half-bridge driving circuit and the QR control circuit, samples and measures the PWM-P driving signal sent by the QR chip, and sets a dead time Td.

[0012] Furthermore, isolation gate drivers are respectively connected to the circuits of the first transistor Q1 and the second transistor Q2, the first driver U3 is connected to the first transistor Q1, and the second driver U4 is connected to the second transistor Q2.

[0013] Furthermore, the QR control circuit is provided with an open collector output OC1, which is externally connected to the output terminal.

[0014] Furthermore, the energy storage inductor L1 and the smoothing capacitor C4 are externally connected to the output end.

[0015] Furthermore, the control chip U1 outputs a single-ended driving signal PWM-P when in operation.

[0016] Furthermore, the measuring chip immediately sends out a pulse width signal H0 having the same width as the PWM-P signal after the dead time Td.

[0017] Furthermore, a bootstrap circuit is connected to the first driver U3 to provide an operating voltage for the driver U3.

[0018] Furthermore, the bootstrap circuit includes a bootstrap resistor R5, a bootstrap diode D1 and a bootstrap capacitor C3; the three are connected in series and in parallel to the first driver U3.

[0019] Furthermore, the energy storage inductor L1 operates in an inductor current discontinuous mode.

[0020] Furthermore, the control chip U1 has a skip cycle detection function, and can select the valley bottom of the damped oscillation at which to turn on according to the duty cycle and load conditions.

[0021] Beneficial Effects

[0022] According to a topological circuit for a converter with a wide voltage range of the present invention, the capability of ZVS soft switching can be realized while adjusting the wide voltage range, thereby improving the application range of the converter and expanding the adaptability of the topological circuit in application. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solution of the embodiment of the present invention, the drawings of the embodiment are briefly introduced below.

[0024] The drawings described below are only related to some embodiments of the present invention, but are not intended to limit the present invention.

[0025] In the attached picture:

[0026] Figure 1 A circuit diagram according to an embodiment of the present invention is shown;

[0027] Figure 2 A schematic diagram of a working signal waveform according to the present invention is shown;

[0028] Reference numerals list

[0029] Q1. First transistor, Q2. Second transistor, C1. First DC blocking capacitor, C2. Second DC blocking capacitor, T1. Main transformer, D2. First secondary side rectifier diode, D3. Second secondary side rectifier diode, L1. Energy storage inductor, C4. Smoothing capacitor, U1. Control chip, U2. Measurement chip, U3. First driver, U4. Second driver, R5. Bootstrap resistor, D1. Bootstrap diode, C3. Bootstrap capacitor. DETAILED DESCRIPTION

[0030] In order to make the purpose, scheme and advantages of the technical solution of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described in conjunction with the drawings of the specific embodiments of the present invention. Unless otherwise specified, the terms used herein have the usual meanings in the art. The same reference numerals in the drawings represent the same components.

[0031] like Figure 1 As shown, in one embodiment:

[0032] The present invention proposes a topological circuit for a converter with a wide voltage range, comprising: a half-bridge drive circuit and a QR control circuit; the half-bridge drive circuit comprises a first transistor Q1, a second transistor Q2, a first DC blocking capacitor C1, a second DC blocking capacitor C2, a main transformer T1, a first secondary-side rectifier diode D2, a second secondary-side rectifier diode D3, an energy storage inductor L1 and a smoothing capacitor C4; the first transistor Q1 and the second transistor Q2 are respectively connected to the same side of the main transformer T1, and are respectively set as the upper tube and the lower tube of the half-bridge drive circuit; the first DC blocking capacitor C1 and the second DC blocking capacitor C2 are respectively connected in parallel with the first transistor Q1 and the second transistor Q2; the first secondary-side rectifier diode D2 and the second secondary-side rectifier diode D3 are connected to the other side of the main transformer T1, and the energy storage inductor L1 and the smoothing capacitor C4 are connected in parallel with each other and are connected in series to one side of the first secondary-side rectifier diode D2;

[0033] The QR control circuit includes a control chip U1, which is connected to the half-bridge drive circuit and is externally connected to a measurement chip U2;

[0034] The measuring chip U2 is connected to the half-bridge driving circuit and the QR control circuit, and adopts a high-speed single-chip microcomputer (model AMP32F051 K) to sample and measure the PWM-P driving signal issued by the QR chip, and set a dead time Td.

[0035] Furthermore, isolation gate drivers are respectively connected to the circuits of the first transistor Q1 and the second transistor Q2, the first driver U3 is connected to the first transistor Q1, and the second driver U4 is connected to the second transistor Q2.

[0036] Furthermore, the QR control circuit is provided with an open collector output OC1, which is externally connected to the output terminal.

[0037] Furthermore, the energy storage inductor L1 and the smoothing capacitor C4 are externally connected to the output end.

[0038] Furthermore, the control chip U1 outputs a single-ended driving signal PWM-P when in operation.

[0039] Furthermore, the measuring chip immediately sends out a pulse width signal H0 having the same width as the PWM-P signal after the dead time Td.

[0040] Furthermore, a bootstrap circuit is connected to the first driver U3 to provide an operating voltage for the driver U3.

[0041] Furthermore, the bootstrap circuit includes a bootstrap resistor R5, a bootstrap diode D1 and a bootstrap capacitor C3; the three are connected in series and in parallel to the first driver U3.

[0042] Furthermore, the energy storage inductor L1 operates in an inductor current discontinuous mode.

[0043] Furthermore, the control chip U1 has a skip cycle detection function, and can select the valley bottom of the damped oscillation at which to turn on according to the duty cycle and load conditions.

[0044] The working principle of this embodiment is as follows Figure 2 As shown:

[0045] The phase of the pulse width PWM-P emitted by the control chip U1 in the QR circuit is in phase with the drive signal GL of the second transistor Q2 in the lower tube, so that the second transistor Q2 is turned on first at startup. The primary chip power supply system P+12V is provided by the bootstrap resistor R5, and the bootstrap diode D1 charges the bootstrap capacitor C3 through the lower tube loop, thereby establishing the power supply VB required by the driver U3 of the upper tube.

[0046] ①T1 moment: GL is high level, Q2 is turned on, because the drain potential VS before Q2 is turned on is equal to the neutral voltage VZ, so Q2 is inevitably turned on under non-zvs conditions, and when Q2 is turned on, D3 is turned on to transfer energy to the output. At the same time, due to the existence of the transformer primary winding excitation inductance, the inductor stores a part of the energy, which is not transferred to the output.

[0047] ②T2 moment: GL is low level, Q2 is turned off, the energy stored in the excitation inductor is released, and the VS voltage reverses. Due to the effect of the output capacitor coss of the MOS, the VS voltage will reach the bus voltage VBus after a short charging time. The inductor energy continues to flow to the bus through the body diode of the upper tube Q1. At this time, the drain-source voltage of Q1 is clamped at a body diode forward voltage drop VF level, which is approximately equal to zero voltage. The T2 time is determined by U2 according to the excitation inductor and the parameters of the MOS coss. This time is also the dead time Td mentioned above.

[0048] ③T3: Because the drain-source voltage VDS of Q1 is zero, GH outputs a high level at this time, which can achieve zero voltage turn-on (zvs) of Q1. After Q1 is turned on, D2 conducts and transfers energy to the output. At the same time, the primary winding excitation inductance stores a part of the energy, which is not transferred to the output.

[0049] ④T4 moment: GH outputs low level, Q1 is turned off, similarly, the inductor energy is released, the VS voltage is reversed and the current is continued through the body diode of the lower tube Q2. If a dead time Td is set at T4 moment and Q2 is turned on immediately afterwards, it is the same as the conventional LLC control mode, and both the upper and lower tubes can be turned on at zero voltage, but what we need is PWM modulation to obtain a wide voltage adjustment rate. At T4 moment, the time when Q1 is turned on is determined by the converter's need to combine the input and output conditions and ultimately by the control loop. During this period, the valley detection mechanism of the QR control chip is relied on to determine the time when Q1 is turned on in the next cycle.

[0050] Finally, it should be noted that when describing the position of each component and the matching relationship between them, the present invention usually takes one / a pair of components as an example. However, those skilled in the art should understand that such position, matching relationship, etc. are also applicable to other components / other pairs of components.

[0051] The above description is merely an exemplary embodiment of the present invention and is not intended to limit the protection scope of the present invention. The protection scope of the present invention is determined by the appended claims.

Claims

1. A topological circuit for a converter with a wide voltage range, It is characterized in that The specific structure includes: A half-bridge drive circuit and a QR control circuit; the half-bridge drive circuit comprises a first transistor (Q1), a second transistor (Q2), a first DC blocking capacitor (C1), a second DC blocking capacitor (C2), a main transformer (T1), a first secondary-side rectifier diode (D2), a second secondary-side rectifier diode (D3), an energy storage inductor (L1) and a smoothing capacitor (C4); the first transistor (Q1) and the second transistor (Q2) are respectively connected to the same side of the main transformer (T1) and are respectively set as the upper tube and the lower tube of the half-bridge drive circuit; the first DC blocking capacitor (C1) and the second DC blocking capacitor (C2) are respectively connected in parallel with the first transistor (Q1) and the second transistor (Q2); the first secondary-side rectifier diode (D2) and the second secondary-side rectifier diode (D3) are connected to the other side of the main transformer (T1), and the energy storage inductor (L1) and the smoothing capacitor (C4) are connected in parallel with each other and are connected in series to one side of the first secondary-side rectifier diode (D2); The QR control circuit comprises a control chip (U1), the control chip U1 is connected to the half-bridge drive circuit and is externally connected to a measurement chip (U2); The measuring chip (U2) is connected to the half-bridge driving circuit and the QR control circuit, samples and measures the PWM-P driving signal emitted by the QR chip, and sets a dead time Td.

2. A topological circuit for a converter with a wide voltage range according to claim 1, It is characterized in that Isolation gate drivers are respectively connected to the circuits of the first transistor (Q1) and the second transistor (Q2), the first driver (U3) is connected to the first transistor (Q1), and the second driver (U4) is connected to the second transistor (Q2).

3. A topological circuit for a converter with a wide voltage range according to claim 1, It is characterized in that The QR control circuit is provided with an open collector output (OC1) which is connected to an output terminal.

4. A topological circuit for a converter with a wide voltage range according to claim 1, It is characterized in that The energy storage inductor (L1) and the smoothing capacitor (C4) are externally connected to the output end.

5. A topological circuit for a converter with a wide voltage range according to claim 1, It is characterized in that The control chip (U1) outputs a single-ended driving signal PWM-P when in operation.

6. A topological circuit for a converter with a wide voltage range according to claim 1, It is characterized in that The measuring chip immediately sends out a pulse width signal H0 having the same width as the PWM-P signal after the dead time Td.

7. A topological circuit for a converter with a wide voltage range according to claim 1, It is characterized in that The first driver (U3) is connected to a bootstrap circuit to provide an operating voltage for the driver U3.

8. A topological circuit for a converter with a wide voltage range according to claim 7, It is characterized in that The bootstrap circuit comprises a bootstrap resistor (R5), a bootstrap diode (D1) and a bootstrap capacitor (C3); the three are connected in series and in parallel to the first driver U3.

9. A topological circuit for a converter with a wide voltage range according to claim 1, It is characterized in that The energy storage inductor (L1) operates in an inductor current discontinuous mode.

10. The topological circuit for a converter with a wide voltage range according to claim 1, It is characterized in that The control chip (U1) has a skip cycle detection function and can select the valley bottom of the damped oscillation to be turned on according to the duty cycle and load conditions.

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