Three-channel randomization circuit applied to three-channel interleaved sampling front end

Abstract

The invention relates to a three-channel randomization circuit applied to a three-channel interleaved sampling front end, which belongs to the technical field of mixed signal integrated circuits and comprises a pseudo-random signal generation circuit, a three-channel randomization signal generation circuit, a sampling hold circuit and a channel selection circuit. The three-channel randomization signal generation circuit comprises three channel enable signal sub-circuits which correspondingly obtain three channels of channel enable signals and three channels of selection signals according to pseudo-random signals respectively; each channel enable signal sub-circuit selects a pseudo-random signal according to the three channel enable signals to obtain a front enable signal, and controls the level of the channel enable signal output in the next period according to the front enable signal; the three-channel randomization signal generation circuit is controlled through closed-loop logic, input of the three-channel randomization signal generation circuit is provided by pseudo-random signals, control over sampling and selection of sampling holding signals are achieved through the three-channel enable signal sub-circuits, and the linearity of the interleaving type sampling front end is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of mixed signal integrated circuits, and in particular relates to a three-channel randomization circuit applied to a three-channel interleaved sampling front end. Background Art

[0002] The traditional sampling front end only contains a single-channel sample-and-hold circuit. The use of a dual-channel interleaved sample-and-hold circuit structure can double the sampling rate of the sampling front end. However, at the same time, the mismatch between channels will deteriorate the linearity and spurious performance of the sampling front end. Therefore, it is necessary to suppress the impact of the mismatch between channels on the performance of the interleaved sampling front end in order to improve the working performance of the sampling front end. Summary of the invention

[0003] In order to solve the above problems existing in the prior art, the present invention provides a three-channel randomization circuit applied to a three-channel interleaved sampling front end. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0004] The present invention provides a three-channel randomization circuit applied to a three-channel interleaved sampling front end, comprising: a pseudo-random signal generating circuit, a three-channel randomization signal generating circuit, a sampling and holding circuit and a channel selection circuit; wherein the pseudo-random signal generating circuit, the output end of which is connected to the input end of the three-channel randomization signal generating circuit, is used to generate a pseudo-random signal; the three-channel randomization signal generating circuit comprises: three channel enable signal sub-circuits, the three channel enable signal sub-circuits respectively obtain three-way channel enable signals and three-way selection signals according to the pseudo-random signals; wherein each channel enable signal sub-circuit obtains a three-way channel enable signal and a three-way selection signal according to the three-way channel enable signal. A pseudo-random signal is selected by a signal generator to obtain a pre-enable signal, and the level of the channel enable signal output in the next cycle is controlled according to the pre-enable signal; a sampling and holding circuit includes three sampling and holding channels, and the three sampling and holding channels are connected to the three channel enable signal sub-circuits in a one-to-one correspondence; each sampling and holding channel inputs an external sampling signal, and is used to sample and hold the external sampling signal under the control of the corresponding channel enable signal to obtain a sampling and holding signal; a channel selection circuit, the input end of which is respectively connected to the output end of the three-channel randomization signal generation circuit and the sampling and holding circuit, and is used to select and output the sampling and holding signal according to the selection signal.

[0005] In one embodiment of the present invention, a pseudo-random signal generating circuit includes: a trigger and an XOR gate; a plurality of triggers are connected in series in sequence; the output ends of the last two triggers are respectively connected to the input ends of the XOR gate, and the output end of the XOR gate is connected to the input end of the first trigger; the output end of the last trigger serves as the output end of the pseudo-random signal generating circuit to output a pseudo-random signal.

[0006] In one embodiment of the present invention, the three channel enable signal sub-circuits have the same structure, and each channel enable signal sub-circuit inputs the channel enable signal output by the other two channel enable signal sub-circuits.

[0007] In one embodiment of the present invention, each channel enable signal subcircuit includes: a first selector, a second selector, a third selector, a first trigger and a second trigger; wherein, the input ends of the first selector and the second selector are respectively input with a positive pseudo-random signal and a negative pseudo-random signal, the control ends are respectively input with the channel enable signals output by the other two channel enable signal subcircuits, and the output ends are both connected with the input end of the first trigger; the input end of the third selector is input with a ground signal, the control end is connected with the output end of the first trigger, and the output end is connected with the input end of the first trigger; the clock signal end of the first trigger is input with a working clock signal, the reset signal end is input with a reset signal, the set signal end is input with a ground signal, and the output end outputs the channel enable signal; the input end of the second trigger is connected with the output end of the first trigger, the reset signal end is input with a reset signal, the set signal end is input with a ground signal, and the output end outputs a selection signal.

[0008] In one embodiment of the present invention, among the three channel enable signals respectively output by the three channel enable signal sub-circuits, one channel enable signal is at a high level, and all the other channel enable signals are at a low level.

[0009] In one embodiment of the present invention, the control end of the x-th channel enable signal subcircuit that inputs the y-th channel enable signal has a phase opposite to that of the pseudo-random signal input to the control end of the z-th channel enable signal subcircuit that inputs the y-th channel enable signal; wherein x=1,2,3; y=1,2,3 and y≠x; z≠x and z≠y.

[0010] In one embodiment of the present invention, the first selector, the second selector and the third selector have the same structure, and all include: an inverter INV1, an inverter INV2, a MOS tube M0, a MOS tube M1, a MOS tube M2 and a MOS tube M3; wherein, the input end of the inverter INV1 inputs a pseudo-random signal, and the output end of the inverter INV1 is respectively connected to the gate of the MOS tube M0 and the gate of the MOS tube M3; the source of the MOS tube M0 is connected to the power supply voltage end, and the drain is connected to the source of the MOS tube M1; the input end of the inverter INV2 inputs a channel enable signal, and the output end is connected to the gate of the MOS tube M1; the drain of the MOS tube M1 is connected to the drain of the MOS tube M2, and outputs a pre-enable signal; the gate of the MOS tube M2 is connected to the input end of the inverter INV2, and the source is connected to the drain of the MOS tube M3; the source of the MOS tube M3 is connected to the ground end.

[0011] In one embodiment of the present invention, the first trigger and the second trigger have the same structure, and both include: a transmission gate TG1, a transmission gate TG2, a transmission gate TG3, a transmission gate TG4, a NOR gate NOR1, a NOR gate NOR2, a NOR gate NOR3 and a NOR gate NOR4; wherein, the input end of the transmission gate TG1 serves as the input end of the first trigger or the second trigger, the inverting control end inputs a positive clock signal, the positive control end inputs an inverting clock signal, and the output end is respectively connected to the output end of the transmission gate TG2 and the first input end of the NOR gate NOR1; the second input end of the NOR gate NOR1 inputs a ground signal, and the output end is respectively connected to the input end of the transmission gate TG3 and the first input end of the NOR gate NOR3; the second input end of the NOR gate NOR3 inputs a ground signal A reset signal is input to the output end of the transmission gate TG2; an inverted clock signal is input to the inverting control end of the transmission gate TG2, and a positive clock signal is input to the positive control end; the output end of the transmission gate TG3 is respectively connected to the first input end of the NOR gate NOR2 and the output end of the transmission gate TG4, an inverted clock signal is input to the inverting control end, and a positive clock signal is input to the positive control end; a reset signal is input to the second input end of the NOR gate NOR2, and the output end is connected to the first input end of the NOR gate NOR4, and serves as the output end of the first trigger or the second trigger; a ground signal is input to the second input end of the NOR gate NOR4, and the output end is connected to the input end of the transmission gate TG4; a positive clock signal is input to the inverting control end of the transmission gate TG4, and an inverted clock signal is input to the positive control end.

[0012] In one embodiment of the present invention, each sampling and holding channel includes: a MOS tube M4 and a capacitor C1; wherein the drain of the MOS tube M4 inputs an external sampling signal, the gate inputs a channel enable signal, the source is connected to the first plate of the capacitor C1, and outputs the sampling and holding signal; the second plate of the capacitor C1 is connected to the ground terminal.

[0013] In one embodiment of the present invention, a channel selection circuit includes: a transmission gate TG5, a transmission gate TG6 and a transmission gate TG7; wherein the first ends of the transmission gates TG5, TG6 and TG7 are respectively connected to the output ends of the three sampling and holding channels, and the holding signals are respectively input, the inverting control ends are respectively input with inverting selection signals, the positive control ends are respectively input with positive selection signals, the output ends are connected to each other, and serve as the output ends of the channel selection circuit.

[0014] Compared with the prior art, the present invention has the following beneficial effects:

[0015] The three-channel randomization circuit applied to the three-channel interleaved sampling front end of the present invention, the pseudo-random signal generating circuit generates a pseudo-random signal; the three-channel randomization signal generating circuit is controlled by closed-loop logic, the input of which is provided by the pseudo-random signal, and the control of sampling and the selection of the sampling and holding signal are realized through three channel enable signal sub-circuits, and the spurious frequency introduced by the mismatch is averaged into the noise floor, thereby improving the linearity of the interleaved sampling front end.

[0016] The three-channel randomization circuit applied to the three-channel interleaved sampling front end of the present invention, the input of each selector is provided by a pseudo-random signal, and the three channel enable signals realize the control of the output of the channel selection circuit through feedback, ensuring that three channel enable signals are randomly output in each working cycle and one of them is at a high level, and the other two channel enable signals are at a low level, thereby being used to control the randomization work of the three-channel interleaved sampling front end. The channel enable signal subcircuit includes a delay of a selector and a trigger, which can effectively improve the operating frequency of the three-channel randomization circuit, thereby improving the sampling rate of the three-channel interleaved sampling front end during randomization work, reducing the frequency spurious caused by channel mismatch in the output signal, and overall improving the linearity of the sampling front end.

[0017] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following specifically cites a preferred embodiment and describes it in detail with the accompanying drawings as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a structural block diagram of a three-channel randomization circuit applied to a three-channel interleaved sampling front end provided by an embodiment of the present invention;

[0019] Figure 2 is a circuit structure diagram of a pseudo-random signal generating circuit provided by an embodiment of the present invention;

[0020] Figure 3 is a circuit structure diagram of a three-channel randomized signal generating circuit provided by an embodiment of the present invention;

[0021] Figure 4 is a timing diagram of a three-channel randomized signal generating circuit provided by an embodiment of the present invention;

[0022] Figure 5 The embodiment of the present invention Figure 3 The circuit structure diagram of the selector in FIG.

[0023] Figure 6 The embodiment of the present invention Figure 3 The circuit structure diagram of the trigger in ;

[0024] Figure 7 is a circuit structure diagram of a sample-and-hold circuit provided in an embodiment of the present invention;

[0025] Figure 8 is a circuit structure diagram of a channel selection circuit provided by an embodiment of the present invention;

[0026] Fig. 9 (a) is an output spectrum diagram of an existing interleaved sampling front end;

[0027] Fig. 9 (b) is an output spectrum diagram of a three-channel interleaved sampling front end using a three-channel randomized signal generating circuit provided in an embodiment of the present invention.

[0028] Reference numerals: 100 - pseudo-random signal generating circuit; 200 - three-channel randomized signal generating circuit; 210 - channel enable signal sub-circuit; 300 - sample and hold circuit; 400 - channel selection circuit. DETAILED DESCRIPTION

[0029] In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, a three-channel randomization circuit applied to a three-channel interleaved sampling front end proposed by the present invention is described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0030] The above and other technical contents, features and effects of the present invention are clearly presented in the following detailed description of the specific implementation modes in conjunction with the accompanying drawings. Through the description of the specific implementation modes, the technical means and effects adopted by the present invention to achieve the predetermined purpose can be more deeply and specifically understood. However, the attached drawings are only for reference and explanation purposes and are not used to limit the technical solutions of the present invention.

[0031] Embodiment 1

[0032] like Figure 1 and Figure 3As shown, this embodiment provides a three-channel randomization circuit applied to a three-channel interleaved sampling front end, including: a pseudo-random signal generating circuit 100, a three-channel randomization signal generating circuit 200, a sampling and holding circuit 300 and a channel selection circuit 400; wherein, the output end of the pseudo-random signal generating circuit 100 is connected to the input end of the three-channel randomization signal generating circuit 200, and the output end of the three-channel randomization signal generating circuit 200 is respectively connected to the input end of the sampling and holding circuit 300 and the channel selection circuit 400; at the same time, the input end of the sampling and holding circuit 300 inputs an external sampling signal, and samples and holds the sampling signal under the control of the three-channel randomization signal generating circuit 200; the input end of the channel selection circuit 400 is connected to the output end of the three-channel randomization signal generating circuit 200, which is controlled by the three-channel randomization signal generating circuit 200, selects the sampling and holding signal output by the three-channel randomization signal generating circuit 200 and outputs it.

[0033] In this embodiment, if Figure 1 As shown, the output end of the pseudo-random signal generating circuit 100 is connected to the input end of the three-channel randomized signal generating circuit 200 for generating a pseudo-random signal.

[0034] In an optional embodiment, if Figure 1 and Figure 2 As shown, the pseudo-random signal generating circuit 100 includes: a trigger and an XOR gate; a plurality of triggers are connected in series, the output of the previous trigger is connected to the input of the next trigger; the outputs of the last two triggers are respectively connected to the input of the XOR gate, and the output of the XOR gate is connected to the input of the first trigger; the output of the last trigger is used as the output of the pseudo-random signal generating circuit 100 to output a pseudo-random signal. The pseudo-random signal is a pair of signals with opposite phases, wherein the positive phase pseudo-random signal is represented by Rand and the negative phase pseudo-random signal is represented by express.

[0035] It is worth noting that the input of the trigger DFF1 is generated by the outputs of the triggers DFF6 and DFF7 through an XOR logic, and the pseudo-random signal generating circuit 100 can output a pseudo-random number sequence with approximately the same probability of high level and low level.

[0036] In this embodiment, if Figure 1 and Figure 3As shown, the three-channel randomized signal generating circuit 200 includes: three channel enable signal sub-circuits 210, and the three channel enable signal sub-circuits 210 respectively obtain three channel enable signals and three selection signals according to the pseudo-random signals; wherein each channel enable signal sub-circuit 210 selects the pseudo-random signal according to the three channel enable signals to obtain the pre-enable signal, and controls the level of the channel enable signal outputted in the next cycle according to the pre-enable signal.

[0037] In an optional embodiment, if Figure 1 and Figure 3 As shown, the three channel enable signal sub-circuits 210 have the same structure, and each channel enable signal sub-circuit 210 inputs the channel enable signal output by the other two channel enable signal sub-circuits 210 .

[0038] For example, Figure 1 and Figure 3 As shown, each channel enable signal sub-circuit 210 includes: a first selector S1, a second selector S2, a third selector S3, a first trigger DFF8 and a second trigger DFF9; wherein the first selector S1 and the second selector S2 are respectively input with a positive pseudo-random signal Rand and an inverse pseudo-random signal The control end respectively inputs the channel enable signals output by the other two channel enable signal sub-circuits 210, and the output ends are connected to the input end of the first trigger DFF8; the input end of the third selector S3 inputs the ground signal, the control end is connected to the output end of the first trigger DFF8, and the output end is connected to the input end of the first trigger DFF8; the clock signal end of the first trigger DFF8 inputs the working clock signal, the reset signal end inputs the reset signal Rst, the set signal end inputs the ground signal, and the output end outputs the channel enable signal; the input end of the second trigger DFF9 is connected to the output end of the first trigger, the reset signal end inputs the reset signal Rst, the set signal end inputs the ground signal, and the output end outputs the selection signal.

[0039] For example, Figure 5As shown, the first selector, the second selector and the third selector have the same structure, and all include: an inverter INV1, an inverter INV2, a MOS tube M0, a MOS tube M1, a MOS tube M2 and a MOS tube M3; wherein, the input end of the inverter INV1 inputs a pseudo-random signal, and the output end of the inverter INV1 is respectively connected to the gate of the MOS tube M0 and the gate of the MOS tube M3; the source of the MOS tube M0 is connected to the power supply voltage end VDD, and the drain is connected to the source of the MOS tube M1; the input end of the inverter INV2 inputs a channel enable signal, the output end is connected to the gate of the MOS tube M1, the drain of the MOS tube M1 is connected to the drain of the MOS tube M2, and the inverter INV2 outputs a pre-enable signal; the gate of the MOS tube M2 is connected to the input end of the inverter INV2, and the source is connected to the drain of the MOS tube M3; the source of the MOS tube M3 is connected to the ground end GND.

[0040] For example, Figure 6 As shown, the first trigger and the second trigger have the same structure, both including: transmission gate TG1, transmission gate TG2, transmission gate TG3, transmission gate TG4, NOR gate NOR1, NOR gate NOR2, NOR gate NOR3 and NOR gate NOR4; wherein, the input end of the transmission gate TG1 is used as the input end of the first trigger or the second trigger, the inverting control end inputs a positive clock signal, the positive control end inputs an inverting clock signal, and the output end is respectively connected to the output end of the transmission gate TG2 and the first input end of the NOR gate NOR1; the second input end of the NOR gate NOR1 inputs a ground signal, and the output end is respectively connected to the input end of the transmission gate TG3 and the first input end of the NOR gate NOR3; the second input end of the NOR gate NOR3 inputs a reset signal Rst, The output end is connected to the input end of the transmission gate TG2; the inverting control end of the transmission gate TG2 inputs an inverted clock signal, and the positive phase control end inputs a positive phase clock signal; the output end of the transmission gate TG3 is respectively connected to the first input end of the NOR gate NOR2 and the output end of the transmission gate TG4, the inverting control end inputs an inverted clock signal, and the positive phase control end inputs a positive phase clock signal; the second input end of the NOR gate NOR2 inputs a reset signal Rst, the output end is connected to the first input end of the NOR gate NOR4, and serves as the output end of the first trigger or the second trigger; the second input end of the NOR gate NOR4 inputs a ground signal, and the output end is connected to the input end of the transmission gate TG4; the inverting control end of the transmission gate TG4 inputs a positive phase clock signal, and the positive phase control end inputs an inverted clock signal.

[0041] For example, Figure 3 and Figure 4 As shown, when the working clock signal CK flips from low level to high level, the output signal of the trigger S3 is updated to the current input signal. When the reset signal Rst is high level, the output of the trigger S3 is reset to low level; when the signal at the set end is high level, the output of the trigger S3 is reset to high level.

[0042] It is worth noting that, among the three channel enable signals respectively output by the three channel enable signal sub-circuits 210 , one channel enable signal is at a high level, and all the other channel enable signals are at a low level.

[0043] Furthermore, the control end of the x-th channel enable signal sub-circuit 210 that inputs the y-th channel enable signal has a phase opposite to that of the pseudo-random signal input to the control end of the z-th channel enable signal sub-circuit 210 that inputs the y-th channel enable signal; wherein, x=1,2,3; y=1,2,3 and y≠x; z≠x and z≠y.

[0044] In other words, if the input terminal of the selector of the x-th channel enable signal subcircuit 210 inputs the positive phase pseudo random signal Rand, and the selector is controlled by the y-th channel enable signal; then at this time, the input terminal of the selector of the z-th channel enable signal subcircuit 210 controlled by the y-th channel enable signal inputs the negative phase pseudo random signal Rand. Similarly, if the input terminal of the selector of the x-th channel enable signal sub-circuit 210 inputs the inverted pseudo-random signal And the selector is controlled by the yth channel enable signal; then at this time, the input end of the selector of the zth channel enable signal sub-circuit 210 controlled by the yth channel enable signal inputs the positive phase pseudo random signal Rand.

[0045] For example, Figure 3 As shown, taking the first channel enable signal subcircuit 210 as an example, the input end of its selector S1 inputs the positive phase pseudo random signal Rand, and the selector S1 is controlled by the second channel enable signal; then at this time, the selector S8 of the third channel enable signal subcircuit 210 is also controlled by the second channel enable signal, and the input end of the selector S8 inputs the negative phase pseudo random signal

[0046] In an optional embodiment, if Figure 1 As shown, the sampling and holding circuit 300 includes three sampling and holding channels, and the three sampling and holding channels are connected to the three channel enable signal sub-circuits 210 in a one-to-one correspondence; each sampling and holding channel inputs an external sampling signal, and is used to sample and hold the external sampling signal under the control of the corresponding channel enable signal to obtain a sampling and holding signal.

[0047] For example, Figure 1 and Figure 7 As shown, each sampling and holding channel includes: a MOS tube M4 and a capacitor C1; wherein the drain of the MOS tube M4 inputs an external sampling signal, the gate inputs a channel enable signal, the source is connected to the first plate of the capacitor C1, and outputs a sampling and holding signal; the second plate of the capacitor C1 is connected to the ground terminal GND.

[0048] It is worth noting that the sample and hold circuit 300 is controlled by a channel enable signal. When the channel enable signal is high, the sample and hold signal follows the input change and the circuit starts sampling. When the channel enable signal is low, the sample and hold signal indicating that sampling is completed is output.

[0049] In an optional embodiment, if Figure 1 As shown, the channel selection circuit 400 has input terminals connected to the output terminals of the three-channel randomized signal generating circuit 200 and the sample-and-hold circuit 300, respectively, and is used to select and output the sample-and-hold signal according to the selection signal.

[0050] For example, Figure 1 and Figure 8 The channel selection circuit 400 shown includes: transmission gate TG5, transmission gate TG6 and transmission gate TG7; wherein the first ends of transmission gate TG5, transmission gate TG6 and transmission gate TG7 are respectively connected to the output ends of three sampling and holding channels, and hold signals are respectively input, the inverting control ends are respectively input with inverting selection signals, the positive control ends are respectively input with positive selection signals, and the output ends are connected to each other and serve as the output end of the channel selection circuit 400. Since only one of the three selection circuits is at a high level, correspondingly, only one transmission gate is turned on, that is, the sampling and holding signal is selected to be output.

[0051] It is worth noting that the first selector S1, the second selector S2 and the third selector S3 are respectively controlled by the second channel enable signal, the third channel enable signal and the first channel enable signal, and when one of the second channel enable signal, the third channel enable signal and the first channel enable signal is at a high level, the selector controlled by the high level selects the pseudo-random signal Rand inputted thereto as the pre-enable signal, and obtains the channel enable signal and the selection signal in the subsequent connected trigger. Among them, the channel enable signal controls the three sampling and holding channels of the sampling and holding circuit 300 for sampling, and the selection signal controls the channel selection circuit 400 to select the sampling and holding signal output of one of the sampling and holding circuits 300. For a low-level channel enable signal, the output signal of the channel enable signal subcircuit 210 where it is located is in a floating state.

[0052] like Figures 1 to 3 As shown, the working principle of the three-channel randomization circuit applied to the three-channel interleaved sampling front end of this embodiment is described:

[0053] If the three-channel randomized signal generating circuit 200 of this embodiment maintains the initial state of the normal working circuit, one of the channel enable signals must be high and the other two channel enable signals must be low. The generation of the first channel enable signal is described below as an example. Since each sampling and holding channel must be enabled at most once within two sampling cycles, if it is at a high level in the current cycle, the first sampling and holding channel is enabled at this time, and the channel enable signals input to the other two sampling and holding channels are both low levels, then the first channel enable signal is fed back to the front-end selector S3 to select the low level to the first pre-enable signal, so as to ensure that the first channel enable signal output by the trigger in the next cycle is low, that is, the first sampling and holding channel is disabled.

[0054] If the first channel enable signal is low in the current cycle, one of the other two channel enable signals is high. If the second channel enable signal is high, the positive pseudo-random signal Rand is selected as the first pre-enable signal. If the third channel enable signal is high, the negative pseudo-random signal Rand is selected. As the first pre-enable signal, due to the positive pseudo-random signal Rand and the negative pseudo-random signal They are all generated by the pseudo-random generation module, so the high and low level states of the first channel enable signal in the next cycle are also random.

[0055] In addition, in order to ensure that only one sampling and holding channel is enabled in the same cycle, for selector S1, if its control signal is the second channel enable signal, the corresponding input signal is the positive phase pseudo-random signal Rand, then for selector S8, its input signal is the negative phase pseudo-random signal Furthermore, since the sample-and-hold signal after the channel sampling is completed needs to be selected to be output in the next cycle, each selection signal is generated in the trigger after one working cycle according to the channel enable signal.

[0056] Further, such as Figure 4 As shown, the channel enable signal and the selection signal complete the initial state reset under the control of a short high-level reset signal Rst. After the reset is completed, the first channel enable signal and the second channel enable signal are low-level, the third channel enable signal is high-level, and the first selection signal to the third selection signal are all low-level. For the first channel enable signal of the next cycle, since the first channel enable signal and the second channel enable signal are low-level and the third channel enable signal is high-level at this time, the selectors S1 and S3 do not work, and the selector S2 converts the inverted signal of the positive pseudo-random signal Rand, that is, the inverted pseudo-random signal When the rising edge of the working clock signal arrives, the first pre-enable signal is synchronized to the first channel enable signal by the trigger DFF8, so the first channel enable signal is synchronized to the first channel enable signal according to The level state is randomly flipped to a high level or maintained at a low level. For the second channel enable signal of the next cycle, similar to the generation mechanism of the first channel enable signal, the selector S4 transmits the random signal Rand to the second pre-enable signal. When the rising edge of the working clock signal arrives, the second channel enable signal is synchronized to Rand and randomly maintains a low level or flips to a high level (opposite to the state of the first channel enable signal). For the third channel enable signal of the next cycle, the selector S9 transmits the low level to the third pre-enable signal. When the rising edge of the working clock signal arrives, the third channel enable signal flips to a low level. In addition, the first to third selection signals are respectively generated by the first to third channel enable signals under the control of the working clock signal after one working cycle.

[0057] like Fig. 9 As shown, by introducing the three-channel randomized signal generating circuit 200 of this embodiment into the three-channel interleaved sampling front end, compared with an existing interleaved sampling front end, the spurious energy is reduced by more than 20dB, which has a great improvement effect on the spurious performance, thereby improving the linearity of the overall sampling network.

[0058] The three-channel randomization circuit applied to the three-channel interleaved sampling front end of the present invention, the pseudo-random signal generating circuit generates a pseudo-random signal; the three-channel randomization signal generating circuit is controlled by closed-loop logic, the input of which is provided by the pseudo-random signal, and the control of sampling and the selection of the sampling and holding signal are realized through three channel enable signal sub-circuits, and the spurious frequency introduced by the mismatch is averaged into the noise floor, thereby improving the linearity of the interleaved sampling front end.

[0059] The three-channel randomization circuit applied to the three-channel interleaved sampling front end of the present invention, the input of each selector is provided by a pseudo-random signal, and the three channel enable signals realize the control of the output of the channel selection circuit through feedback, ensuring that three channel enable signals are randomly output in each working cycle and one of them is at a high level, and the other two channel enable signals are at a low level, thereby being used to control the randomization work of the three-channel interleaved sampling front end. The channel enable signal subcircuit includes a delay of a selector and a trigger, which can effectively improve the operating frequency of the three-channel randomization circuit, thereby improving the sampling rate of the three-channel interleaved sampling front end during randomization work, reducing the frequency spurious caused by channel mismatch in the output signal, and overall improving the linearity of the sampling front end.

[0060] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant is intended to cover non-exclusive inclusion, so that the article or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed. In the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the article or device including the elements. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The orientation or position relationship indicated by "up", "down", "left", "right", etc. is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention.

[0061] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A three-channel randomization circuit applied to a three-channel interleaved sampling front end, characterized in that: include: A pseudo-random signal generating circuit (100), a three-channel randomized signal generating circuit (200), a sampling and holding circuit (300) and a channel selecting circuit (400); Wherein, the output end of the pseudo-random signal generating circuit (100) is connected to the input end of the three-channel randomized signal generating circuit (200) to generate a pseudo-random signal; The three-channel randomized signal generating circuit (200) comprises: three channel enable signal subcircuits (210), wherein the three channel enable signal subcircuits (210) respectively obtain three channel enable signals and three selection signals according to the pseudo-random signals; wherein each of the channel enable signal subcircuits (210) selects the pseudo-random signal according to the three channel enable signals to obtain a pre-enable signal, and controls the level of the channel enable signal outputted in the next cycle according to the pre-enable signal; The sampling and holding circuit (300) comprises three sampling and holding channels, and the three sampling and holding channels are connected to the three channel enable signal subcircuits (210) in a one-to-one correspondence; each of the sampling and holding channels inputs an external sampling signal, and is used to sample and hold the external sampling signal under the control of the corresponding channel enable signal to obtain a sampling and holding signal; The channel selection circuit (400) has input ends respectively connected to the output ends of the three-channel randomization signal generating circuit (200) and the sampling and holding circuit (300), and is used to select and output the sampling and holding signal according to the selection signal.

2. The three-channel randomization circuit applied to a three-channel interleaved sampling front end according to claim 1, characterized in that: The pseudo-random signal generating circuit (100) comprises: a trigger and an XOR gate; a plurality of the triggers are connected in series in sequence; the output ends of the last two triggers are respectively connected to the input ends of the XOR gates, and the output end of the XOR gates is connected to the input end of the first trigger; the output end of the last trigger serves as the output end of the pseudo-random signal generating circuit (100) to output a pseudo-random signal.

3. The three-channel randomization circuit applied to a three-channel interleaved sampling front end according to claim 1, characterized in that: The three channel enable signal subcircuits (210) have the same structure, and each of the channel enable signal subcircuits (210) inputs the channel enable signal output by the other two channel enable signal subcircuits (210).

4. The three-channel randomization circuit applied to a three-channel interleaved sampling front end according to claim 3, characterized in that: Each of the channel enable signal sub-circuits (210) comprises: a first selector, a second selector, a third selector, a first trigger and a second trigger; The input ends of the first selector and the second selector are respectively input with a positive phase pseudo-random signal and a negative phase pseudo-random signal, the control ends are respectively input with channel enable signals output by the other two channel enable signal sub-circuits (210), and the output ends are both connected with the input end of the first trigger; The input terminal of the third selector inputs a ground signal, the control terminal is connected to the output terminal of the first trigger, and the output terminal is connected to the input terminal of the first trigger; The clock signal end of the first trigger inputs a working clock signal, the reset signal end inputs a reset signal, the set signal end inputs a ground signal, and the output end outputs a channel enable signal; the input end of the second trigger is connected to the output end of the first trigger, the reset signal end inputs a reset signal, the set signal end inputs a ground signal, and the output end outputs a selection signal.

5. The three-channel randomization circuit applied to a three-channel interleaved sampling front end according to claim 1, characterized in that: Among the three channel enable signals respectively output by the three channel enable signal subcircuits (210), one channel enable signal is at a high level, and all the other channel enable signals are at a low level.

6. The three-channel randomization circuit applied to a three-channel interleaved sampling front end according to claim 4, characterized in that: The control end of the x-th channel enable signal sub-circuit (210) that inputs the y-th channel enable signal has a phase opposite to that of the pseudo-random signal inputted by the control end of the z-th channel enable signal sub-circuit (210) that inputs the y-th channel enable signal; Among them, x=1,2,3; y=1,2,3 and y≠x; z≠x and z≠y.

7. The three-channel randomization circuit applied to a three-channel interleaved sampling front end according to claim 4, characterized in that: The first selector, the second selector and the third selector have the same structure, and all include: an inverter INV1, an inverter INV2, a MOS tube M0, a MOS tube M1, a MOS tube M2 and a MOS tube M3; The pseudo-random signal is input to the input end of the inverter INV1, and the output end of the inverter INV1 is respectively connected to the gate of the MOS tube M0 and the gate of the MOS tube M3; the source of the MOS tube M0 is connected to the power supply voltage end, and the drain is connected to the source of the MOS tube M1; The input end of the inverter INV2 inputs the channel enable signal, and the output end is connected to the gate of the MOS tube M1; the drain of the MOS tube M1 is connected to the drain of the MOS tube M2, and outputs the pre-enable signal; The gate of the MOS tube M2 is connected to the input end of the inverter INV2, and the source is connected to the drain of the MOS tube M3; the source of the MOS tube M3 is connected to the ground end.

8. The three-channel randomization circuit applied to a three-channel interleaved sampling front end according to claim 7, characterized in that: The first trigger and the second trigger have the same structure, and both include: a transmission gate TG1, a transmission gate TG2, a transmission gate TG3, a transmission gate TG4, a NOR gate NOR1, a NOR gate NOR2, a NOR gate NOR3 and a NOR gate NOR4; The input end of the transmission gate TG1 is used as the input end of the first trigger or the second trigger, the inverting control end is input with a positive clock signal, the positive control end is input with an inverting clock signal, and the output end is respectively connected with the output end of the transmission gate TG2 and the first input end of the NOR gate NOR1; The ground signal is input to the second input terminal of the NOR gate NOR1, and the output terminal is respectively connected to the input terminal of the transmission gate TG3 and the first input terminal of the NOR gate NOR3; the reset signal is input to the second input terminal of the NOR gate NOR3, and the output terminal is connected to the input terminal of the transmission gate TG2; the inverting control terminal of the transmission gate TG2 inputs the inverted clock signal, and the positive control terminal inputs the positive clock signal; The output end of the transmission gate TG3 is respectively connected to the first input end of the NOR gate NOR2 and the output end of the transmission gate TG4, the inverting control end is input with the inverting clock signal, and the positive control end is input with the positive clock signal; the second input end of the NOR gate NOR2 is input with the reset signal, and the output end is connected to the first input end of the NOR gate NOR4 and serves as the output end of the first trigger or the second trigger; The ground signal is input into the second input terminal of the NOR gate NOR4, and the output terminal is connected to the input terminal of the transmission gate TG4; the positive phase clock signal is input into the inverting control terminal of the transmission gate TG4, and the inverting clock signal is input into the positive phase control terminal.

9. The three-channel randomization circuit applied to a three-channel interleaved sampling front end according to claim 1, characterized in that: Each of the sampling and holding channels includes: a MOS tube M4 and a capacitor C1; The drain of the MOS tube M4 inputs the external sampling signal, the gate inputs the channel enable signal, the source is connected to the first plate of the capacitor C1, and outputs a sampling and holding signal; the second plate of the capacitor C1 is connected to the ground.

10. The three-channel randomization circuit applied to a three-channel interleaved sampling front end according to claim 1, characterized in that: The channel selection circuit (400) comprises: a transmission gate TG5, a transmission gate TG6 and a transmission gate TG7; The first ends of the transmission gate TG5, the transmission gate TG6 and the transmission gate TG7 are respectively connected to the output ends of the three sampling and holding channels, and the holding signals are respectively inputted, the inverting control ends are respectively inputted with inverting selection signals, and the positive control ends are respectively inputted with positive selection signals, and the output ends are connected to each other and serve as the output ends of the channel selection circuit (400).

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