Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor capable of improving both moisture resistance and high-temperature reliability. In a laminated ceramic capacitor (1) according to the present embodiment, in a laminated body (10), effective layer sections (11E) in which a plurality of internal electrode layers (30) face each other in a height direction (T) include a first side surface-side effective layer section (11E1), a second side surface-side effective layer section (11E2), and a central section-side effective layer section (11EC). The average thickness in the height direction (T) of the dielectric layer (20) inside the first side surface-side effective layer section (11E1) and the second side surface-side effective layer section (11E2) is smaller than the average thickness in the height direction (T) of the dielectric layer (20) inside the central section-side effective layer section (11EC). The average particle diameter of the ceramic material in the dielectric layer (20) inside the first side surface-side active layer section (11E1) and the second side surface-side active layer section (11E2) is larger than the average particle diameter of the ceramic material in the dielectric layer (20) inside the central section-side active layer section (11EC).

Description

Technical Field

[0001] The present invention relates to a laminated ceramic capacitor. Background Art

[0002] In the past, there are known laminated ceramic capacitors. Generally, laminated ceramic capacitors include a ceramic sintered body containing a dielectric ceramic such as barium titanate. A plurality of internal electrodes are arranged inside the ceramic sintered body so as to overlap each other with ceramic layers interposed therebetween. In addition, external electrodes are formed on one end face and the other end face of the ceramic sintered body so as to be electrically connected to the internal electrodes (for example, Patent Document 1).

[0003] Prior Art Literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 8-306580 Summary of the invention

[0006] Problem that the invention aims to solve

[0007] However, various measures are being taken for multilayer ceramic capacitors to ensure high temperature reliability, such as moisture resistance to steam or the like and performance that satisfies requirements even under high temperature loads, in order to further improve performance.

[0008] An object of the present invention is to provide a multilayer ceramic capacitor capable of improving both moisture resistance and high-temperature reliability.

[0009] Technical solutions to solve problems

[0010] The multilayer ceramic capacitor of the present invention has a multilayer body, which includes a plurality of stacked dielectric layers and a plurality of stacked internal electrode layers, and includes a first main surface and a second main surface opposite to each other in a height direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the height direction and the width direction, and is constituted by an effective layer portion in which the plurality of internal electrode layers are opposed to each other in the height direction with the dielectric layer therebetween, wherein the dielectric layer includes a ceramic material, the effective layer portion includes a first side surface side edge extending in the height direction on the first side surface, and a second side surface side edge extending in the height direction on the second side surface, and includes a first side surface side edge extending in the height direction from the first side surface side edge along the width direction toward the effective layer portion. The first side effective layer portion including the area inside the effective layer portion, the second side effective layer portion including the area from the second side edge along the width direction toward the inside of the effective layer portion, and the central part side effective layer portion including the area near the center of the effective layer portion in the width direction, the average thickness in the height direction of the dielectric layer existing in the first side effective layer portion and the second side effective layer portion is thinner than the average thickness in the height direction of the dielectric layer existing in the central part side effective layer portion, and the average grain size of the ceramic material in the dielectric layer existing in the first side effective layer portion and the second side effective layer portion is larger than the average grain size of the ceramic material in the dielectric layer existing in the central part side effective layer portion.

[0011] Effects of the Invention

[0012] According to the present invention, it is possible to provide a multilayer ceramic capacitor capable of improving both moisture resistance and high-temperature reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a perspective view of the appearance of a multilayer ceramic capacitor according to an embodiment.

[0014] Figure 2 It is along Figure 1 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor taken along line II-II shown in FIG.

[0015] Figure 3 It is along Figure 2 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor taken along line III-III.

[0016] Figure 4 It is along Figure 2 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor taken along line IV-IV shown in FIG.

[0017] Figure 5This is an example of an enlarged image of a cross section of an exposed effective layer portion.

[0018] Figure 6 FIG. 1 is a diagram showing a dual-structured multilayer ceramic capacitor. DETAILED DESCRIPTION

[0019] Hereinafter, a multilayer ceramic capacitor 1 according to an embodiment of the present disclosure will be described. Figure 1 It is a perspective view of the appearance of the multilayer ceramic capacitor 1 according to the present embodiment. Figure 2 It is along Figure 1 A cross-sectional view of the multilayer ceramic capacitor 1 taken along line II-II. Figure 3 It is along Figure 2 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line III-III. Figure 4 It is along Figure 2 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line IV-IV.

[0020] The multilayer ceramic capacitor 1 includes a multilayer body 10 and external electrodes 40 .

[0021] exist Figure 1 to Figure 4 , an XYZ orthogonal coordinate system is shown. The length direction L of the laminated ceramic capacitor 1 and the laminated body 10 corresponds to the X direction. The width direction W of the laminated ceramic capacitor 1 and the laminated body 10 corresponds to the Y direction. The height direction T of the laminated ceramic capacitor 1 and the laminated body 10 corresponds to the Z direction. Here, Figure 2 The section shown is also referred to as the LT section. Figure 3 The section shown is also referred to as the WT section. Figure 4 The section shown is also referred to as the LW section.

[0022] like Figure 1 to Figure 4 As shown, the stack 10 includes a first main surface TS1 and a second main surface TS2 opposite to each other in a height direction T, a first side surface WS1 and a second side surface WS2 opposite to each other in a width direction W perpendicular to the height direction T, and a first end surface LS1 and a second end surface LS2 opposite to each other in a length direction L perpendicular to the height direction T and the width direction W.

[0023] like Figure 1 As shown, the laminate 10 has a substantially rectangular parallelepiped shape. In addition, the dimension of the length direction L of the laminate 10 is not necessarily longer than the dimension of the width direction W. It is preferred that the corners and ridges of the laminate 10 are rounded. The corner is the portion where three faces of the laminate intersect, and the ridge is the portion where two faces of the laminate intersect. In addition, a part or all of the surface constituting the laminate 10 may be formed with concavities and convexities.

[0024] like Figure 2 as well as Figure 3As shown, the laminate 10 includes an inner layer portion 11 , and a first main surface side outer layer portion 12 and a second main surface side outer layer portion 13 arranged in the height direction T so as to sandwich the inner layer portion 11 .

[0025] The inner layer portion 11 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30. The inner layer portion 11 includes the internal electrode layer 30 located closest to the first main surface TS1 side to the internal electrode layer 30 located closest to the second main surface TS2 side in the height direction T. In the inner layer portion 11, the plurality of internal electrode layers 30 are arranged opposite to each other with the dielectric layer 20 interposed therebetween. The inner layer portion 11 is a portion that generates electrostatic capacitance and substantially functions as a capacitor.

[0026] The plurality of dielectric layers 20 are composed of dielectric materials. Preferably, the ceramic material in the dielectric layer comprises a perovskite structure, the perovskite structure comprising Ba, Sr, Zr, Ti, Hf, Si, and optionally Ca, the molar number of Sr / (molar number of Ba+molar number of Ca+molar number of Sr) being 0.6 to 0.95, and the molar number of Zr / (molar number of Zr+molar number of Ti+molar number of Hf) being 0.9 to 0.98.

[0027] By selecting the above-mentioned material and composition, there is an advantage in that good temperature characteristics can be ensured.

[0028] In addition, it is further preferred that the ceramic material in the dielectric layer includes a perovskite structure, which contains Ba, Sr, Zr, Ti, Hf, Si, and optionally contains Ca, and (molar number of Ba + molar number of Ca + molar number of Sr) / (molar number of Zr + molar number of Ti + molar number of Hf) is greater than 1.00 and less than 1.03.

[0029] By selecting the above-mentioned materials and composition, there is a further advantage that oxygen defects in the dielectric can be suppressed during firing in a reducing atmosphere, thereby improving reliability.

[0030] The thickness of the dielectric layer 20 is preferably 0.7 μm or more and 2.5 μm or less. The number of laminated dielectric layers 20 is preferably 10 or more and 1500 or less. The number of dielectric layers 20 is the sum of the number of dielectric layers of the inner layer portion 11 and the number of dielectric layers of the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0031] The plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32. The plurality of first internal electrode layers 31 are arranged on the plurality of dielectric layers 20. The plurality of second internal electrode layers 32 are arranged on the plurality of dielectric layers 20. The plurality of first internal electrode layers 31 and the plurality of second internal electrode layers 32 are alternately arranged in the height direction T of the laminate 10 with the dielectric layers 20 interposed therebetween. The first internal electrode layers 31 and the second internal electrode layers 32 are arranged so as to sandwich the dielectric layer 20.

[0032] The first internal electrode layer 31 includes a first opposing portion 31A opposing the second internal electrode layer 32 and a first lead portion 31B led out from the first opposing portion 31A to the first end surface LS1. The first lead portion 31B is exposed at the first end surface LS1.

[0033] The second internal electrode layer 32 includes a second opposing portion 32A opposing the first internal electrode layer 31 and a second lead portion 32B led out from the second opposing portion 32A to the second end surface LS2. The second lead portion 32B is exposed at the second end surface LS2.

[0034] In the present embodiment, the first opposing portion 31A and the second opposing portion 32A are opposed to each other via the dielectric layer 20 , thereby forming capacitance and exhibiting capacitor characteristics.

[0035] The shapes of the first opposing portion 31A and the second opposing portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed obliquely. The shapes of the first lead-out portion 31B and the second lead-out portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed obliquely.

[0036] The dimension of the first opposing portion 31A in the width direction W and the dimension of the first lead portion 31B in the width direction W may be formed to be the same dimension, or one of the dimensions may be formed to be smaller. The dimension of the second opposing portion 32A in the width direction W and the dimension of the second lead portion 32B in the width direction W may be formed to be the same dimension, or one of the dimensions may be formed to be smaller.

[0037] The first internal electrode layer 31 and the second internal electrode layer 32 are made of a suitable conductive material such as a metal such as Ni, Cu, Ag, Pd, Au, or an alloy containing at least one of these metals. When an alloy is used, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0038] The thickness of each of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably about 0.2 μm or more and 1.5 μm or less, for example. The total number of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably 10 or more and 1500 or less.

[0039] In addition, Sn may be disposed at the interface between the first internal electrode layer and the dielectric layer, and at the interface between the second internal electrode layer and the dielectric layer. In addition, Sn may be in a layered form or may be dispersed. In addition, Sn may be dissolved in the internal electrode side or in the dielectric particles on the dielectric layer side.

[0040] The first main surface side outer layer portion 12 is located on the first main surface TS1 side of the stacked body 10. The first main surface side outer layer portion 12 is an aggregate of a plurality of dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. The dielectric layer 20 used in the first main surface side outer layer portion 12 may be the same as the dielectric layer 20 used in the internal layer portion 11.

[0041] The second main surface side outer layer portion 13 is located on the second main surface TS2 side of the stacked body 10. The second main surface side outer layer portion 13 is an aggregate of a plurality of dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layer 20 used in the second main surface side outer layer portion 13 may be the same as the dielectric layer 20 used in the internal layer portion 11.

[0042] Thus, the laminated body 10 includes a plurality of laminated dielectric layers 20 and a plurality of internal electrode layers 30 laminated on the dielectric layers 20. That is, the laminated ceramic capacitor 1 includes the laminated body 10 in which the dielectric layers 20 and the internal electrode layers 30 are alternately laminated.

[0043] The laminate 10 also includes an effective layer portion 11E. The effective layer portion 11E is a portion where the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 face each other. The effective layer portion 11E is configured as a part of the internal layer portion 11. Figure 4 , the range of the effective layer portion 11E in the width direction W and the length direction L is shown. The effective layer portion 11E is also referred to as a counter electrode portion or a capacitor effective portion. The details of the effective layer portion 11E will be described later.

[0044] In addition, the stacked body 10 has a side outer layer portion. The side outer layer portion has a first side outer layer portion WG1 and a second side outer layer portion WG2. The first side outer layer portion WG1 is a portion including the dielectric layer 20 located between the effective layer portion 11E and the first side WS1. The second side outer layer portion WG2 is a portion including the dielectric layer 20 located between the effective layer portion 11E and the second side WS2. Figure 3 , Figure 4 , the range of the first side outer layer portion WG1 and the second side outer layer portion WG2 in the width direction W is shown. In addition, the side outer layer portion is also called a W gap or a side gap.

[0045] In addition, the stacked body 10 has an end face side outer layer portion. The end face side outer layer portion has a first end face side outer layer portion LG1 and a second end face side outer layer portion LG2. The first end face side outer layer portion LG1 is a portion including the dielectric layer 20 located between the effective layer portion 11E and the first end face LS1. The second end face side outer layer portion LG2 is a portion including the dielectric layer 20 located between the effective layer portion 11E and the second end face LS2. Figure 2 , Figure 4 , the range of the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2 in the length direction L is shown. In addition, the end surface side outer layer portion is also called an L gap or an end gap.

[0046] The external electrode 40 includes a first external electrode 40A disposed on the first end surface LS1 side and a second external electrode 40B disposed on the second end surface LS2 side.

[0047] The first external electrode 40A is arranged on the first end surface LS1. The first external electrode 40A is connected to the first internal electrode layer 31. The first external electrode 40A may also be arranged on a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2. In the present embodiment, the first external electrode 40A is formed to extend from the first end surface LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0048] The second external electrode 40B is arranged on the second end surface LS2. The second external electrode 40B is connected to the second internal electrode layer 32. The second external electrode 40B may also be arranged on a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2. In the present embodiment, the second external electrode 40B is formed to extend from the second end surface LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0049] As described above, in the laminate 10, the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 are opposed to each other via the dielectric layer 20, thereby forming a capacitor. Therefore, the first external electrode 40A connected to the first internal electrode layer 31 and the second external electrode 40B connected to the second internal electrode layer 32 exhibit capacitor characteristics.

[0050] The first external electrode 40A includes a first foundation electrode layer 50A and a first plating layer 60A disposed on the first foundation electrode layer 50A.

[0051] The second external electrode 40B includes a second foundation electrode layer 50B and a second plating layer 60B disposed on the second foundation electrode layer 50B.

[0052] The first foundation electrode layer 50A is arranged on the first end surface LS1. The first foundation electrode layer 50A is connected to the first internal electrode layer 31. In the present embodiment, the first foundation electrode layer 50A is formed to extend from the first end surface LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0053] The second base electrode layer 50B is arranged on the second end surface LS2. The second base electrode layer 50B is connected to the second internal electrode layer 32. In the present embodiment, the second base electrode layer 50B is formed to extend from the second end surface LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2. In addition, the first base electrode layer may be arranged only on the surface of the first end surface of the stack, and the second base electrode layer may be arranged only on the surface of the second end surface of the stack.

[0054] The first base electrode layer 50A and the second base electrode layer 50B of the present embodiment are sintered layers. The sintered layers preferably contain a metal component and a glass component. The metal component, for example, contains at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The glass component, for example, contains at least one selected from B, Si, Ba, Mg, Al, Li, etc.

[0055] The sintered layer is, for example, a sintered layer obtained by applying a conductive paste containing glass and metal to the laminate and sintering it. The sintered layer may be a sintered layer obtained by simultaneously sintering a laminated chip having an internal electrode and a dielectric layer and a conductive paste applied to the laminated chip, or a sintered layer obtained by sintering a laminated chip having an internal electrode and a dielectric layer and then applying a conductive paste to the laminate and sintering it. In addition, when the laminated chip having an internal electrode and a dielectric layer and the conductive paste applied to the laminated chip are sintered simultaneously, the sintered layer is preferably formed by sintering a paste to which a dielectric material is added instead of a glass component. The sintered layer may also be a multilayer.

[0056] The thickness of the first foundation electrode layer 50A located at the first end surface LS1 in the length direction L is preferably about 3 μm or more and 160 μm or less in the center portion in the height direction T and the width direction W of the first foundation electrode layer 50A, for example.

[0057] The thickness of the second foundation electrode layer 50B located at the second end surface LS2 in the longitudinal direction L is preferably about 3 μm or more and 160 μm or less in the central portion in the height direction T and the width direction W of the second foundation electrode layer 50B, for example.

[0058] When the first base electrode layer 50A is also provided on a portion of at least one surface of the first main surface TS1 or the second main surface TS2, the thickness of the first base electrode layer 50A provided on the portion in the height direction T is preferably, for example, greater than 3 μm and less than 40 μm in the central portion in the length direction L and the width direction W of the first base electrode layer 50A provided on the portion.

[0059] When the first base electrode layer 50A is also provided on a portion of at least one surface of the first side surface WS1 or the second side surface WS2, the thickness in the width direction W of the first base electrode layer 50A provided on the portion is preferably, for example, greater than 3 μm and less than 40 μm in the central portion in the length direction L and the height direction T of the first base electrode layer 50A provided on the portion.

[0060] When a second base electrode layer 50B is also provided on a portion of at least one surface of the first main surface TS1 or the second main surface TS2, the thickness of the second base electrode layer 50B provided on the portion in the height direction T is preferably, for example, greater than 3 μm and less than 40 μm in the central portion in the length direction L and the width direction W of the second base electrode layer 50B provided on the portion.

[0061] When the second base electrode layer 50B is also provided on a portion of at least one surface of the first side surface WS1 or the second side surface WS2, the thickness in the width direction W of the second base electrode layer 50B provided on the portion is preferably, for example, greater than 3 μm and less than 40 μm in the central portion in the length direction L and the height direction T of the second base electrode layer 50B provided on the portion.

[0062] In addition, the first base electrode layer 50A and the second base electrode layer 50B are not limited to sintered layers. The first base electrode layer 50A and the second base electrode layer 50B include at least one selected from a sintered layer, a conductive resin layer, a thin film layer, etc. For example, the first base electrode layer 50A and the second base electrode layer 50B may also be a thin film layer. The thin film layer is formed by a thin film forming method such as a sputtering method or a vapor deposition method. The thin film layer is a layer of less than 1 μm on which metal particles are deposited.

[0063] The first plating layer 60A is arranged to cover the first base electrode layer 50A.

[0064] The second plating layer 60B is arranged to cover the second base electrode layer 50B.

[0065] The first plating layer 60A and the second plating layer 60B may include, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc. The first plating layer 60A and the second plating layer 60B may also be formed of multiple layers. The first plating layer 60A and the second plating layer 60B are preferably a two-layer structure in which a Sn plating layer is formed on a Ni plating layer.

[0066] In the present embodiment, the first plating layer 60A includes a first Ni plating layer 61A and a first Sn plating layer 62A located on the first Ni plating layer 61A.

[0067] In the present embodiment, the second plating layer 60B includes a second Ni plating layer 61B and a second Sn plating layer 62B located on the second Ni plating layer 61B.

[0068] The Ni plating layer prevents the first base electrode layer 50A and the second base electrode layer 50B from being corroded by the solder when mounting the multilayer ceramic capacitor 1. In addition, the Sn plating layer improves the wettability of the solder when mounting the multilayer ceramic capacitor 1. Thus, the mounting of the multilayer ceramic capacitor 1 becomes easy. The thickness of each of the first Ni plating layer 61A, the first Sn plating layer 62A, the second Ni plating layer 61B, and the second Sn plating layer 62B is preferably 2 μm or more and 15 μm or less.

[0069] In addition, the first external electrode 40A and the second external electrode 40B of the present embodiment may also have a conductive resin layer containing conductive particles and a thermosetting resin, for example. When a conductive resin layer is provided as a base electrode layer (the first base electrode layer 50A, the second base electrode layer 50B), the conductive resin layer may be configured to cover the sintered layer, or may be directly provided on the laminate 10 without providing the sintered layer. When the conductive resin layer is configured to cover the sintered layer, the conductive resin layer is provided between the sintered layer and the plating layer (the first plating layer 60A, the second plating layer 60B). The conductive resin layer may completely cover the sintered layer, or may cover a portion of the sintered layer.

[0070] The conductive resin layer including a thermosetting resin is more flexible than, for example, a conductive layer including a plated film or a fired product of a conductive paste. Therefore, even when a physical impact or an impact caused by a thermal cycle is applied to the multilayer ceramic capacitor 1, the conductive resin layer functions as a buffer layer. Therefore, the conductive resin layer suppresses cracks in the multilayer ceramic capacitor 1.

[0071] The metal constituting the conductive particles may also be Ag, Cu, Ni, Sn, Bi or an alloy containing them. The conductive particles preferably contain Ag. The conductive particles are, for example, Ag metal powder. Ag has the lowest resistivity among metals and is therefore suitable for electrode materials. In addition, Ag is a noble metal and is therefore not easily oxidized and has high weather resistance. Therefore, Ag metal powder is suitable as the conductive particles.

[0072] In addition, the conductive particles may be metal powders coated with Ag on the surface of the metal powders. When using metal powders coated with Ag on the surface of the metal powders, the metal powders are preferably Cu, Ni, Sn, Bi or alloy powders thereof. In order to make the metal of the base material a cheap metal while maintaining the characteristics of Ag, it is preferred to use metal powders coated with Ag.

[0073] Furthermore, the conductive particles may be conductive particles in which Cu and Ni have been subjected to an oxidation prevention treatment. In addition, the conductive particles may be metal powders in which Sn, Ni, and Cu are coated on the surface of the metal powder. When a metal powder in which Sn, Ni, and Cu are coated on the surface of the metal powder is used, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy powder thereof.

[0074] The shape of the conductive particles is not particularly limited. The conductive particles may be spherical or flat, but preferably, a mixture of spherical metal powder and flat metal powder is used.

[0075] The conductive particles contained in the conductive resin layer mainly play a role in ensuring the conductivity of the conductive resin layer. Specifically, a plurality of conductive particles are in contact with each other, thereby forming a conductive path inside the conductive resin layer.

[0076] The resin constituting the conductive resin layer may also include at least one selected from various known thermosetting resins such as epoxy resin, phenolic resin, polyurethane resin, silicone resin, polyimide resin, etc. Among them, epoxy resin having excellent heat resistance, moisture resistance, adhesion, etc. is one of the most suitable resins. In addition, the resin of the conductive resin layer preferably includes a curing agent together with the thermosetting resin. When epoxy resin is used as the base resin, the curing agent of the epoxy resin may also be various known compounds such as phenolic, amine, anhydride, imidazole, active ester, and amide-imide.

[0077] The conductive resin layer may be formed of a plurality of layers. The thickness of the thickest portion of the conductive resin layer is preferably 10 μm or more and 150 μm or less.

[0078] Alternatively, the following structure may be adopted, that is, instead of providing the first base electrode layer 50A and the second base electrode layer 50B, the first plated layer 60A and the second plated layer 60B described later may be directly disposed on the laminate 10. That is, the laminated ceramic capacitor 1 may also have a structure including a plated layer that is directly electrically connected to the first internal electrode layer 31 and the second internal electrode layer 32. In such a case, the plated layer may be formed after a catalyst is disposed on the surface of the laminate 10 as a pretreatment.

[0079] In this case, the plating layer is also preferably a multilayer. The lower plating layer and the upper plating layer are preferably respectively, for example, preferably containing at least one metal selected from Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi or Zn, or an alloy containing these metals. The lower plating layer is more preferably formed using Ni with solder resistance. The upper plating layer is more preferably formed using Sn or Au with good solder wettability. In addition, for example, when Ni is used to form the first internal electrode layer 31 and the second internal electrode layer 32, the lower plating layer is preferably formed using Cu with good bonding properties with Ni. In addition, the upper plating layer can be formed as needed, and the external electrode 40 can also be composed of only the lower plating layer. In addition, the plating layer can use the upper plating layer as the outermost layer, and other plating layers can also be further formed on the surface of the upper plating layer.

[0080] The thickness of each plating layer disposed without providing a base electrode layer is preferably 1 μm or more and 15 μm or less. In addition, the plating layer preferably does not contain glass. The metal ratio per unit volume of the plating layer is preferably 99 volume % or more.

[0081] In addition, when the plating layer is directly formed on the laminated body 10, the thickness of the base electrode layer can be reduced. Therefore, the dimension of the height direction T of the laminated ceramic capacitor 1 can be reduced in accordance with the reduction of the thickness of the base electrode layer, thereby seeking to reduce the height of the laminated ceramic capacitor 1. Alternatively, the thickness of the dielectric layer 20 sandwiched between the first internal electrode layer 31 and the second internal electrode layer 32 can be increased in accordance with the reduction of the thickness of the base electrode layer, thereby seeking to increase the thickness of the body. In this way, by directly forming the plating layer on the laminated body 10, the degree of freedom in design of the laminated ceramic capacitor can be improved.

[0082] In addition, if the dimension in the length direction of the multilayer ceramic capacitor 1 including the stacked body 10 and the external electrode 40 is set to L dimension, the L dimension is preferably 0.2 mm or more and 3.6 mm or less. In addition, if the dimension in the height direction of the multilayer ceramic capacitor 1 is set to T dimension, the T dimension is preferably 0.1 mm or more and 2.6 mm or less. In addition, if the dimension in the width direction of the multilayer ceramic capacitor 1 is set to W dimension, the W dimension is preferably 0.1 mm or more and 2.6 mm or less.

[0083] Next, the details of the effective layer portion 11E will be described. Figure 3 As shown, the effective layer portion 11E includes a first side edge 11ES1 and a second side edge 11ES2. The first side edge 11ES1 extends in the height direction T on the first side WS1 side along the end of the first side WS1 side of the plurality of internal electrode layers 30. The second side edge 11ES2 extends in the height direction T on the second side WS2 side along the end of the second side WS2 side of the plurality of internal electrode layers 30.

[0084] In addition, the effective layer portion 11E includes a first side effective layer portion 11E1, a second side effective layer portion 11E2, and a center effective layer portion 11EC. The first side effective layer portion 11E1 is a region of the effective layer portion 11E extending from the first side edge 11ES1 along the width direction W toward the inside of the effective layer portion 11E. The second side effective layer portion 11E2 is a region of the effective layer portion 11E extending from the second side edge 11ES2 along the width direction W toward the inside of the effective layer portion 11E. The center effective layer portion 11EC is a region near the center of the effective layer portion 11E in the width direction W.

[0085] Here, among the plurality of dielectric layers 20, the thickness of the dielectric layer 20 in the height direction T existing inside the first side effective layer portion 11E1 and the second side effective layer portion 11E2 is thinner than the thickness of the dielectric layer 20 in the height direction T existing inside the center side effective layer portion 11EC. That is, the first side effective layer portion 11E1 and the second side effective layer portion 11E2 (hereinafter also collectively referred to as side effective layer portions) are portions where the thickness of the dielectric layer 20 in the height direction T existing inside them is thinner than the thickness of the dielectric layer 20 in the height direction T existing inside the center side effective layer portion 11EC.

[0086] The thickness of the dielectric layer 20 in the height direction T is continuously thinned in the first side effective layer portion 11E1 along the width direction W from the boundary with the center side effective layer portion 11EC toward the first side side edge 11ES1. The thickness of the dielectric layer 20 in the height direction T is continuously thinned in the second side effective layer portion 11E2 along the width direction W from the boundary with the center side effective layer portion 11EC toward the second side side edge 11ES2. The region where the thickness of the dielectric layer 20 in the height direction T is continuously thinned is preferably arranged inside the effective layer portion 11E in the width direction W at a distance of 1% or more and 17% or less from the first side side edge 11ES1 and the second side side edge 11ES2 relative to the dimension of the effective layer portion 11E in the width direction W.

[0087] As a result, the dielectric layer, internal electrode, and outer layer near the side effective layer are appropriately compressed, and the compactness of the side effective layer can be improved. Therefore, it is possible to suppress the infiltration of moisture into the laminate 10. As a result, the moisture resistance reliability of the laminated ceramic capacitor 1 can be improved.

[0088] The dimensions of the first side effective layer portion 11E1 and the second side effective layer portion 11E2 in the width direction W are preferably 1% or more and 17% or less relative to the dimension of the effective layer portion 11E in the width direction W. The dimensions of the first side effective layer portion 11E1 and the second side effective layer portion 11E2 in the width direction W are more preferably 1% or more and 6% or less relative to the dimension of the effective layer portion 11E in the width direction W.

[0089] As long as it is within the above range, a range in which the dielectric layer is thin can be appropriately ensured, and moisture resistance reliability can be ensured.

[0090] The grain size of the ceramic material in the dielectric layer 20 existing in the first-side effective layer portion 11E1 and the second-side effective layer portion 11E2 is larger than the grain size of the ceramic material in the dielectric layer existing in the center-side effective layer portion 11EC.

[0091] The ratio of the minimum thickness in the height direction T of the dielectric layer 20 existing inside the first side effective layer portion 11E1 and the second side effective layer portion 11E2 to the maximum particle size of the ceramic material in the dielectric layer 20 existing inside the first side effective layer portion 11E1 and the second side effective layer portion 11E2 is preferably 0.83 or more and 1.82 or less. In addition, the above-mentioned maximum particle size is set to a value calculated using the "average value + 3σ" of the particle sizes of multiple ceramic particles measured by the method described later. The above-mentioned minimum thickness is set to a value calculated using the "average value - 3σ" of the thickness of the dielectric layer 20 measured by the method described later.

[0092] With the above configuration, the number of particles in one dielectric layer 20 in the side effective layer portion can be appropriately ensured, and the electric field distribution in the layer of the side effective layer portion can be further uniformed. As a result, high temperature reliability can be further improved.

[0093] If the ratio of the minimum thickness in the height direction T of the dielectric layer 20 existing inside the side effective layer portion to the maximum particle size of the ceramic material in the dielectric layer 20 existing inside the side effective layer portion becomes less than 0.83, the number of particles in one dielectric layer 20 in the side effective layer portion cannot be ensured, the electric field distribution in the layer of the side effective layer portion becomes uneven, and sometimes the high temperature reliability decreases. In addition, when the above ratio is set to 1.82 or more, the thickness of the dielectric layer must be thickened, so the electrostatic capacitance decreases accordingly.

[0094] <Method for measuring particle size and dielectric layer thickness>

[0095] The following describes a method for measuring the particle size and the thickness of the dielectric layer 20 in this embodiment. The particle size of the ceramic particles of the ceramic material in the dielectric layer 20 and the thickness of the dielectric layer 20 are measured based on observation using a SEM (scanning electron microscope).

[0096] First, the measurement target portion is described. The SEM observation for measurement is performed on a WT cross section approximately parallel to the first end surface LS1 and the second end surface LS2 at a position approximately in the center in the length direction L of the effective layer portion 11E. The SEM observation of the effective layer portion 11EC on the central side is performed as follows: Figure 3 The position of P1 in the WT cross section shown in FIG. 1 is carried out with respect to the center of the effective layer portion 11E in the height direction T and the center in the width direction W. The SEM observation of the first side effective layer portion 11E1 and the second side effective layer portion 11E2 is shown in FIG. Figure 3More specifically, the positions of P2A and P2B in the WT cross section shown in FIG. 1 are implemented with respect to the center in the height direction T and the center in the width direction W of the first-side effective layer portion 11E1 and the second-side effective layer portion 11E2 .

[0097] The method for measuring the average particle size and the maximum particle size of the ceramic material is described. The stacked ceramic capacitor 1 is broken at a position approximately in the center in the length direction L with pliers to expose the WT cross section of the stack 10. Then, the fracture surface is heat treated at 1000°C for 30 minutes, and pre-treated to make it easy to observe the particle size. After being treated by the above method, the measurement object part is photographed at a high magnification of 20,000 times using FE-SEM. The outer edge of the particle is depicted by the image captured by the analysis software, the particle size is measured and the average value is calculated, and this value is set as the average particle size. The maximum particle size is calculated using the "average value + 3σ" of the measured value. For the central side effective layer part 11EC, these values ​​are calculated using the image data of the position of the above-mentioned measurement object part P1. For the first side side effective layer part 11E1 and the second side side effective layer part 11E2 (side side effective layer part), these values ​​are calculated using the two image data at the positions of the above-mentioned measurement object parts P2A and P2B.

[0098] The following describes a method for measuring the average thickness and the minimum thickness in the height direction T of the dielectric layer 20. The laminate 10 is reinforced with resin and polished so that a WT cross section substantially parallel to the first end face LS1 and the second end face LS2 is exposed. Then, the measurement target portion in the WT cross section of the polished laminate 10 is photographed at a magnification of 5000 times using an SEM.

[0099] The thicknesses of ten dielectric layers 20 (ten cross sections of the dielectric layers 20 ) and ten internal electrode layers 30 (ten cross sections of the internal electrode layers 30 ) on the captured image were measured, and the average value was calculated.

[0100] Below, using Figure 5 The method for measuring the thickness of the dielectric layer 20 is described in detail. In addition, the method for measuring the thickness of the dielectric layer 20 at the measurement target sites P1, P2A, and P2B is the same, so only the measurement of P1 is described as a representative. Here, the case of measuring the thickness of the internal electrode layer 30 in addition to the thickness of the dielectric layer 20 is described.

[0101] The thickness of the internal electrode layer 30 is measured in the following manner. Figure 5This is an example of an enlarged image of the exposed effective layer section at the position of the measurement target site P1. In the enlarged image shown in the figure, for example, a plurality of straight lines La, Lb, Lc, Ld, and Le extending in the height direction T (stacking direction T) are drawn at approximately equal intervals S. The interval S is preferably about 5 to 10 times the thickness of the internal electrode layer 30 to be measured. For example, when measuring an internal electrode layer 30 having a thickness of about 1 μm, the interval S is set to 5 μm.

[0102] Next, the thickness d1, d2, d3, d4, and d5 of each internal electrode layer 30 is measured on each of the five straight lines La, Lb, Lc, Ld, and Le, and the average value thereof is taken as the thickness of one internal electrode layer 30 in the height direction T. However, in the case where an internal electrode layer 30 is missing on the straight lines La, Lb, Lc, Ld, and Le and the dielectric layers 20 sandwiching the internal electrode layer 30 are connected to each other, or in the case where the enlarged view of the measurement position is unclear, a new straight line is drawn to measure the thickness of the internal electrode layer 30. This operation is performed for 10 internal electrode layers 30, and the average value thereof is taken as the average thickness of the internal electrode layer 30 in the height direction T of the present embodiment.

[0103] In addition, the thickness of the dielectric layer 20 is also measured by the same method as the internal electrode layer 30. The thickness D1, D2, D3, D4, and D5 of each dielectric layer 20 are measured on each of the five straight lines La, Lb, Lc, Ld, and Le, and the average value thereof is used as the thickness of one dielectric layer 20. This operation is performed on 10 dielectric layers 20, and the average value thereof is used as the average thickness in the height direction T of the dielectric layer 20 of this embodiment. The minimum thickness in the height direction T of the dielectric layer 20 is calculated by "average value-3σ". For the central side effective layer portion 11EC, these values ​​are calculated using the data of the thickness of 10 dielectric layers at the position of the above-mentioned measurement object site P1. For the first side side effective layer portion 11E1 and the second side side effective layer portion 11E2 (side side effective layer portion), these values ​​are calculated using the data of the thickness of a total of 20 dielectric layers at the positions of the above-mentioned measurement object sites P2A and P2B.

[0104] Next, a method for manufacturing the multilayer ceramic capacitor 1 according to the present embodiment will be described.

[0105] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet and the conductive paste for the internal electrode contain a binder and a solvent. The binder and the solvent may be known binders and solvents.

[0106] On the dielectric sheet, a conductive paste for the internal electrode layer 30 is printed in a predetermined pattern by, for example, screen printing or gravure printing. Thus, a dielectric sheet having a pattern of the first internal electrode layer 31 and a dielectric sheet having a pattern of the second internal electrode layer 32 are prepared.

[0107] By stacking a predetermined number of dielectric sheets on which the pattern of the internal electrode layer is not printed, a portion of the first main surface side outer layer portion 12 on the first main surface TS1 side is formed. By stacking a dielectric sheet on which the pattern of the first internal electrode layer 31 is printed and a dielectric sheet on which the pattern of the second internal electrode layer 32 is printed in sequence, a portion of the inner layer portion 11 is formed. By stacking a predetermined number of dielectric sheets on which the pattern of the internal electrode layer is not printed on the portion of the inner layer portion 11, a portion of the second main surface side outer layer portion 13 on the second main surface TS2 side is formed. In this way, a laminated sheet is produced.

[0108] The laminated sheets are pressed in the height direction T by means of isostatic pressing or the like, thereby making a laminated block. In the present embodiment, the thickness of the dielectric layer 20 on the side is relatively thinned. For example, the thickness and hardness of the rubber used in the isostatic pressing are adjusted to achieve the structure of the present application. Specifically, the thickness of the rubber used in the isostatic pressing is thickened. Alternatively, the hardness of the rubber used in the isostatic pressing is made harder than usual. Thus, the thickness of the dielectric layer 20 on the side is relatively thinned.

[0109] The stacked blocks are cut into predetermined sizes to produce stacked small pieces. At this time, the corners and ridges of the stacked small pieces may be rounded by barrel grinding or the like.

[0110] In the process of firing the stacked small pieces, there are a pre-calcination process and a formal calcination process. In the pre-calcination process, first, the stacked small pieces are placed on a firing placement device, and the binder contained in the stacked small pieces is heated and removed. Here, the ceramic green sheets as dielectric sheets of the stacked small pieces and the organic binder contained in the conductive paste for the internal electrode layer 30 are removed. The atmosphere in the furnace of the pre-calcination process is carried out in an air atmosphere, but the amount of gas such as N2, H2, H2O, etc. can be adjusted. The pre-calcination temperature at this time is preferably above 150°C and below 400°C.

[0111] Next, in the formal calcination process, the pre-calcined laminated small pieces placed on the sintering setting device are placed in the sintering furnace, and the temperature in the furnace is set to be above 600°C and below 1400°C for sintering. At this time, the heating rate is 1°C / min to 6000°C / min, and the particle size is adjusted. In addition, the amount of gas such as N2, H2, and H2O is adjusted in the furnace. In this way, a laminate can be obtained.

[0112] Here, in this embodiment, the stacked body 10 is produced by firing the stacked small pieces. In order to make the particles on the side relatively larger, the stacked small pieces are fired in a reducing atmosphere. For example, the oxygen partial pressure during firing is adjusted to achieve the structure of the present application. Specifically, the firing is performed in an atmosphere with a lower oxygen partial pressure than usual. As a result, the particles on the side that are in direct contact with the atmosphere with a lower oxygen partial pressure become relatively larger.

[0113] A conductive paste that becomes a base electrode layer (a first base electrode layer 50A and a second base electrode layer 50B) is applied to both end surfaces of the stack 10. Then, a sintering treatment is performed to form the base electrode layer. In the present embodiment, the base electrode layer is a sintered layer. For example, a conductive paste containing a glass component and a metal is applied to the stack 10 by a method such as dipping. Then, a sintering treatment is performed to form the base electrode layer. The temperature of the sintering treatment at this time is preferably above 700°C and below 900°C. In addition, when a sintered layer is used to form the base electrode layer, the sintered layer may also contain a ceramic component. In this case, the ceramic component may be contained instead of the glass component, or both.

[0114] At this time, as the added ceramic material, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20. In this case, it is preferable to apply a conductive paste to the stacked small pieces before firing, and to simultaneously fire the stacked small pieces and the conductive paste applied to the stacked small pieces to form the stacked body 10 having the fired layer formed thereon. The temperature of the firing treatment (firing temperature) at this time is preferably 900° C. or more and 1400° C. or less.

[0115] Then, a plating layer is formed on the surface of the base electrode layer. In the present embodiment, a first plating layer 60A is formed on the surface of the first base electrode layer 50A. In addition, a second plating layer 60B is formed on the surface of the second base electrode layer 50B. In the present embodiment, a Ni plating layer and a Sn plating layer are formed as plating layers. When performing the plating process, either electrolytic plating or electroless plating can also be used. However, regarding electroless plating, in order to increase the plating deposition speed, it is necessary to perform pretreatment using a catalyst, etc., so there is a disadvantage that the process is complicated. Therefore, it is usually preferred to use electrolytic plating. The Ni plating layer and the Sn plating layer are formed in sequence, for example, by roller plating.

[0116] In addition, when the base electrode layer is formed by a thin film layer, a thin film layer as the base electrode layer is formed in a portion where an external electrode is to be formed by masking, etc. The thin film layer is formed by a thin film forming method such as sputtering or evaporation. The thin film layer is a layer of 1.0 μm or less in which metal particles are deposited.

[0117] In addition, when a conductive resin layer is provided as a base electrode layer, the conductive resin layer can be configured to cover the sintered layer, or it can be directly configured on the laminate 10 without providing the sintered layer. When a conductive resin layer is provided, a conductive resin paste containing a thermosetting resin and a metal component is applied on the sintered layer or the laminate 10, and then heat-treated at a temperature of 250° C. to 550° C. or above. Thus, the thermosetting resin is heat-cured to form a conductive resin layer. The atmosphere during the heat treatment is preferably an N2 atmosphere. In addition, in order to prevent the scattering of the resin and to prevent the oxidation of various metal components, the oxygen concentration is preferably 100 ppm or less.

[0118] In addition, the base electrode layer may not be provided and the plating layer may be directly arranged on the exposed portion of the internal electrode layer 30 of the stack 10. In this case, the first end face LS1 and the second end face LS2 of the stack 10 are plated to form a plating layer on the exposed portion of the internal electrode layer 30. When the plating process is performed, any one of electrolytic plating and electroless plating may be used. However, regarding electroless plating, in order to increase the plating deposition speed, it is necessary to utilize a catalyst etc. for pretreatment, so there is a disadvantage that the process is complicated. Therefore, it is usually preferred to use electrolytic plating. As a plating method, it is preferred to use drum plating. In addition, it is also possible to form an upper plating layer by the same method as the lower plating layer as needed, and the upper plating layer is formed on the surface of the lower plating layer.

[0119] Through such manufacturing steps, the multilayer ceramic capacitor 1 can be manufactured.

[0120] <Example>

[0121] Using the manufacturing method involved in the above-mentioned embodiment, a laminated ceramic capacitor was produced as a sample of the embodiment. In the production of the sample of the embodiment, the thickness of the rubber used in the isostatic pressing was adjusted. Specifically, a rubber thicker than usual was used. In addition, in the production of the sample of the embodiment, the oxygen partial pressure during firing was adjusted. Specifically, firing was performed in an atmosphere with a lower oxygen partial pressure than usual. The specifications of the laminated ceramic capacitor are as follows.

[0122] ･Dimensions of multilayer ceramic capacitors: 1.68 mm (length direction L) × 0.87 mm (width direction W) × 0.88 mm (thickness direction T)

[0123] ･Ceramic material: SrBaZrO3

[0124] ･Capacitance: 100nF

[0125] ･Internal electrode material: Ni

[0126] Using the manufacturing method according to the above-described embodiment, laminated ceramic capacitors having specifications processed under the following conditions were produced as samples of comparative examples. The specifications of the laminated ceramic capacitors of Comparative Examples 1 and 2 are as follows.

[0127] Comparative Example 1: A rubber having a thickness thinner than usual was used. Furthermore, the calcination was performed in an atmosphere in which the oxygen partial pressure during calcination was higher than usual.

[0128] Comparative Example 2: A rubber having a thickness thinner than usual was used. Furthermore, the calcination was performed in an atmosphere in which the oxygen partial pressure during calcination was lower than usual.

[0129] ･Dimensions of multilayer ceramic capacitors: 1.68 mm (length direction L) × 0.87 mm (width direction W) × 0.88 mm (thickness direction T)

[0130] ･Ceramic material: SrBaZrO3

[0131] ･Capacitance: 100nF

[0132] ･Internal electrode: Ni

[0133] Next, the samples of the embodiments and comparative examples were subjected to a moisture resistance reliability test and a high temperature reliability test. In addition, 10 samples made in the same batch were used as objects, and the particle size of the ceramic material in the dielectric layer and the thickness of the dielectric layer were measured by the aforementioned measurement method. In addition, the measured values ​​of the particle size and thickness are the average values ​​of the 10 samples.

[0134] As a moisture resistance reliability test, a moisture resistance test of each sample was implemented based on the PCBT test method. In more detail, each sample was mounted on a wiring substrate using eutectic solder, and was placed in a high temperature and high humidity tank with a temperature of 125 [°C] and a relative humidity of 95 [% RH], and was set to a state where a DC current of 25 [V] was applied between a pair of external electrodes, and this state was maintained for 72 hours. Then, the case where the number of samples whose insulation resistance value did not drop by more than 2 digits before and after the test was 0 was judged as "○", and the case where the number of samples whose insulation resistance value dropped by more than 2 digits before and after the test was more than 20 was judged as "×". In addition, 36 samples were tested for each embodiment and each comparative example.

[0135] As a high-temperature reliability test, a high-temperature load test of each sample was implemented based on the HALT test method. In more detail, each sample was placed in a special fixture as a single unit, put into a high-temperature tank at a temperature of 150 [°C], and set to a state where a direct current of 100 [V] was applied between a pair of external electrodes, and this state was maintained for 100 hours. Then, the case where no failure occurred in the test was judged as "○", the case where 1 to 5 failures occurred in the test was judged as "△", and the case where more than 6 failures occurred in the test was judged as "×". In addition, 36 samples of each embodiment and each comparative example were tested.

[0136] The following summarizes the measurement data of the thickness of the dielectric layer and the grain size of the ceramic material in the dielectric layer, and the results of the moisture resistance reliability test and the high temperature reliability test for the samples of the examples and comparative examples.

[0137] [Table 1]

[0138]

[0139] According to the above results, the results of the humidity resistance reliability test of Examples 1 to 5, which are samples in which the average thickness A in the height direction T of the dielectric layer present in the side effective layer portion is thinner than the average thickness B in the height direction T of the dielectric layer present in the center effective layer portion, are good. On the other hand, the results of the humidity resistance reliability test of Comparative Examples 1 to 2, which are samples in which the average thickness A in the height direction T of the dielectric layer present in the side effective layer portion is thicker than the average thickness B in the height direction T of the dielectric layer present in the center effective layer portion, are not good.

[0140] In addition, the results of the high temperature reliability test were good for Examples 1 to 5, which were samples in which the average grain size C of the ceramic material in the dielectric layer present in the side effective layer portion was larger than the average grain size D of the ceramic material in the dielectric layer present in the center effective layer portion. On the other hand, the results of the high temperature reliability test were not good for Comparative Example 1, which was a large sample in which the average grain size C of the ceramic material in the dielectric layer present in the side effective layer portion was smaller than the average grain size D of the ceramic material in the dielectric layer present in the center effective layer portion.

[0141] In addition, Examples 2 to 5, which are samples in which the ratio E / F of the minimum thickness E in the height direction T of the dielectric layer present inside the side effective layer portion to the maximum particle size F of the ceramic material in the dielectric layer present inside the side effective layer portion is greater than 0.83 and less than 1.82, have better results in the high temperature reliability test than Example 1, which is a sample outside this range.

[0142] Based on the above, it can be seen that by making the average thickness of the dielectric layer existing inside the side effective layer portion in the height direction T thinner than the average thickness of the dielectric layer existing inside the center side effective layer portion and making the average particle size of the ceramic material in the dielectric layer existing inside the side effective layer portion larger than the average particle size of the ceramic material in the dielectric layer existing inside the center side effective layer portion, both moisture resistance and high temperature reliability can be improved.

[0143] Based on the above results, according to the multilayer ceramic capacitor 1 of the present embodiment, the following effects are achieved.

[0144] (1) A laminated ceramic capacitor 1 according to the present embodiment includes a laminated body 10, the laminated body 10 including a plurality of laminated dielectric layers 20 and a plurality of laminated internal electrode layers 30, the laminated body 10 including a first main surface TS1 and a second main surface TS2 opposing each other in a height direction T, a first side surface WS1 and a second side surface WS2 opposing each other in a width direction W orthogonal to the height direction T, and a first end surface LS1 and a second end surface LS2 opposing each other in a length direction L orthogonal to the height direction T and the width direction W, and an effective layer portion 11E in which the plurality of internal electrode layers 30 are opposed to each other in the height direction T with the dielectric layer 20 interposed therebetween, wherein the dielectric layer 20 includes a ceramic material, the effective layer portion 11E including a first side surface side edge 11ES1 extending in the height direction T on the first side surface WS1 side and a second side surface side edge 11ES2 extending in the height direction T on the second side surface WS2 side, and including a first side surface side edge 11ES1 extending in the height direction T from the first side surface side edge 11ES1 to the second side surface WS2 side. The first side effective layer portion 11E1 including the area along the width direction W toward the inside of the effective layer portion 11E, the second side effective layer portion 11E2 including the area from the second side edge 11ES2 along the width direction W toward the inside of the effective layer portion 11E, and the central side effective layer portion 11EC including the area near the center of the effective layer portion 11E in the width direction W, the average thickness in the height direction T of the dielectric layer 20 existing in the first side effective layer portion 11E1 and the second side effective layer portion 11E2 is thinner than the average thickness in the height direction T of the dielectric layer 20 existing in the central side effective layer portion 11EC, and the average particle size of the ceramic material in the dielectric layer 20 existing in the first side effective layer portion 11E1 and the second side effective layer portion 11E2 is larger than the average particle size of the ceramic material in the dielectric layer 20 existing in the central side effective layer portion 11EC.

[0145] In the past, there are known laminated ceramic capacitors. Generally, laminated ceramic capacitors have a ceramic sintered body containing dielectric ceramics such as barium titanate. A plurality of internal electrodes are arranged inside the ceramic sintered body so as to overlap each other through ceramic layers. In addition, external electrodes are formed on one end face and the other end face of the ceramic sintered body so as to be electrically connected to the internal electrodes.

[0146] In such a multilayer ceramic capacitor, when the thickness of the dielectric layer existing inside the side effective layer portion in the height direction T is thicker than the thickness of the dielectric layer existing inside the center effective layer portion in the height direction T, there are many pores (bubbles) in the side effective layer portion due to lack of proper compression, so that the density of the dielectric layer in the side effective layer portion decreases, thereby reducing the moisture resistance reliability.

[0147] Here, in this embodiment, as described above, the thickness of the dielectric layer in the height direction T present in the side effective layer portion is thinner than the thickness of the dielectric layer in the height direction T present in the center effective layer portion. As a result, the compactness of the side effective layer portion can be improved, and the infiltration of moisture into the laminate can be suppressed. As a result, the moisture resistance reliability of the laminated ceramic capacitor can be improved.

[0148] Furthermore, in the present embodiment, the grain size of the ceramic material in the dielectric layer present in the side effective layer portion is larger than the grain size of the ceramic material in the dielectric layer present in the center effective layer portion.

[0149] It is believed that if the particle size increases, the generation of additive segregation phase can be suppressed. This is because it is believed that if the particle size increases, the grain boundaries are reduced, so the generation of additive segregation phase of the low resistance layer that is easy to segregate to the grain boundaries can be suppressed. As a result, it is believed that the electric field concentration can be suppressed, so the high temperature reliability can be improved.

[0150] As described above, by controlling the thickness of the dielectric layer and the ceramic particle size, the density of the side effective layer can be improved to improve moisture resistance, and the number of ceramic particles in one dielectric layer can be made appropriate, thereby dispersing the electric field in one dielectric layer to improve high-temperature reliability.

[0151] Therefore, the present invention can provide a multilayer ceramic capacitor in which both moisture resistance and high-temperature reliability can be improved by controlling the thickness of the thin region of the dielectric element and the ceramic grain size.

[0152] (2) In the present embodiment, the ratio of the minimum thickness in the height direction T of the dielectric layer 20 existing inside the first side effective layer portion 11E1 and the second side effective layer portion 11E2 to the maximum particle size of the ceramic material in the dielectric layer 20 existing inside the first side effective layer portion 11E1 and the second side effective layer portion 11E2 is 0.83 or more and 1.82 or less. Thus, the number of particles in one dielectric layer in the side effective layer portion can be appropriately ensured, and the electric field distribution in the layer of the side effective layer portion can be further uniformized. As a result, the high temperature reliability can be further improved.

[0153] (3) In the present embodiment, the ceramic material in the dielectric layer 20 includes a perovskite structure including Ba, Sr, Zr, Ti, Hf, Si, and optionally Ca. Thus, the dielectric layer 20 can be made thinner, and even if it is made thinner, excellent insulation degradation life and moisture load resistance life under high electric fields can be obtained.

[0154] [Modifications]

[0155] For example, the structure of the multilayer ceramic capacitor 1 is not limited to Figure 1 to Figure 4 For example, the multilayer ceramic capacitor 1 may also be as follows Figure 6 The following is a dual-layer ceramic capacitor.

[0156] Figure 6 The stacked ceramic capacitor 1 shown is a stacked ceramic capacitor 1 of a 2-connection structure, and as the internal electrode layer 30, in addition to the first internal electrode layer 33 and the second internal electrode layer 34, it also has a floating internal electrode layer 35 that is not drawn out at any end surface of the first end surface LS1 and the second end surface LS2. In this way, the floating internal electrode layer 35 is provided as the internal electrode layer 30, so that the stacked ceramic capacitor 1 has a structure in which the effective layer portion is divided into a plurality of layers. As a result, a plurality of capacitance components are formed between the opposing internal electrode layers 30, and the capacitance components are connected in series. Therefore, the voltage applied to each capacitance component becomes lower, and the stacked ceramic capacitor 1 can be made to have a high withstand voltage.

[0157] The present invention is not limited to the configuration of the above-described embodiment, and can be applied with appropriate changes within the scope of the present invention. In addition, a combination of two or more of the preferred configurations described in the above-described embodiment also constitutes the present invention.

[0158] Description of Reference Numerals

[0159] 1: Multilayer ceramic capacitor;

[0160] T: height direction;

[0161] W: width direction;

[0162] L: length direction;

[0163] TS1: 1st main surface;

[0164] TS2: 2nd main surface;

[0165] WS1: side 1;

[0166] WS2: side 2;

[0167] LS1: 1st end face;

[0168] LS2: 2nd end face;

[0169] 10: laminate;

[0170] 11E: effective layer;

[0171] 11EC: effective layer part on the central part;

[0172] 11E1: first side effective layer portion;

[0173] 11E2: effective layer portion on the second side;

[0174] 11ES1: 1st side edge;

[0175] 11ES2: 2nd side edge;

[0176] 20: dielectric layer;

[0177] 30: Internal electrode layer.

Claims

1. A laminated ceramic capacitor, comprising a laminated body, the laminated body comprising a plurality of laminated dielectric layers and a plurality of laminated internal electrode layers, and comprising a first main surface and a second main surface opposite to each other in a height direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the height direction and the width direction, and comprising an effective layer portion in which the plurality of internal electrode layers are opposite to each other in the height direction via the dielectric layer, wherein: The dielectric layer comprises a ceramic material, The effective layer portion comprises: a first side surface edge of the first side surface extending in the height direction; and a second side edge extending in the height direction of the second side surface, And the effective layer portion comprises: The first side effective layer portion includes a region extending from the first side edge along the width direction toward the interior of the effective layer portion; The second side effective layer portion includes a region extending from the second side edge along the width direction toward the interior of the effective layer portion; and The central side effective layer portion includes a region near the central portion of the effective layer portion in the width direction, The average thickness in the height direction of the dielectric layer existing inside the first side effective layer portion and the second side effective layer portion is thinner than the average thickness in the height direction of the dielectric layer existing inside the center side effective layer portion, An average grain size of the ceramic material in the dielectric layer inside the first-side effective layer portion and the second-side effective layer portion is larger than an average grain size of the ceramic material in the dielectric layer inside the center-side effective layer portion.

2. The multilayer ceramic capacitor according to claim 1, wherein The ratio of the minimum thickness in the height direction of the dielectric layer existing inside the first side effective layer portion and the second side effective layer portion to the maximum particle size of the ceramic material in the dielectric layer existing inside the first side effective layer portion and the second side effective layer portion is greater than 0.83 and less than 1.

82.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein: The ceramic material in the dielectric layer comprises a perovskite structure comprising Ba, Sr, Zr, Ti, Hf, Si, and optionally Ca.

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