Method and device for evaluating aging state of solder layer based on reflection characteristic identification

Abstract

The invention belongs to a power semiconductor device state monitoring method, and particularly relates to a solder layer aging state evaluation method and device based on reflection characteristic identification. The method comprises: generating a detection signal; injecting a detection signal into the to-be-tested equipment, transmitting the detection signal to the to-be-tested equipment through the connecting cable, and generating a corresponding reflection signal under the condition that the impedance of the connecting cable is not matched with the impedance of the to-be-tested equipment; determining a target reflected signal based on the synchronization reference signal and the reflected signal; processing the target reflection signal to obtain a target characteristic parameter related to the impedance attribute of the to-be-tested equipment; and mapping the target characteristic parameter into a corresponding target aging state based on a mapping model of the characteristic parameter and the aging state. According to the method, partial limitation of an internal parameter monitoring scheme is overcome, the defects of complexity and precision of a stress coupling model in the prior art can be effectively avoided, and packaging limitation of module internal evaluation parameter acquisition is overcome.

Description

Technical Field

[0001] The present invention relates to a method for monitoring the state of a power semiconductor device, and in particular to a method and a device for evaluating the aging state of a solder layer based on reflection feature identification. Background Art

[0002] Power modules represented by insulated gate bipolar transistors (IGBTs) are core components of power transmission, conversion and control systems. Research on the aging status of solder layers based on the degradation mechanism of IGBT modules has a positive guiding significance for device failure warning and system operation and maintenance. At present, the "electromagnetic-thermal-mechanical" stress coupling model is one of the theoretical foundations for the study of solder layer aging failure laws and fatigue life prediction. Among them, the thermal stress effect caused by the mismatch of the coefficient of thermal expansion (CTE) is the key to the traceability analysis of the solder layer aging process.

[0003] At present, the existing research on monitoring and evaluation of solder layer aging status is mainly based on analytical methods such as multi-physics field simulation and thermal network modeling, which indirectly maps the solder aging status by measuring or estimating thermal resistance and junction temperature parameters, or directly evaluates and monitors the aging status and remaining service life of IGBT modules by simulating the evolution of voids and cracks and performing sample distribution statistics. However, multi-physics field analysis and thermal propagation network models are easily affected by factors such as parameter accuracy and temperature sensitivity, and the detection accuracy of characteristic parameters such as thermal resistance and junction temperature is limited by the limitations of device packaging structure at the application level. Summary of the invention

[0004] The technical problem to be solved by the present invention is that the above-mentioned methods commonly used in the prior art are easily affected by factors such as parameter accuracy and temperature sensitivity, and the detection accuracy of characteristic parameters such as thermal resistance and junction temperature is limited by the limitations of the device packaging structure at the application level. In order to solve the above problems, the present invention provides a method and device for evaluating the aging status of a solder layer based on reflection feature identification.

[0005] The content of the present invention includes:

[0006] In a first aspect, an embodiment of the present invention provides a method for evaluating the aging state of a solder layer based on reflection feature recognition, comprising:

[0007] generating a detection signal;

[0008] Injecting the detection signal into the device to be tested, the detection signal is transmitted to the device to be tested via a connecting cable, and generating a corresponding reflection signal when the impedance of the connecting cable does not match the impedance of the device to be tested;

[0009] determining a target reflected signal based on a synchronization reference signal and the reflected signal, wherein the synchronization reference signal is the same as the detection signal;

[0010] Processing the target reflection signal to obtain a target characteristic parameter related to the impedance property of the device to be tested;

[0011] Based on a pre-constructed mapping model between characteristic parameters and aging states, the target characteristic parameters are mapped to corresponding target aging states.

[0012] Optionally, generating a detection signal comprises:

[0013] The pseudo-random sequence is spread spectrum modulated by binary phase shift keying to obtain the SSTDR signal;

[0014] The SSTDR signal is determined as a detection signal.

[0015] Optionally, determining the target reflected signal based on the synchronization reference signal and the reflected signal includes:

[0016] Acquire an initial acquisition sample, wherein the initial acquisition sample contains aliasing of multiple reflected signals;

[0017] Fitting the waveforms of the remaining reflection signals except the first reflection signal in the initial collection samples, and extracting the target reflection signal from the initial collection samples;

[0018] Performing a cross-correlation operation on the target reflection signal and the synchronization reference signal to obtain a correlation operation result;

[0019] The target characteristic parameter is determined based on the correlation operation result, and the target characteristic parameter is the maximum correlation peak value.

[0020] Optionally, the initial collection sample is:

[0021]

[0022] Among them, S i is the detection signal, S ac is the initial sample collection, f DUT (n) is the nth reflection signal generated by the device to be tested, and m is the number of reflection signals collected; ρ A is the transmission coefficient at the endpoint of the device to be tested, and n and m are both integers greater than or equal to 2;

[0023] The fitting waveforms of multiple reflection signals satisfy:

[0024]

[0025] Among them, f A (n) is the nth reflection signal at the injection point of the detection signal, i A (n) is the nth transmission signal at the injection point of the detection signal, Γ A is the reflection coefficient at the injection point of the detection signal, Γ B is the reflection coefficient at the endpoint of the device to be tested;

[0026] The target reflection signal is:

[0027]

[0028] Among them, f DUT_ref (n) is the fitting waveform of the nth reflection signal.

[0029] Optionally, the maximum correlation peak satisfies:

[0030]

[0031] Among them, S i is the detection signal, f DUT (t-τ) is the reflection signal generated by the device under test at time (t-τ), f DUT (1) is the target reflection signal, ρ A is the transmission coefficient at the endpoint of the device to be tested, R(t) is the correlation operation result, T is the signal period, τ is the round-trip transmission delay of the signal, when t0=τ, R(t) is equal to the maximum correlation peak R Pτ .

[0032] Optionally, before determining the target reflected signal based on the synchronization reference signal and the reflected signal, the method further includes:

[0033] The reflection signal is collected along a first channel, and the synchronization reference signal is collected along a second channel, where the synchronization reference signal is a signal generated synchronously with the detection signal.

[0034] Optionally, before mapping the target characteristic parameter to the corresponding target aging state based on the pre-constructed mapping model of characteristic parameters and aging states, the method further includes:

[0035] Injecting the detection signal at different aging stages of an experimental device, the experimental device and the device to be tested being of the same type;

[0036] Extracting target reflection signals corresponding to the experimental equipment at different aging stages;

[0037] The target reflection signals corresponding to the different aging stages are processed to obtain characteristic parameters corresponding to the different aging stages, and a mapping model between the characteristic parameters and the aging state is constructed.

[0038] In a second aspect, an embodiment of the present invention provides a solder layer aging state assessment device based on reflection feature recognition, comprising:

[0039] A signal generating module, used for generating a detection signal;

[0040] A signal injection module, used for injecting the detection signal into the device to be tested, wherein the detection signal is transmitted to the device to be tested via a connecting cable, and generating a corresponding reflection signal when the impedance of the connecting cable does not match the impedance of the device to be tested;

[0041] A first processing module, configured to determine a target reflected signal based on a synchronization reference signal and the reflected signal, wherein the synchronization reference signal is the same as the detection signal;

[0042] A second processing module, used for processing the target reflection signal to obtain a target characteristic parameter related to the impedance property of the device to be tested;

[0043] The mapping module is used to map the target characteristic parameter to the corresponding target aging state based on a pre-constructed mapping model between the characteristic parameter and the aging state.

[0044] In a third aspect, an embodiment of the present invention provides an electronic device, comprising: a memory, a processor, and a program stored in the memory and executable on the processor; the processor is used to read the program in the memory to implement the steps in the method for evaluating the aging status of a solder layer based on reflection feature identification as described in the first aspect.

[0045] In a fourth aspect, an embodiment of the present invention provides a readable storage medium for storing a program, which, when executed by a processor, implements the steps in the method for evaluating the aging state of a solder layer based on reflection feature recognition as described in the first aspect.

[0046] In view of the problems that the existing multi-physics field analysis and heat propagation network model methods are easily affected by factors such as parameter accuracy and temperature sensitivity, and the detection accuracy of characteristic parameters such as thermal resistance and junction temperature is limited by the limitations of the device packaging structure at the application level, in an embodiment of the present invention, a detection signal is injected into the device to be tested, and the detection signal is transmitted to the device to be tested via a connecting cable, and a corresponding reflection signal is generated when the impedance of the connecting cable does not match the impedance of the device to be tested; a target reflection signal is determined based on a synchronous reference signal and the reflection signal, and the target reflection signal is processed to obtain a target characteristic parameter related to the impedance property of the device to be tested; based on a pre-constructed mapping model of characteristic parameters and aging states, the target characteristic parameters are mapped to corresponding target aging states.

[0047] The beneficial effect of the present invention is that the method provided by the present invention does not rely on the traditional electrical parameters of the device to be tested. Since there is an obvious bandwidth difference between the injected detection signal and the normal working signal of the system, a non-intrusive detection target without interference can be achieved. At the same time, the present invention indirectly depicts the development trend of solder layer voids by means of signal reflection characteristics, overcomes some limitations of the internal parameter monitoring scheme, can effectively avoid the complexity and accuracy defects of the "electromagnetic-thermal-mechanical" stress coupling model in the prior art, and overcomes the packaging limitations of the module internal evaluation parameter collection. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Attached Figure 1 A flow chart of a method for evaluating the aging state of a solder layer based on reflection feature recognition provided by an embodiment of the present invention;

[0049] Attached Figure 2 Schematic diagram of the SSTDR signal modulation, transmission and reflection process provided by an embodiment of the present invention;

[0050] Attached Figure 3a A schematic diagram of an SSTDR signal detection solution for IGBT state evaluation provided by an embodiment of the present invention;

[0051] Attached Figure 3b For attachment Figure 3a A partial enlarged view of the signal generation part;

[0052] Attached Figure 3c For attachment Figure 3a A partial enlarged view of the signal detection module;

[0053] Attached Figure 3d For attachment Figure 3a A partial enlarged view of the DUT module;

[0054] Attached Figure 3e For attachment Figure 3a A partial enlarged view of the data processing part;

[0055] Attached Figure 4a Schematic diagram of the device to be tested;

[0056] Attached Figure 4b This is a schematic diagram of the initial sample in the off state;

[0057] Attached Figure 4c It is a schematic diagram of the initial sample in the on state;

[0058] Attached Figure 4d Schematic diagram of R(t) in the off state;

[0059] Attached Figure 4e Schematic diagram of R(t) in the on state;

[0060] Attached Figure 4f This is a schematic diagram of the normalized related waveform in the off state;

[0061] Attached Figure 4g It is a schematic diagram of the normalized related waveform in the on state;

[0062] Attached Figure 5 The internal structure of the IGBT and the detection signal transmission path provided by the embodiment of the present invention;

[0063] Attached Figure 6 A schematic diagram of the accelerated aging experiment platform provided in an embodiment of the present invention;

[0064] Attached Figure 7 Characterize the device aging status based on the trend of void rate change;

[0065] Attached Figure 8 A schematic flow chart of a solder layer aging state assessment method based on SSTDR signal feature mapping provided by an embodiment of the present invention;

[0066] Attached Figure 9a It is the experimental test platform in this embodiment;

[0067] Attached Figure 9b This is a schematic diagram of an aging sample to be tested in this embodiment;

[0068] Attached Fig.10a The variation trend of the characteristic parameters of SSTDR signal under BPSK7 code type as the solder layer ages;

[0069] Attached Fig.10b The variation trend of the characteristic parameters of SSTDR signal under BPSK15 code type as the solder layer ages;

[0070] Attached Fig.10c The variation trend of the characteristic parameters of the SSTDR signal under the BPSK31 code type as the solder layer ages;

[0071] Attached Fig.10d The variation trend of the characteristic parameters of the SSTDR signal under the BPSK63 code type as the solder layer ages;

[0072] Attached Fig.11 A schematic diagram of a solder layer aging state assessment device based on reflection feature recognition provided by an embodiment of the present invention;

[0073] Attached Fig.12 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0074] In the embodiments of the present invention, the term "and / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent three situations: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar. The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable where appropriate, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first" and "second" are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more.

[0075] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0076] See also Figure 1 , Figure 1 A flow chart of a method for evaluating the aging state of a solder layer based on reflection feature recognition provided in an embodiment of the present invention is provided. This method can be used to evaluate the aging state of different devices. For example, the aging state of an IGBT solder layer can be evaluated based on this method.

[0077] like Figure 1 As shown, the method specifically comprises the following steps:

[0078] Step 101: Generate a detection signal.

[0079] Step 102 : injecting the detection signal into the device under test, the detection signal is transmitted to the device under test via a connecting cable, and generating a corresponding reflection signal when the impedance of the connecting cable does not match the impedance of the device under test.

[0080] Step 103: determining a target reflected signal based on a synchronization reference signal and the reflected signal, wherein the synchronization reference signal is the same as the detection signal.

[0081] Step 104: Process the target reflection signal to obtain target characteristic parameters related to the impedance property of the device to be tested.

[0082] Step 105 : Mapping the target characteristic parameter to the corresponding target aging state based on a pre-constructed mapping model between the characteristic parameter and the aging state.

[0083] For ease of understanding, the relevant principles of evaluating the aging state of the device to be tested based on the present invention are first introduced below.

[0084] See also Figure 2 , define the impedance of the connecting cable as Z0, and the impedance of the device under test (DUT) as Z x From the transmission line theory, we know that the injected detection signal S i (i.e. incident signal) Figure 2 After being injected into point A (i.e., the injection point of the detection signal), it propagates along the connecting cable (in this embodiment, the connecting cable is a homogeneous cable). If there is an impedance mismatch between the DUT and the connecting cable (Z x ≠Z0), then from the boundary conditions, we know that the signal Figure 2 Point B (i.e., the end point of the device to be tested) is continuous and does not undergo a sudden change. Therefore, S i Reflection and transmission will occur at the DUT, and S is defined f For S i The reflected signal, S r For S i The transmission signal, U i is the voltage effective value of the detection signal, I i is the effective value of the current of the detection signal, U f is the voltage effective value of the reflected signal, I f is the effective value of the current of the reflected signal, U r is the voltage effective value of the transmission signal, I r is the effective value of the current of the transmission signal, then the following relationship in formula (1) is satisfied:

[0085]

[0086] Where Γ is the reflection coefficient of the signal and ρ is the transmission coefficient of the signal.

[0087] From the above formula (1), we can see that Γ and ρ change with Z x Change, when Z x >>Z0, Γ≈1, the signal is totally reflected (S f =S i ); when Z x = Z0, Γ = 0, impedance matching, signal is not reflected (S f =0); when Z x ≈0, Γ≈-1, the signal is totally reflected in the negative direction (S f ≈-S i ). According to the above rules, the correlation between the reflected signal and the DUT impedance state can be established.

[0088] In this embodiment, the device under test (DUT) is taken as the whole or part of the IGBT module as an example. As a specific embodiment, the whole or part of the IGBT module is taken as the DUT, and the observed object will show the impedance property related to the detection signal, and Z x will change with the aging process of the device, so extracting S f The impedance characteristic information contained in can provide a basis for evaluating the aging status of DUT.

[0089] Optionally, in some embodiments, step 101 includes:

[0090] The pseudo-random sequence is spread spectrum modulated by binary phase shift keying to obtain the SSTDR signal;

[0091] The SSTDR signal is determined as a detection signal.

[0092] See also Figure 2 As a specific embodiment, a pseudo-random noise code (PN) is modulated by binary phase shift keying (BPSK) to obtain a spread spectrum time domain reflectometry (SSTDR) signal, and the obtained SSTDR signal is injected as a detection signal. Through the above method, the robustness and signal recognition accuracy of the detection signal under complex network conditions can be greatly improved, thereby improving the accuracy of the evaluation.

[0093] Optionally, in some embodiments, step 103 includes:

[0094] Acquire an initial acquisition sample, wherein the initial acquisition sample contains aliasing of multiple reflected signals;

[0095] Fitting the waveforms of the remaining reflection signals except the first reflection signal in the initial collection samples, and extracting the target reflection signal from the initial collection samples;

[0096] Performing a cross-correlation operation on the target reflection signal and the synchronization reference signal to obtain a correlation operation result;

[0097] The target characteristic parameter is determined based on the correlation operation result.

[0098] See also Figure 2 , Figure 2 The platform solution for SSTDR signal detection of IGBT module constructed by the present invention. The signal generation module injects the modulated SSTDR signal from point A, S i Transmitted along the connecting cable to the DUT test end (point B), when the impedance does not match (Z0≠Z DUT ), DUT generates S f And transmit it back to the signal acquisition module at point A.

[0099] When actually testing the IGBT, since the round-trip transmission delay of the signal is usually much smaller than the signal period and the signal injection / collection end is a multi-branch structure, the initial signal samples stored in the signal acquisition module have aliasing, that is, in this embodiment, the initial collection samples have aliasing of multiple reflected signals. In order to improve the recognition accuracy of the signal characteristic peak, it is necessary to extract the first (target) reflection signal to avoid the adverse effects of the aliasing phenomenon.

[0100] A cross-correlation operation is performed on the target reflection signal and the synchronization reference signal, and a correlation operation result is obtained:

[0101]

[0102] Optionally, in some embodiments, the initially collected sample is:

[0103]

[0104] Among them, S i is the detection signal, S ac is the initial sample collection, f DUT (n) is the nth reflection signal generated by the device to be tested, and m is the number of reflection signals collected; ρ A is the transmission coefficient at the endpoint of the device to be tested, and n and m are both integers greater than or equal to 2.

[0105] Based on the detection platform topology, the fitting waveforms of multiple reflection signals can be obtained as follows:

[0106]

[0107] Among them, f A (n) is the nth reflection signal at the injection point of the detection signal, i A (n) is the nth transmission signal at the injection point of the detection signal, Γ A is the reflection coefficient at the injection point of the detection signal, Γ B is the reflection coefficient at the end point of the device under test, Γ A , Γ B and ρ A Determined by the impedance parameters of the connecting cables and DUT.

[0108] Combining the above formulas (3) and (4), by fitting the waveforms of the remaining reflection signals except the first one, the target reflection signal can be extracted from the initial collected samples. The target reflection signal is:

[0109]

[0110] Among them, f DUT_ref (n) is the fitting waveform of the nth reflection signal.

[0111] Combining the above formula (2) and formula (5), the SSTDR signal characteristic value analytical model suitable for the IGBT module detection solution can be obtained. The target characteristic parameters can be calculated through the above analytical model.

[0112] Optionally, in some embodiments, the target characteristic parameter is a maximum correlation peak value, and the maximum correlation peak value satisfies:

[0113]

[0114] Among them, S i (τ) is the synchronization reference signal, R(t) is the correlation operation result, T is the signal period, τ is the round-trip transmission delay of the signal, when t0 = τ, R(t) achieves the maximum correlation peak R Pτ .

[0115] Through the above embodiments, the interference waveform can be eliminated, and the target reflected signal waveform after filtering the interference signal is smoother and conforms to the impedance mapping response law of the reflected signal and the DUT, thereby improving the precision and accuracy of evaluating the aging status of the DUT.

[0116] Optionally, in some embodiments, before step 103, the method further includes:

[0117] The reflection signal is collected along the first channel, and the synchronization reference signal is collected along the second channel, wherein the synchronization reference signal is a signal generated synchronously with the detection signal. In this embodiment, the synchronization reference signal is another synchronously generated detection signal and is directly collected by the signal collection device along another independent channel.

[0118] In order to verify the feasibility of the above-mentioned solder layer aging state assessment method based on reflection feature recognition, the SKM50GB12T4 type soldering PMI is selected as the DUT in this embodiment to carry out the platform function verification experiment. Figure 4a When the drive circuit controls the IGBT in normal on-off operation, the substrate temperature is kept constant at 25°C at room temperature, and the SSTDR modulation signal is injected into the CE terminal to collect the initial sample. Figure 4b and Figure 4c .

[0119] It should be understood that in this embodiment, the on and off states of the IGBT correspond to "on" and "off" respectively. During the test, the driving signal of the IGBT controls the tube action normally, so the target reflection signal of the IGBT in two states can be obtained during the experimental test. In this embodiment, the data waveforms of both the on and off states are collected for subsequent signal processing.

[0120] From the collected signal S ac With reference signal S i It can be seen from the waveform of (τ) that the two are synchronized, but due to the influence of signal aliasing, the initial sampling waveform has serious coupling distortion. Therefore, based on the above formulas (3) and (4), signal fitting analysis is performed and the interference waveform is eliminated to obtain the target reflection signal of the DUT in the on and off states respectively, and finally the characteristic peak value R related to the impedance property of the DUT is extracted based on formula (6). pτ .

[0121] See also Figure 4d-4g It can be seen that the waveform of the target reflected signal after filtering out the interference signal is smoother and conforms to the impedance mapping response law of the reflected signal and the DUT:

[0122]

[0123] In the off state, the equivalent impedance of the CE terminal of the IGBT is significantly lower than Z0, so the relevant peak value is positive R pτ (+). Its corresponding delay τ=232ns, in the off state R pτ(-) corresponds to a delay of 218ns, and the ideal delay of the reflected signal generated by the IGBT can be calculated from the known experimental parameters of the platform to be about 215ns, so the feasibility and accuracy of the proposed signal processing algorithm for identifying target feature information are confirmed within the ns level error range. The experimental results show that the signal preprocessing algorithm for aliasing blind area identification improves the "signal-impedance" mapping accuracy of the IGBT, which provides a good premise for extracting the weak impedance change information caused by the evolution of the chip solder layer void.

[0124] The following is an explanation of each parameter. pτ is the peak value of the relevant waveform, |R pτ | is its absolute value, R pτ (+) is the “positive correlation peak” corresponding to the “high impedance state”, R pτ (-) is the "negative correlation peak" corresponding to the "low impedance state", "Z DUT -1 The superscript “-1” in “” stands for the reciprocal.

[0125] In order to achieve the purpose of mechanistic analysis of the characteristic parameters of the reflection signal, we first take IGBT as an example and carry out device-level analytical research in combination with the local structural characteristics of IGBT and the evolution mechanism of the solder layer.

[0126] The IGBT module contains multiple physical layers, but the physical properties of various materials vary greatly. During the service life of the device, the "electrical-thermal-mechanical" coupling effect cycles back and forth. The deformation difference caused by the CTE difference of various materials will cause interlayer stress fluctuations. Since the material properties of the solder layer and the adjacent layers are the most different, the fatigue accumulation effect is the most significant. At the same time, the increase in impedance caused by the increase in the void rate also corresponds to the change in the characteristic parameters of the reflected signal.

[0127] See also Figure 5 , Figure 5 The internal structure section of the IGBT used as the DUT in the embodiment of the present invention is shown in FIG. Each material layer is electrically or physically connected through solder. The flow path of the SSTDR detection signal injected into the CE terminal in the IGBT module is: "C pin terminal - upper copper layer - chip solder layer - IGBT chip - bonding wire - upper copper layer - E pin terminal" and "freewheeling diode (Freewheeling diode, FWD) reverse freewheeling path", so the DUT equivalent impedance Z can be obtained. CE_eq The simplified expression of is as follows:

[0128] Z CE_eq =Z C +Z Co +Z E +(Z S_chip +Z T_chip +Z W)||(Z S_chip +Z D_chip +Z W ) (8);

[0129] Among them, "||" represents parallel summation, and Z C is the equivalent impedance of the collector terminal, Z Co is the equivalent impedance of the copper layer, Z E represents the equivalent impedance of the emitter terminal, Z S_chip is the equivalent impedance of the chip solder layer, Z T_chip is the equivalent impedance of the IGBT chip, Z D_chip is the equivalent impedance of the FWD chip, Z W is the equivalent impedance of the bonding wire. In this embodiment, taking the IGBT as the device under test, then Z CE_eq has the same meaning as the aforementioned Z DUT .

[0130] This embodiment takes the IGBT chip with more significant service loss as the research object. Therefore, to avoid misfiring of the FWD, a positive DC bias is superimposed on S i . For the convenience of analyzing the impedance characteristics of the target reflection signal, taking Z0 as the reference term, "R0" and "R ∞ " are defined to represent "Z DUT <<Z0" and "Z DUT >>Z0" two types of impedance value ranges, respectively. Then there is:

[0131]

[0132] Among them, σ is the void fraction of the chip solder layer, "on" is used to characterize the on-state of the IGBT, "off" is used to characterize the off-state of the IGBT, and "all" is used to characterize that both states are satisfied (on / off).

[0133] Combining equations (7)-(9), it can be seen that when the IGBT chip is conducting normally (on), the relationship between the impedance of the chip solder layer and the measured impedance at the C-E terminal satisfies:

[0134]

[0135] The above formula (10) clarifies the response trend of the impedance attributes of the IGBT device and the characteristic parameters of the reflection signal during the degradation process of the chip solder layer, and constructs the mapping relationship between "signal-impedance-solder layer".

[0136] For IGBT, solder layer failure is one of the main mechanisms of IGBT degradation, and the void rate of the chip solder layer can intuitively reflect the health-aging status of the IGBT module. In order to clarify the development trend of the void rate with the aging process of the device to be studied, in this embodiment, the SKM50GB12T4 IGBT is taken as an example, and the power cycle method is used to simulate the complete aging process of the healthy sample until the device is finally damaged.

[0137] See also Figure 6 , Figure 6 The simplified topology of the accelerated aging experimental platform built for this embodiment. In the example, the aging sample repeats the heating and cooling process during the power cycle of a single cycle of about 35s. During the on-phase of the IGBT chip, a large current is passed until the module reaches thermal equilibrium. During the off-phase, 100mA continuous current is maintained. With the help of a water cooling device, the IGBT chip junction temperature fluctuation range of the aging sample is controlled within 30-140℃.

[0138] Generally, the life cycle of an IGBT under fatigue accumulation conforms to the trend of a "bathtub curve". Therefore, this embodiment records void samples in a step-by-step manner based on the balance of aging efficiency and evaluation effect factors: "healthy → 2W cycles → 3.5W cycles → ..." until the device fails (short circuit) at 3.964W cycles.

[0139] In this embodiment, the sample CT image is binarized, and the chip solder layer void rates σ of the samples at different aging stages are obtained by OpenCV algorithm: 0 times (healthy - 3.3254%) → 2W times (3.7650%) → 3.5W times (6.7005%) → 3.964W times (faulty damage - 18.7689%).

[0140] like Figure 7 As shown in the figure, with the increase of the number of power cycles, the iteration speed of the IGBT module in different aging stages (healthy → early service → mid-to-late service → failure) gradually accelerates (red curve). During this period, the chip solder layer also grows from the initial void rate, experiences a steady slow growth period, a rapid rise period, and finally reaches a peak value when the module fails (blue curve). The trend of the void rate σ with the increase of the (device) solder layer degradation process is the characteristic parameter (R) of the reflection signal in formula (10) pτ ) provides a reliable basis for the scientific verification of the identification results.

[0141] It can be seen from the above power cycling test results that although the void ratio can effectively characterize the degradation evolution process of the solder layer, the void identification process will destroy the integrity of the device. To overcome the above defects, this embodiment extracts the SSTDR signal characteristic parameters based on the "reflection signal characteristics-impedance properties-(device) solder layer aging state" mapping analytical model.

[0142] Optionally, in some embodiments, before step 105, the method further includes:

[0143] Injecting the detection signal at different aging stages of an experimental device, the experimental device and the device to be tested being of the same type;

[0144] Extracting target reflection signals corresponding to the experimental equipment at different aging stages;

[0145] The target reflection signals corresponding to the different aging stages are processed to obtain characteristic parameters corresponding to the different aging stages, and a mapping model between the characteristic parameters and the aging state is constructed.

[0146] See also Figure 8 As a specific embodiment, the method specifically includes the following steps:

[0147] Signal generation and injection: The SSTDR detection signal after parameter adjustment is obtained by performing spectrum modulation on the pseudo-random signal. During the power cycling experiment, the SSTDR detection signal is injected into the CE end at different aging stages of the IGBT module.

[0148] Signal acquisition and preprocessing: Collect and store the initial aliasing signal (i.e., the initial acquisition sample), and filter out the interference signal and environmental noise based on the above method to extract the target reflection signal.

[0149] Signal feature identification and aging assessment: Based on formula (6), the relevant peak parameters R corresponding to the target reflection signal at different aging stages are calculated respectively. pτ , extract the signal characteristic parameters that are consistent with the aging law of the solder layer (in this embodiment, the maximum correlation peak), and build a mapping model between the characteristic parameters and the aging state. For the new device to be tested, determine whether there are other degradation factors according to formula (10). If not, then based on R pτ Conduct aging status assessment.

[0150] Formula (10) shows the mapping relationship between “solder layer impedance-equivalent impedance of device CE end-related peak value”. From the above impedance model analysis, it can be seen that when the device ages and causes the solder layer to degrade, the impedance of the solder layer will change accordingly, resulting in an upward trend of the characteristic value, that is, 0<ΔR pτ <1, but since the impedance of the IGBT in the on state is always less than Z0, R pτ <0. When this condition is not met, it is considered that the characteristic value change caused by the impedance change is caused by other aging factors.

[0151] Based on the signal scheme shown in FIG3 , this embodiment detects the CE end reflection signal when the IGBT chip is turned on at different stages of the sample power cycle process. See FIG9 for the experimental platform built for this example. In order to clarify the effect of the signal code type on the detection method, four types of modulation signals (BPSK7, BPSK15, BPAK31 and BPSK63) are selected to carry out experiments. The experimental statistical results are as follows: Figure 10a-Figure 10d shown.

[0152] From the experimental results, we can see that the characteristic parameters of each type of detection signal |R Pτ | -1 With the increase of the number of power cycles, they all show a trend of "first slowly decreasing and then rapidly increasing". Combined with the "signal-impedance-solder layer" mapping analytical model shown in formula (10), it can be seen that in the early to middle stages of the device service, the chip solder layer void (σ) grows steadily and slowly. The void growth leads to an increase in the parasitic capacitance and equivalent resistance of the solder layer, while |R Pτ | -1 The downward trend indicates that the increase in parasitic capacitance dominates the solder layer impedance property Z in this process. S_chip The downward trend of Z CE_eq However, in the later period of service of the module near the short circuit fault, although σ also shows an accelerating upward trend, the equivalent resistance of the chip and solder layer near the melting breakdown increases significantly during this stage, thus dominating Z CE_eq The rapid increase of |R Pτ | -1 The above results are consistent with the aforementioned signal-impedance modeling theory.

[0153] See also Fig.10a The early change trend corresponding to the BPSK7 code in the modulation scheme fluctuates. Combined with the early slow growth trend of σ and the principle of related feature extraction, it can be seen that the response sensitivity of the SSTDR signal to the slight impedance change of the DUT is limited by the complexity of the signal pattern. The above results show that the accuracy of SSTDR signal feature recognition and anti-interference ability increase with the increase of the complexity of the modulation pattern, but under actual application conditions, the optimization degree of the pattern is also limited by factors such as signal generation, acquisition storage and processing costs.

[0154] See also Fig.10d The BPSK63 code shown in the figure is combined with the above theoretical analysis. Based on the change trend of the signal characteristic value in the "signal-impedance-solder layer" mapping association, the complete service life of the IGBT chip solder layer can be divided into four stages: healthy, slow degradation period, rapid degradation period and fault damage. Combining equations (7) and (10), it can be seen that in the process of continuously monitoring the aging state of the IGBT module solder layer, based on Δ|R Pτ | -1The (+, -) sign and Δ value can be used to scientifically evaluate the aging state of the device, and then provide guidance for the operation and maintenance of high-risk devices in the rapid degradation period. Compared with the (device) solder layer aging state assessment method that uses direct statistical void rate as a reference, the void rate is a measure of the solder layer aging state, but this method does not rely on the statistics of the void rate indicator, that is, it uses the "indirect" method of signal characteristic values ​​to map and evaluate the aging state of the DUT. It can be seen that this method, on the basis of overcoming the limitations of the collection of evaluation parameters within the module, clarifies the changing trend and division basis of the new evaluation indicators of the solder layer aging stage, and provides a new idea for the non-destructive detection method of the health-aging state of the chip solder layer.

[0155] The void rate is a measure of the aging state of the solder layer, but this method does not rely on the statistics of the void rate indicator, that is, it uses the "indirect" method of signal characteristic values ​​to map and evaluate the aging state of the DUT. The traditional void rate statistical evaluation method in the prior art can effectively characterize the degradation evolution process of the solder layer, but the void identification process will destroy the integrity of the device. The present invention indirectly depicts the development trend of the void in the solder layer by means of signal reflection characteristics, overcoming some limitations of the internal parameter monitoring scheme.

[0156] In the embodiment of the present invention, the method does not rely on the traditional electrical parameters of the device under test, and because there is an obvious bandwidth difference between the injected detection signal and the normal working signal of the system, a non-intrusive detection goal without interfering with each other can be achieved.

[0157] See also Fig.11 The embodiment of the present invention further provides a solder layer aging state assessment device 1100 based on reflection feature recognition, comprising:

[0158] A signal generating module 1101 is used to generate a detection signal;

[0159] The signal injection module 1102 is used to inject the detection signal into the device under test, the detection signal is transmitted to the device under test via the connection cable, and a corresponding reflection signal is generated when the impedance of the connection cable does not match the impedance of the device under test;

[0160] A first processing module 1103 is configured to determine a target reflected signal based on a synchronization reference signal and the reflected signal, wherein the synchronization reference signal is the same as the detection signal;

[0161] The second processing module 1104 is used to process the target reflection signal to obtain a target characteristic parameter related to the impedance property of the device to be tested;

[0162] The mapping module 1103 is used to map the target characteristic parameter to the corresponding target aging state based on a pre-constructed mapping model between the characteristic parameter and the aging state.

[0163] Optionally, the signal generating module 1101 is specifically used for:

[0164] The pseudo-random sequence is spread spectrum modulated by binary phase shift keying to obtain the SSTDR signal;

[0165] The SSTDR signal is determined as a detection signal.

[0166] Optionally, the first processing module 1103 includes:

[0167] A collection unit, used for collecting and obtaining an initial collection sample, wherein the initial collection sample contains aliasing of multiple reflected signals;

[0168] An extraction unit, used for fitting the waveforms of the remaining reflection signals except the first reflection signal in the initial collection samples, and extracting the target reflection signal from the initial collection samples;

[0169] A calculation unit, used for performing a cross-correlation operation on the target reflection signal and the synchronization reference signal to obtain a correlation operation result;

[0170] A determination unit is used to determine the target characteristic parameter based on the correlation operation result, and the target characteristic parameter is a maximum correlation peak value.

[0171] Optionally, the initial collection sample is:

[0172]

[0173] Among them, S i is the detection signal, S ac is the initial sample collection, f DUT (n) is the nth reflection signal generated by the device to be tested, and m is the number of reflection signals collected; ρ A is the transmission coefficient at the endpoint of the device to be tested, and n and m are both integers greater than or equal to 2;

[0174] The fitting waveforms of multiple reflection signals satisfy:

[0175]

[0176] Among them, f A (n) is the nth reflection signal at the injection point of the detection signal, i A (n) is the nth transmission signal at the injection point of the detection signal, Γ A is the reflection coefficient at the injection point of the detection signal, Γ B is the reflection coefficient at the endpoint of the device to be tested;

[0177] The target reflection signal is:

[0178]

[0179] Among them, f DUT_ref (n) is the fitting waveform of the nth reflection signal.

[0180] Optionally, the maximum correlation peak satisfies:

[0181]

[0182] Among them, S i is the detection signal, f DUT (t-τ) is the reflection signal generated by the device under test at time (t-τ), f DUT (1) is the target reflection signal, ρ A is the transmission coefficient at the endpoint of the device to be tested, R(t) is the correlation operation result, T is the signal period, τ is the round-trip transmission delay of the signal, when t0=τ, R(t) is equal to the maximum correlation peak R Pτ .

[0183] Optionally, the solder layer aging state assessment device 1100 method based on reflection feature recognition further includes:

[0184] The acquisition module is used to acquire the reflection signal along the first channel and acquire the synchronization reference signal along the second channel, wherein the synchronization reference signal is a signal generated synchronously with the detection signal.

[0185] Optionally, the solder layer aging state assessment device 1100 based on reflection feature recognition further includes:

[0186] An injection module, used for injecting the detection signal into different aging stages of an experimental device, wherein the experimental device and the device to be tested are of the same type;

[0187] An extraction module, used to extract target reflection signals corresponding to the experimental equipment at different aging stages;

[0188] The third processing module is used to process the target reflection signals corresponding to the different aging stages to obtain characteristic parameters corresponding to the different aging stages, and to construct a mapping model between the characteristic parameters and the aging state.

[0189] The solder layer aging state assessment device 1100 based on reflection feature recognition provided in an embodiment of the present invention can execute the above method embodiment, and its implementation principle and technical effect are similar, which will not be described in detail in this embodiment.

[0190] It should be noted that the division of units in the embodiments of the present invention is schematic and is only a logical function division. There may be other division methods in actual implementation. In addition, each functional unit in each embodiment of the present invention may be integrated into a processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0191] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a processor-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) or a processor (processor) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program codes.

[0192] like Fig.12 As shown, an embodiment of the present invention provides an electronic device 1200, comprising: a memory 1202, a processor 1201, and a program stored in the memory 1202 and executable on the processor 1201; the processor 1201 is used to read the program in the memory 1202 to implement the steps in the solder layer aging status assessment method based on reflection feature identification as described above.

[0193] An embodiment of the present invention also provides a readable storage medium, on which a program is stored. When the program is executed by a processor, the various processes of the above-mentioned solder layer aging status assessment method based on reflection feature recognition are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here. Among them, the readable storage medium can be any available medium or data storage device that can be accessed by the processor, including but not limited to magnetic storage (such as floppy disk, hard disk, magnetic tape, magneto-optical disk (MO), etc.), optical storage (such as compact disk (CD), digital video disc (DVD), Blu-ray Disc (BD), high-definition versatile disc (HVD), etc.), and semiconductor memory (such as read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read only memory (EEPROM), non-volatile memory (NAND FLASH), solid-state drive (Solid State Disk or Solid State Drive, SSD)), etc.

[0194] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0195] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, disk, CD), and includes a number of instructions for a terminal (which can be a mobile phone, computer, server, air conditioner, or network equipment, etc.) to execute the methods described in each embodiment of the present invention.

[0196] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A method for evaluating the aging state of a solder layer based on reflection feature recognition, characterized in that: include: generating a detection signal; Injecting the detection signal into the device to be tested, the detection signal is transmitted to the device to be tested via a connecting cable, and generating a corresponding reflection signal when the impedance of the connecting cable does not match the impedance of the device to be tested; determining a target reflected signal based on a synchronization reference signal and the reflected signal, wherein the synchronization reference signal is the same as the detection signal; Processing the target reflection signal to obtain a target characteristic parameter related to the impedance property of the device to be tested; Based on a pre-constructed mapping model between characteristic parameters and aging states, the target characteristic parameters are mapped to corresponding target aging states.

2. The method according to claim 1, characterized in that: The generating of the detection signal comprises: The pseudo-random sequence is spread spectrum modulated by binary phase shift keying to obtain the SSTDR signal; The SSTDR signal is determined as a detection signal.

3. The method according to claim 1, characterized in that: The determining of the target reflected signal based on the synchronization reference signal and the reflected signal comprises: Acquire an initial acquisition sample, wherein the initial acquisition sample contains aliasing of multiple reflected signals; Fitting the waveforms of the remaining reflection signals except the first reflection signal in the initial collection samples, and extracting the target reflection signal from the initial collection samples; Performing a cross-correlation operation on the target reflection signal and the synchronization reference signal to obtain a correlation operation result; The target characteristic parameter is determined based on the correlation operation result, and the target characteristic parameter is the maximum correlation peak value.

4. The method according to claim 3, characterized in that: The initial collection samples are: Among them, S i is the detection signal, S ac is the initial sample collection, f DUT (n) is the nth reflection signal generated by the device to be tested, and m is the number of reflection signals collected; ρ A is the transmission coefficient at the endpoint of the device to be tested, and n and m are both integers greater than or equal to 2; The fitting waveforms of multiple reflection signals satisfy: Among them, f A (n) is the nth reflection signal at the injection point of the detection signal, i A (n) is the nth transmission signal at the injection point of the detection signal, Γ A is the reflection coefficient at the injection point of the detection signal, Γ B is the reflection coefficient at the endpoint of the device to be tested; The target reflection signal is: Among them, f DUT_ref (n) is the fitting waveform of the nth reflection signal.

5. The method according to claim 3, characterized in that: The maximum correlation peak satisfies: Among them, S i is the detection signal, f DUT (t-τ) is the reflection signal generated by the device under test at time (t-τ), f DUT (1) is the target reflection signal, ρ A is the transmission coefficient at the endpoint of the device to be tested, R(t) is the correlation operation result, T is the signal period, τ is the round-trip transmission delay of the signal, when t0=τ, R(t) is equal to the maximum correlation peak R Pτ .

6. The method according to claim 1, characterized in that: Before determining the target reflected signal based on the synchronization reference signal and the reflected signal, the method further includes: The reflection signal is collected along a first channel, and the synchronization reference signal is collected along a second channel, where the synchronization reference signal is a signal generated synchronously with the detection signal.

7. The method according to any one of claims 1 to 6, characterized in that: Before mapping the target characteristic parameter to the corresponding target aging state based on the pre-constructed mapping model of characteristic parameters and aging states, the method further includes: Injecting the detection signal at different aging stages of an experimental device, the experimental device and the device to be tested being of the same type; Extracting target reflection signals corresponding to the experimental equipment at different aging stages; The target reflection signals corresponding to the different aging stages are processed to obtain characteristic parameters corresponding to the different aging stages, and a mapping model between the characteristic parameters and the aging state is constructed.

8. A solder layer aging state assessment device based on reflection feature recognition, characterized in that: include: A signal generating module, used for generating a detection signal; A signal injection module, used for injecting the detection signal into the device to be tested, wherein the detection signal is transmitted to the device to be tested via a connecting cable, and generating a corresponding reflection signal when the impedance of the connecting cable does not match the impedance of the device to be tested; A first processing module, configured to determine a target reflected signal based on a synchronization reference signal and the reflected signal, wherein the synchronization reference signal is the same as the detection signal; A second processing module, used for processing the target reflection signal to obtain a target characteristic parameter related to the impedance property of the device to be tested; The mapping module is used to map the target characteristic parameter to the corresponding target aging state based on a pre-constructed mapping model between the characteristic parameter and the aging state.

9. An electronic device, comprising: A memory, a processor, and a program stored in the memory and executable on the processor; wherein the processor is used to read the program in the memory to implement the steps in the solder layer aging status assessment method based on reflection feature identification as described in any one of claims 1 to 7.

10. A readable storage medium for storing a program, characterized in that: When the program is executed by a processor, the steps of the method for evaluating the aging state of a solder layer based on reflection feature recognition according to any one of claims 1 to 7 are implemented.

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