Planar gate silicon carbide VDMOS capable of improving short circuit reliability and preparation method of planar gate silicon carbide VDMOS

Abstract

The invention provides a planar gate silicon carbide VDMOS capable of improving short circuit reliability and a preparation method, and the preparation method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming drain electrode metal; performing epitaxial growth on the upper side surface of the silicon carbide substrate to form a drift layer; performing ion implantation on the drift layer to form a current sharing layer; forming a barrier layer on the drift layer, and performing etching and ion implantation to form a P-type well region and a low-resistance region; a barrier layer is formed again, etching and ion implantation are carried out, and an N-type source region and a P-type source region are formed; re-forming a barrier layer, etching the barrier layer to form a through hole, and depositing to form a first gate dielectric layer; depositing to form a second gate dielectric layer; a barrier layer is formed again, the barrier layer is etched to form a through hole, metal is deposited, and a gate metal layer is formed; and re-forming a barrier layer, etching the barrier layer to form a through hole, depositing metal, forming a source metal layer, and removing the barrier layer to complete preparation. And the heat conduction capability and the thermal reliability of the insulating medium are effectively improved.

Description

Technical Field

[0001] The invention relates to a planar gate silicon carbide VDMOS capable of improving short circuit reliability and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices, and is widely used in electric vehicles, aerospace, power conversion and other fields. For silicon carbide power VDMOS, the requirements for device performance in different fields have different emphases, but the overall requirements include lower on-resistance, faster switching speed, higher reliability (including gate reliability, drain voltage impact reliability, short circuit reliability, etc.), and lower body diode conduction loss.

[0003] In applications such as motor control systems or load switches, when the motor or load is short-circuited, VDMOS will be directly connected to the bus voltage. Since VDMOS is in the on state at this time, it will generate an instantaneous short-circuit current of hundreds of amperes, causing a very large internal transient temperature rise and damaging the device. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a planar gate silicon carbide VDMOS with improved short-circuit reliability and a preparation method thereof, so as to effectively improve the thermal conductivity and thermal reliability of the insulating medium.

[0005] In a first aspect, the present invention is implemented as follows: a method for preparing a planar gate silicon carbide VDMOS with improved short circuit reliability comprises the following steps:

[0006] Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal; epitaxially growing a drift layer on the side of the silicon carbide substrate;

[0007] Step 2, forming a current-balancing layer by ion implantation into the drift layer;

[0008] Step 3: forming a barrier layer on the drift layer, etching the barrier layer to form a through hole, and performing ion implantation into the current balancing layer to form a P-type well region;

[0009] Step 4, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the current balancing layer to form a low resistance area;

[0010] Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the P-type well region to form an N-type source region;

[0011] Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the P-type well region to form a P-type source region;

[0012] Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form a first gate dielectric layer;

[0013] Step 8, depositing to form a second gate dielectric layer, wherein the first gate dielectric layer and the second gate dielectric layer are made of different deposited materials;

[0014] Step 9, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer;

[0015] Step 10: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

[0016] In a second aspect, the present invention is implemented as follows: a planar gate silicon carbide VDMOS with improved short-circuit reliability, wherein the silicon carbide VDMOS is prepared by the preparation method of the first aspect.

[0017] The advantages of the present invention are:

[0018] 1. The present invention designs a gate insulating medium to address the gate structure degradation problem during short circuit. The gate dielectric is designed to be two layers. The first gate dielectric layer is traditional silicon dioxide to ensure good contact with the silicon carbide interface and reduce the interface state density. The second gate dielectric layer is diamond, which can effectively improve the thermal conductivity and thermal reliability of the insulating medium.

[0019] Second, the present invention constructs an N-type low resistance region in the JFET region, which can effectively reduce the on-resistance of the JFET region, avoid heat concentration in the JFET region during short circuit, and distribute it in the N-type drift layer with a larger resistance value, thereby avoiding heat concentration, effectively protecting the gate structure and suppressing heat concentration;

[0020] 3. Since heat accumulates in a very short time when the device is short-circuited, the source metal aluminum of the traditional device is easily melted by heat and flows toward the gate structure, affecting the reliability of the device. The present invention uses nickel-tungsten alloy to effectively improve the metal reliability of the device;

[0021] 4. In order to prevent heat from being concentrated in the JFET and its lower area when the device is short-circuited, an N-type current equalization area is constructed to evenly distribute the current from the JFET area to the inside of the device, moving the heat concentration area to the N-type drift area, close to the drain area, to improve the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0023] Figure 1 The schematic diagram of a planar gate silicon carbide VDMOS for improving short-circuit reliability of the present invention is shown.

[0024] Figure 2 A cross-sectional view of the process of a planar gate silicon carbide VDMOS with improved short circuit reliability according to the present invention Figure 1 .

[0025] Figure 3 A cross-sectional view of the process of a planar gate silicon carbide VDMOS with improved short circuit reliability according to the present invention Figure 2 .

[0026] Figure 4 A cross-sectional view of the process of a planar gate silicon carbide VDMOS with improved short circuit reliability according to the present invention Figure 3 .

[0027] Figure 5 A cross-sectional view of the process of a planar gate silicon carbide VDMOS with improved short circuit reliability according to the present invention Figure 4 .

[0028] Figure 6 A cross-sectional view of the process of a planar gate silicon carbide VDMOS with improved short circuit reliability according to the present invention Figure 5 .

[0029] Figure 7 A cross-sectional view of the process of a planar gate silicon carbide VDMOS with improved short circuit reliability according to the present invention Figure 6 .

[0030] Figure 8 A cross-sectional view of the process of a planar gate silicon carbide VDMOS with improved short circuit reliability according to the present invention Figure 7 .

[0031] Fig. 9 A cross-sectional view of the process of a planar gate silicon carbide VDMOS with improved short circuit reliability according to the present invention Figure 8 .

[0032] Fig.10 A cross-sectional view of the process of a planar gate silicon carbide VDMOS with improved short circuit reliability according to the present invention Figure 9 .

[0033] Fig.11 A cross-sectional view of the process of a planar gate silicon carbide VDMOS with improved short circuit reliability according to the present invention Figure 10 . DETAILED DESCRIPTION

[0034] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0036] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0037] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0038] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0039] like Figures 1 to 11 As shown, the embodiment of the present application provides a method for preparing a planar gate silicon carbide VDMOS with improved short circuit reliability, comprising the following steps:

[0040] Step 1: depositing metal on the lower side of the silicon carbide substrate 101 to form a drain metal 110; epitaxially growing a drift layer 102 on the upper side of the silicon carbide substrate 101;

[0041] Step 2: forming a current-balancing layer 103 by ion implantation into the drift layer 102, wherein the ion implantation energy is 10-300 keV;

[0042] Step 3: forming a barrier layer a on the drift layer 102, etching the barrier layer a to form a through hole, and performing ion implantation into the current balancing layer 103 to form a P-type well region 105, wherein the ion implantation energy is 10-200 keV;

[0043] Step 4: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, and perform ion implantation into the current balancing layer 103 to form a low resistance region 104, with the ion implantation energy being 10-200kev;

[0044] Step 5, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, perform ion implantation into the P-type well region 105 to form an N-type source region 1051, and the ion implantation energy is 10-100 keV;

[0045] Step 6: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, perform ion implantation into the P-type well region 105 to form a P-type source region 1052, and the ion implantation energy is 10-100 keV;

[0046] Step 7, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, and depositing to form a first gate dielectric layer 106;

[0047] Step 8: depositing to form a second gate dielectric layer 107, wherein the first gate dielectric layer 106 and the second gate dielectric layer 107 are made of different deposited materials;

[0048] Step 9, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, depositing metal, and forming a gate metal layer 109;

[0049] Step 10: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, deposit metal to form a source metal layer 108, remove the barrier layer a, and complete the preparation.

[0050] like Figure 1 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes:

[0051] Silicon carbide substrate 101,

[0052] A drift layer 102, wherein the lower side of the drift layer 102 is connected to the upper side of the silicon carbide substrate 101;

[0053] A current balancing layer 103, wherein the lower side of the current balancing layer 103 is connected to the upper side of the drift layer 102; a groove (not shown) is provided in the current balancing layer 103;

[0054] A low resistance region 104, wherein the low resistance region 104 is disposed in the groove, and the lower side of the current balancing layer 104 is connected to the current balancing layer 103;

[0055] A P-type well region 105, wherein the P-type well region 105 is disposed in the groove, wherein the outer side of the P-type well region 105 is connected to the current balancing layer 103, the inner side of the P-type well region 105 is connected to the outer side of the low resistance region 104, and the lower side of the P-type well region 105 is connected to the current balancing layer 103; an N-type source region 1051 and a P-type source region 1052 are disposed in the P-type well region 105, wherein the N-type source region 1051 is connected to the P-type source region 1052;

[0056] A first gate dielectric layer 106, wherein the lower side of the first gate dielectric layer 106 is respectively connected to the N-type source region 1051, the P-type well region 105 and the low resistance region 104;

[0057] A second gate dielectric layer 107 , wherein the second gate dielectric layer 107 is connected to the first gate dielectric layer 106 ;

[0058] A source metal layer 108 , wherein the source metal layer 108 is respectively connected to the current balancing layer 103 , the P-type well region 105 , the N-type source region 1051 , and the P-type source region 1052 ;

[0059] A gate metal layer 109 , wherein the gate metal layer 109 is connected to the second gate dielectric layer 107 ;

[0060] and a drain metal layer 110 , wherein the drain metal layer 110 is connected to the lower side of the silicon carbide substrate 101 .

[0061] In this embodiment, preferably, the first gate dielectric layer 106 is silicon dioxide, and the second gate dielectric layer 107 is diamond.

[0062] In this embodiment, preferably, the doping concentration of the low resistance region 104 is greater than the doping concentration of the current equalizing layer 103 .

[0063] In this embodiment, preferably, the thickness of the first gate dielectric layer 106 is smaller than the thickness of the second gate dielectric layer 107 .

[0064] In this embodiment, preferably, the thickness of the P-type well region 105 is twice the thickness of the N-type source region 1051 .

[0065] In this embodiment, preferably, the thickness of the current balancing layer 103 is three times the thickness of the N-type source region 1051 .

[0066] In this embodiment, preferably, the thickness of the low resistance region 104 is equal to the thickness of the P-type well region 105 .

[0067] In another embodiment, the silicon carbide substrate 101 is N-type, and its doping concentration is 2e18cm -3 ; The drift layer 102 is N-type, and its doping concentration is 1e16cm -3 The current balancing layer 103 is N-type, and its doping concentration is 1e17cm -3 ; The doping concentration of the P-type well region 105 is 5e17 cm -3 ; The low resistance region 104 is N-type, and its doping concentration is 1e18 cm -3 The material of the first gate dielectric layer 106 is silicon dioxide, the material of the second gate dielectric layer 107 is diamond, and the doping concentration of the N-type source region 1051 is 2e18cm -3 , the doping concentration of the P-type source region 1052 is 1e19cm -3 ;

[0068] The concentration of the N-type silicon carbide substrate 101 is to ensure the formation of a low-resistance ohmic contact with the drain metal layer 110, thereby reducing the overall on-resistance of the device; the doping concentration of the N-type drift layer 102 is a compromise between the reverse withstand voltage and on-resistance of the device, and the doping concentration of the N-type current balancing layer 103 is to reduce the on-resistance of the device while forming a Schottky metal rather than an ohmic contact with the source metal layer 108; the N-type low-resistance region 104 is to reduce the resistance of the device JFET region to avoid heat generation in this region affecting the reliability of the device gate structure, and the doping concentrations of the N-type source region 1051 and the P-type source region 1052 are to form an ohmic contact with the source metal and reduce the contact resistance.

[0069] The thickness of the N-type silicon carbide substrate 101 of the device is 1 μm, and the thickness of the N-type drift layer 102 is 15-25 μm. The thickness is adjusted within the above range according to the different requirements for the withstand voltage characteristics of the device. The thickness of the N-type current balancing layer 103 below the P-type well region 105 is 300 nm, and the thickness of the N-type current balancing layer 103 from the contact area with the source metal layer 108 to the upper side of the drift layer 102 is 900 nm. The contact surface width of the N-type current balancing layer 103 and the source metal layer 108 is 200 nm. -300nm, can be designed individually according to the freewheeling capability of the body diode, the N-type current balancing layer 103 can effectively shield the capacitance effect of the gate to the drain, reduce the gate-drain charge of the device, and improve the switching speed of the device, the thickness of the P-type well region 105 is 600nm, the thickness of the first gate dielectric layer 106 is 20nm, the thickness of the second gate dielectric layer 107 is 30nm, the thickness of the P-type source region 1052 is 300nm, and the thickness of the N-type source region 1051 is 300nm;

[0070] The present invention designs a gate insulating medium to address the gate structure degradation problem during short circuit. The gate dielectric is designed to be two layers, namely a first gate dielectric layer 106 and a second gate dielectric layer 107. The first gate dielectric layer 106 is silicon dioxide to ensure good contact with the silicon carbide interface, reduce the interface state density, and improve the consistency of the device threshold voltage and switching characteristics. The second gate dielectric layer 107 is diamond, which can effectively improve the thermal conductivity and thermal reliability of the insulating medium.

[0071] Since heat accumulates in a very short time when the device is short-circuited, the source metal aluminum of the traditional device is easily melted by the heat and flows toward the gate structure, affecting the reliability of the device. The present invention uses nickel-tungsten alloy for the source metal layer, the drain metal layer and the gate metal layer, effectively improving the metal reliability of the device.

[0072] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a planar gate silicon carbide VDMOS with improved short circuit reliability, characterized in that: The steps include: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal; epitaxially growing a drift layer on the side of the silicon carbide substrate; Step 2, forming a current-balancing layer by ion implantation into the drift layer; Step 3: forming a barrier layer on the drift layer, etching the barrier layer to form a through hole, and performing ion implantation into the current balancing layer to form a P-type well region; Step 4, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the current balancing layer to form a low resistance area; Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the P-type well region to form an N-type source region; Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the P-type well region to form a P-type source region; Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form a first gate dielectric layer; Step 8, depositing to form a second gate dielectric layer, wherein the first gate dielectric layer and the second gate dielectric layer are made of different deposited materials; Step 9, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer; Step 10: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

2. A method for preparing a planar gate silicon carbide VDMOS with improved short circuit reliability as claimed in claim 1, characterized in that: The first gate dielectric layer is silicon dioxide, and the second gate dielectric layer is diamond.

3. The method for preparing a planar gate silicon carbide VDMOS with improved short circuit reliability as claimed in claim 1, characterized in that: The doping concentration of the low resistance region is greater than the doping concentration of the current balancing layer.

4. The method for preparing a planar gate silicon carbide VDMOS with improved short circuit reliability as claimed in claim 1, characterized in that: The thickness of the first gate dielectric layer is smaller than the thickness of the second gate dielectric layer.

5. The method for preparing a planar gate silicon carbide VDMOS with improved short circuit reliability as claimed in claim 1, characterized in that: The thickness of the P-type well region is twice the thickness of the N-type source region.

6. The method for preparing a planar gate silicon carbide VDMOS with improved short circuit reliability as claimed in claim 1, characterized in that: The thickness of the current balancing layer is three times the thickness of the N-type source region.

7. The method for preparing a planar gate silicon carbide VDMOS with improved short circuit reliability as claimed in claim 1, characterized in that: The thickness of the low resistance region is equal to the thickness of the P-type well region.

8. A planar gate silicon carbide VDMOS with improved short circuit reliability, characterized in that: The silicon carbide VDMOS is prepared by any one of the preparation methods of claims 1 to 7.

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