Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for solving the technical problem of mask pattern drift. The manufacturing method comprises the steps that a plurality of mask patterns are formed on a substrate, the substrate is etched with the mask patterns as masks, and a boss and a contact groove surrounding the boss are formed in the substrate; isolation layers are formed on the mask patterns and the side walls of the bosses, the two adjacent mask patterns in the adjacent rows make contact with the isolation layers on the side walls of the corresponding bosses, the isolation layers further enclose a filling hole, and the filling hole exposes the substrate; and forming a first conductive layer in the filling hole, and carrying out annealing treatment on the first conductive layer, the isolation layer, the mask pattern and the substrate. The isolation layer isolates the first conductive layer from the mask pattern, so that the mask pattern is prevented from drifting due to melt flow when the mask pattern and the first conductive layer are annealed. In addition, the adjacent mask patterns in the adjacent rows are in contact with the isolation layers on the side walls of the bosses, and the gaps between the mask patterns with small gaps are filled with the isolation layers.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] With the continuous development of science and technology, the application of semiconductor structures is becoming more and more extensive. In the fields of computers, communications, etc., semiconductor structures with different functions are needed. The semiconductor structure includes a substrate, a mask pattern is formed on the substrate, a conductive layer is filled between the mask patterns, and the conductive layer is in contact with the substrate to form a bit line contact plug (Bit Line Contact, referred to as BLC). In order to ensure the performance of the bit line contact plug, the substrate, the mask pattern and the conductive layer are usually annealed to recrystallize the conductive layer and reduce the voids or gaps inside it. However, after the semiconductor structure is annealed, the mask pattern often drifts, affecting the performance of the semiconductor structure. Summary of the invention

[0003] In view of the above problems, the embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, so as to ensure the profile of the mask pattern and improve the performance of the semiconductor structure.

[0004] According to some embodiments, a first aspect of the present disclosure provides a method for manufacturing a semiconductor structure, comprising:

[0005] A plurality of mask patterns are formed on a substrate and arranged in an array at intervals, wherein in any three adjacent rows of the mask patterns, the distance between two adjacent mask patterns in adjacent rows is smaller than the distance between two adjacent mask patterns in the same row, and smaller than the distance between two mask patterns opposite to each other in alternate rows;

[0006] Using the mask pattern as a mask, etching the substrate to form a boss corresponding to the mask pattern and a contact groove surrounding the boss in the substrate;

[0007] An isolation layer is formed on the sidewall of each of the mask patterns and the bosses, the isolation layers on the sidewalls of two adjacent mask patterns and the corresponding bosses in adjacent rows are in contact with each other, and the isolation layers on the sidewalls of two adjacent mask patterns and the corresponding bosses in one row and on the sidewalls of two mask patterns and the corresponding bosses in alternate rows enclose a filling hole, wherein the filling hole exposes the substrate;

[0008] forming a first conductive layer, wherein the first conductive layer covers the side surfaces of the isolation layer and completely fills the filling hole;

[0009] The first conductive layer, the isolation layer, the mask pattern and the substrate are annealed.

[0010] In some possible embodiments, forming an isolation layer on the sidewalls of each of the mask patterns and the bosses includes:

[0011] forming an initial isolation layer, wherein the initial isolation layer covers the side walls of the mask pattern, the top surface of the mask pattern, and the side walls and bottom walls of the contact groove, and the initial isolation layers on the side walls of two adjacent mask patterns and corresponding bosses in adjacent rows are in contact with each other;

[0012] The initial isolation layer located on the top surface of the mask pattern and the initial isolation layer located on the bottom wall of the contact groove are removed to expose the substrate, and the remaining initial isolation layer forms the isolation layer.

[0013] In some possible embodiments, forming the first conductive layer includes:

[0014] The first conductive layer is deposited on the side surface and the top surface of the isolation layer and the top surface of the mask pattern, the first conductive layer completely fills the filling hole, and the top surface of the first conductive layer is higher than the top surface of the mask pattern.

[0015] In some possible embodiments, before forming the first conductive layer, the method further includes:

[0016] The side surface of the isolation layer of the side wall of the filling hole is thinned to enlarge the filling hole, and the enlarged filling hole is spaced apart from the mask pattern and the boss.

[0017] In some possible embodiments, a plurality of mask patterns that are spaced apart and arranged in an array are formed on a substrate, including:

[0018] Providing a substrate having a plurality of active regions spaced apart from each other;

[0019] The mask pattern is formed on the substrate, the mask pattern covers the end of the active region, and one mask pattern covers the end of two active regions adjacent to each other along a first direction.

[0020] In some possible embodiments, the mask pattern includes a barrier layer, a third conductive layer, and a first protective layer stacked in sequence, and after the first conductive layer, the isolation layer, the mask pattern, and the substrate are annealed, the further comprising:

[0021] performing a planarization process on the top surface of the first conductive layer;

[0022] removing a portion of the isolation layer and the first conductive layer, and retaining the isolation layer and the first conductive layer in the contact groove, so as to expose at least a side wall of the third conductive layer;

[0023] A second conductive layer is formed on the reserved isolation layer and the first conductive layer, wherein the second conductive layer fills the space between adjacent mask patterns and contacts the third conductive layer.

[0024] In some possible embodiments, after forming the second conductive layer, the method further includes:

[0025] Etching and removing a portion of the second conductive layer to expose the top surface and sidewalls of the first protective layer;

[0026] removing the first protective layer to expose the third conductive layer, wherein the top surface of the third conductive layer is flush with the top surface of the second conductive layer;

[0027] forming a fourth conductive layer on the second conductive layer and the third conductive layer, and forming a second protective layer on the fourth conductive layer, wherein the second protective layer, the fourth conductive layer, the third conductive layer and the barrier layer form a bit line layer;

[0028] The bit line layer, the first conductive layer, the second conductive layer and the isolation layer are etched, the bit line layer forms a plurality of bit lines which are spaced apart and extend along the first direction, the first conductive layer and the second conductive layer form a first contact layer, the isolation layer forms a second contact layer, and the second contact layer is located on opposite sides of the first contact layer along the first direction.

[0029] The method for manufacturing a semiconductor structure provided by the embodiment of the present disclosure has at least the following advantages:

[0030] The manufacturing method provided by the embodiment of the present disclosure uses a mask pattern as a mask, etches a substrate to form a boss, forms an isolation layer on the mask pattern and the sidewall of the boss, forms a first conductive layer in the filling hole formed by the isolation layer, and anneals the first conductive layer to improve the holes in the first conductive layer and improve the conductive performance of the first conductive layer. At the same time, the isolation layer isolates the first conductive layer from the mask pattern to prevent the mask pattern and the first conductive layer from melting and flowing to cause the mask pattern to collapse, that is, to prevent the mask pattern from drifting and ensure the contour of the mask pattern.

[0031] In addition, the distance between two adjacent mask patterns in adjacent rows is smaller than the distance between two adjacent mask patterns in the same row, and smaller than the distance between two mask patterns that are opposite to each other in alternate rows. The isolation layers on the side walls of two adjacent mask patterns in adjacent rows and the corresponding bosses are in contact, and the isolation layers on the side walls of two adjacent mask patterns in the same row and the corresponding bosses, and on the side walls of two mask patterns that are opposite to each other in alternate rows, enclose a filling hole. On the one hand, the isolation layer forms a whole, improving the stability of the isolation layer, and on the other hand, the isolation layer fills a smaller gap, and the manufacturing difficulty is low.

[0032] According to some embodiments, a second aspect of the present disclosure provides a semiconductor structure, comprising:

[0033] A substrate, the substrate having a plurality of bosses disposed at intervals and arranged in an array, and contact grooves surrounding the bosses, wherein in any three adjacent rows of the bosses, the distance between two adjacent bosses in an adjacent row is smaller than the distance between two adjacent bosses in the same row, and smaller than the distance between two opposite bosses in alternate rows;

[0034] A bit line contact structure is disposed in the contact groove, wherein the bit line contact structure includes a first contact layer and a second contact layer, wherein the second contact layer is located at two opposite sides of the first contact layer along a first direction and contacts the side wall of the boss.

[0035] In some possible embodiments, the first contact layer includes a first conductive layer and a second conductive layer, the first conductive layer contacts the substrate, the second contact layer is connected to two opposite sides of the first conductive layer along the first direction, the second conductive layer is located on the first conductive layer and the first contact layer, and the top surface of the second conductive layer is higher than the top surface of the substrate.

[0036] In some possible embodiments, the semiconductor structure further includes:

[0037] a plurality of bit lines arranged at intervals and extending along the first direction, each of the bit lines correspondingly contacting a column of the bit line contact structures arranged along the first direction, and each of the bit lines correspondingly contacting a column of the bosses opposite to each other row;

[0038] The bit line includes a blocking layer, a third conductive layer, a fourth conductive layer and a second protective layer, the blocking layer and the third conductive layer are located on the boss and are stacked in sequence, the blocking layer and the third conductive layer are located on opposite sides of the second conductive layer along the first direction and are in contact with the second conductive layer, the fourth conductive layer is located on the second conductive layer and the third conductive layer, and the second protective layer is located on the fourth conductive layer.

[0039] The semiconductor structure provided by the embodiments of the present disclosure has at least the following advantages:

[0040] The semiconductor structure provided by the embodiment of the present disclosure includes a substrate and a bit line contact structure, wherein the substrate has a plurality of spaced bosses and a contact groove surrounding the bosses, wherein the distance between two adjacent bosses in any three adjacent rows of bosses is the smallest. The bit line contact structure is located in the contact groove, and the bit line contact structure includes a first contact layer and a second contact layer, wherein the second contact layer is located on two opposite sides of the first contact layer along a first direction and contacts the side wall of the boss. By providing the second contact layer, the first contact layer is isolated from the boss, thereby preventing the first contact layer from melting and flowing with other film layers, thereby ensuring the contour of the mask pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 is a flow chart of a method for manufacturing a semiconductor structure in an embodiment of the present disclosure;

[0042] Figure 2 It is a schematic diagram after the boss and the contact groove are formed in one embodiment of the present disclosure;

[0043] Figure 3 for Figure 2 Schematic diagram of the cross section at A in the middle;

[0044] Figure 4 It is a schematic diagram after forming an isolation layer in one embodiment of the present disclosure;

[0045] Figure 5 for Figure 4 Schematic diagram of the cross section at A in the middle;

[0046] Figure 6 A schematic diagram after forming a first conductive layer in one embodiment of the present disclosure;

[0047] Figure 7 for Figure 6 Schematic diagram of the cross section at A in the middle;

[0048] Figure 8 Another schematic diagram after forming the first conductive layer in one embodiment of the present disclosure;

[0049] Fig. 9 for Figure 8 Schematic diagram of the cross section at A in the middle;

[0050] Fig.10 This is a schematic diagram after annealing in one embodiment of the present disclosure;

[0051] Fig.11 A process diagram of forming an isolation layer in one embodiment of the present disclosure;

[0052] Fig.12 A process diagram of enlarging a filling hole in an embodiment of the present disclosure;

[0053] Fig.13 It is a schematic diagram of the first conductive layer after being planarized in one embodiment of the present disclosure;

[0054] Fig.14 This is a schematic diagram after a portion of the first conductive layer is removed in one embodiment of the present disclosure;

[0055] Fig.15 Another schematic diagram after a portion of the first conductive layer is removed in one embodiment of the present disclosure;

[0056] Fig.16It is a schematic diagram after a portion of the second conductive layer is formed in one embodiment of the present disclosure;

[0057] Fig.17 This is a schematic diagram of an embodiment of the present disclosure after a portion of the second conductive layer is removed;

[0058] Fig.18 This is a schematic diagram of an embodiment of the present disclosure after the first protective layer is removed;

[0059] Fig.19 It is a schematic diagram after forming a bit line in one embodiment of the present disclosure;

[0060] Fig. 20 for Fig.19 Schematic diagram of the cross section at point A.

[0061] Description of reference numerals:

[0062] 10-substrate; 11-active region;

[0063] 12- boss; 13- contact groove;

[0064] 14-semiconductor substrate; 15-third protective layer;

[0065] 20-mask pattern; 21-blocking layer;

[0066] 22-third conductive layer; 23-first protective layer;

[0067] 30-isolation layer; 31-filling hole;

[0068] 32-initial isolation layer; 40-first conductive layer;

[0069] 50- second conductive layer; 60- fourth conductive layer;

[0070] 70-second protective layer; 81-first contact layer;

[0071] 82-Second contact layer. DETAILED DESCRIPTION

[0072] The semiconductor contact structure in the related art has the problem that the mask pattern is easy to drift. The inventor has found that the reason is that the middle film layer of the mask pattern and the conductive layer are made of the same material, and the conductive properties of the middle film layer and the conductive layer of the mask pattern can be improved by annealing. During annealing, the middle film layer and the conductive layer of the mask pattern melt and flow, causing the top film layer above the middle film layer of the mask pattern to collapse, that is, the top film layer of the mask pattern drifts, and the contour of the mask pattern changes, affecting the alignment of subsequent processes and the performance of the semiconductor structure.

[0073] To this end, the present disclosure provides a semiconductor structure, wherein an isolation layer is formed at least on the sidewall of the mask pattern, thereby isolating the mask pattern from the first conductive layer. The isolation layer limits the mask pattern, preventing the mask pattern and the first conductive layer from melting and flowing during annealing, thereby preventing the mask pattern from drifting, and ensuring the contour of the mask pattern.

[0074] In addition, the distance between two adjacent mask patterns in adjacent rows is smaller than the distance between two adjacent mask patterns in the same row, and smaller than the distance between two mask patterns that are opposite to each other in alternate rows. The isolation layers on the side walls of two adjacent mask patterns in adjacent rows and the corresponding bosses are in contact, and the isolation layers on the side walls of two adjacent mask patterns in the same row and the corresponding bosses, and on the side walls of two mask patterns that are opposite to each other in alternate rows, enclose a filling hole. On the one hand, the isolation layer forms a whole, improving the stability of the isolation layer, and on the other hand, the isolation layer fills a smaller gap, and the manufacturing difficulty is low.

[0075] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0076] See also Figure 1 The present disclosure provides a method for manufacturing a semiconductor structure, which specifically includes the following steps:

[0077] Step S100: forming a plurality of mask patterns that are spaced apart and arranged in an array on a substrate, wherein in any three adjacent rows of mask patterns, a distance between two adjacent mask patterns in adjacent rows is smaller than a distance between two adjacent mask patterns in the same row, and smaller than a distance between two mask patterns that are opposite to each other in alternate rows.

[0078] See also Figure 2 and Figure 3 The substrate 10 provides support for the structure thereon, and may include a semiconductor substrate 14 and a third protective layer 15 covering the semiconductor substrate 14. The third protective layer 15 is provided to prevent the surface of the semiconductor substrate 14 from being exposed and oxidized. The semiconductor substrate 14 may be a silicon substrate, a germanium substrate, a gallium nitride substrate, a silicon on insulator substrate (Silicon On Insulator, SOI for short), etc., and the third protective layer 15 may be a silicon oxide layer.

[0079] The mask pattern 20 is formed on the substrate 10. There are a plurality of mask patterns 20. The plurality of mask patterns 20 are arranged at intervals and in an array, that is, the plurality of mask patterns 20 are arranged in a plurality of rows and columns. The column direction can be a first direction ( Figure 2 The X direction is shown, for example, the bit line extension direction), that is, each column of mask patterns 20 is arranged at intervals along the first direction. The row direction is the second direction ( Figure 2 The Y direction shown is, for example, the word line extension direction), that is, each row of mask patterns 20 is arranged at intervals along the second direction.

[0080] Exemplarily, the mask patterns 20 in adjacent rows are staggered, and the mask patterns 20 in alternate rows that are opposite to each other form a column of mask patterns 20, that is, the mask patterns 20 in alternate rows are arranged opposite to each other along the first direction. The projections of the mask patterns 20 in adjacent rows in the first direction only partially overlap, and the projections of the mask patterns 20 in the first direction completely overlap. A row of mask patterns 20 between the alternate mask patterns 20 is located at the center axis extending along the second direction between the two alternate mask patterns 20, and the mask pattern 20 located at the center axis is located at the center of the four adjacent mask patterns 20 in its adjacent row, so that the multiple mask patterns 20 are arranged approximately in a hexagonal manner, so as to increase the arrangement density of the mask patterns 20, and expose the active areas between the multiple mask patterns 20 to form a bit line contact structure arranged approximately in a hexagonal manner, thereby improving the space utilization of the semiconductor structure.

[0081] In any three adjacent rows of mask patterns 20, the distance between two adjacent mask patterns 20 in adjacent rows is smaller than the distance between two adjacent mask patterns 20 in the same row, and smaller than the distance between two mask patterns 20 opposite to each other in alternate rows. That is, among a plurality of adjacent mask patterns 20, the distance between two adjacent mask patterns 20 in adjacent rows is the smallest, and the aspect ratio is the largest, and the distance between two adjacent mask patterns 20 in the same row and the distance between two mask patterns 20 opposite to each other in alternate rows may be equal.

[0082] Among them, two mask patterns 20 adjacent to each other in adjacent rows refer to a mask pattern 20 in a row of mask patterns 20 and a mask pattern 20 that is closest to the mask pattern 20 in the adjacent row of mask patterns 20. Each mask pattern 20 may be adjacent to one, two or four adjacent rows of mask patterns 20. Mask patterns 20 in the same row are arranged along the second direction, and two mask patterns 20 opposite to each other in alternate rows are arranged along the first direction.

[0083] Step S200: using the mask pattern as a mask, etching the substrate to form a boss corresponding to the mask pattern and a contact groove surrounding the boss in the substrate.

[0084] Continue reading Figure 2 Hehe Figure 3, using the mask pattern 20 as a mask, the exposed substrate 10 is etched to form a boss 12 and a contact groove 13 in the substrate 10. The boss 12 corresponds to the mask pattern 20 to transfer the pattern of the mask pattern 20 to the substrate 10.

[0085] There may be a plurality of bosses 12, and the arrangement of the plurality of bosses 12 is the same as the arrangement of the plurality of mask patterns 20, that is, each boss 12 corresponds to a mask pattern 20 and is located directly below the corresponding mask pattern 20. The contact groove 13 surrounds the boss 12, that is, the boss 12 is located in the contact groove 13, so that the plurality of bosses 12 are spaced apart. The cross section of the boss 12 is a regular trapezoid, and the cross section of the contact groove 13 is an inverted trapezoid.

[0086] Step S300: An isolation layer is formed on the side wall of each mask pattern and boss, the isolation layers on the side walls of two adjacent mask patterns and corresponding bosses in adjacent rows are in contact with each other, and the isolation layers on the side walls of two adjacent mask patterns and corresponding bosses in the same row and on the side walls of two mask patterns and corresponding bosses opposite to each other in alternate rows enclose a filling hole, and the filling hole exposes the substrate.

[0087] See also Figure 4 and Figure 5 , the mask pattern 20 and the boss 12 thereunder are the corresponding mask pattern 20 and boss 12. An isolation layer 30 is deposited on the sidewalls of each mask pattern 20 and boss 12. The top surface of the isolation layer 30 may be flush with the top surface of the mask pattern 20, and the material of the isolation layer 30 may include silicon nitride or silicon nitride oxide. By covering the isolation layer 30 on the sidewalls of the mask pattern 20, the isolation layer 30 surrounds and isolates the mask pattern 20 and provides support, thereby ensuring the independence of the mask pattern 20 during the subsequent annealing process, avoiding the melting drift of the mask pattern 20, and thus ensuring the accuracy of the position and morphology of the mask pattern 20.

[0088] The isolation layer 30 on the side walls of two adjacent mask patterns 20 and corresponding bosses 12 in adjacent rows is in contact, and the isolation layer 30 is filled between the two adjacent mask patterns 20 in adjacent rows, and is filled between the two adjacent bosses 12 in adjacent rows. The isolation layer 30 on the side walls of two adjacent mask patterns 20 and bosses 12 in the same row, and on the side walls of two mask patterns 20 and bosses 12 opposite to each other in alternate rows, encloses a filling hole 31, and the filling hole 31 exposes the substrate 10.

[0089] It can be understood that the corresponding mask pattern 20 and the boss 12 form a column, and the isolation layer 30 is deposited on the side wall of each column, and the isolation layer 30 is filled between two adjacent columns in an adjacent row. The isolation layer 30 on the side walls of two adjacent columns in a row and the isolation layer 30 on the side walls of two opposite columns in alternate rows enclose a filling hole 31.

[0090] By contacting the isolation layer 30 on the side wall of the boss 12 with two adjacent mask patterns 20 in adjacent rows, on the one hand, the isolation layer 30 forms a whole, improving the stability of the isolation layer 30, and ensuring the stability of the overall structure of multiple mask patterns 20. On the other hand, the isolation layer 30 fills the gap between the two adjacent mask patterns 20 and the boss 12 in the adjacent rows, thereby filling up the smaller gap between the adjacent mask patterns 20 and the smaller gap between the adjacent bosses 12, reducing the difficulty of filling.

[0091] Step S400: forming a first conductive layer, wherein the first conductive layer covers the side surfaces of the isolation layer and completely fills the filling hole.

[0092] See also Figure 6 and Figure 7 , at least a first conductive layer 40 is formed in the filling hole 31, for example, the first conductive layer 40 can be formed by an epitaxial growth process, the first conductive layer 40 is in contact with the substrate 10, and covers the side of the isolation layer 30. The first conductive layer 40 fills the filling hole 31 to fill the filling hole 31. The top surface of the first conductive layer 40 can be flush with the top surface of the mask pattern 20 and the top surface of the isolation layer 30, so that the isolation layer 30 isolates the mask pattern 20 and the first conductive layer 40, thereby preventing the mask pattern 20 and the first conductive layer 40 from flowing laterally in the molten state during annealing, and ensuring the accuracy of the position of the mask pattern 20.

[0093] See also Figure 8 and Fig. 9 In some other examples, the first conductive layer 40 may also cover the top surface of the isolation layer 30 and the top surface of the mask pattern 20, that is, forming the first conductive layer 40 includes: depositing the first conductive layer 40 on the side and top surface of the isolation layer 30 and the top surface of the mask pattern 20, the first conductive layer 40 fills the filling hole 31, and the top surface of the first conductive layer 40 is higher than the top surface of the mask pattern 20, so as to facilitate the formation of the first conductive layer 40.

[0094] In the above example, the isolation layer 30 can support the mask pattern 20 and prevent the mask pattern 20 and the first conductive layer 40 from flowing laterally when in a molten state, so as to define the position of the mask pattern 20 and avoid the mask pattern 20 from shifting, thereby avoiding alignment problems in subsequent processes. The mask pattern 20 and the first conductive layer 40 above the isolation layer 30 are the entire film layer, and the flow of the mask pattern 20 when molten has no effect on the mask pattern 20.

[0095] The material of the first conductive layer 40 includes polysilicon, and the mask pattern 20 can be a stacked structure. The material of the middle film layer in the stacked structure is the same as the material of the first conductive layer 40, for example, a polysilicon layer, and the material of the middle film layer in the stacked structure can be undoped polysilicon, and the material of the first conductive layer is doped polysilicon, so that the first conductive layer 40 and the middle film layer are isolated by using the isolation layer 30 and the top film layer above the middle film layer, so that the isolation effect is good, and the effect of preventing the mask pattern 20 from drifting is good.

[0096] For example, Fig. 9 As shown, the mask pattern 20 includes a barrier layer 21, a third conductive layer 22 and a first protective layer 23 stacked in sequence, and the barrier layer 21 is located on the substrate 10. The material of the third conductive layer 22 is the same as that of the first conductive layer 40. The first conductive layer 40 and the third conductive layer 22 of the same material are completely isolated by the isolation layer 30 and the first protective layer 23, and the two will not contact each other in the molten state, thereby preventing the third conductive layer 22 from drifting, and the position of the mask pattern 20 is accurate. Among them, the material of the barrier layer 21 can be nitride or oxide, such as silicon nitride and silicon oxide, and the material of the first protective layer 23 can be oxide, such as silicon oxide.

[0097] Step S500: performing annealing treatment on the first conductive layer, the isolation layer, the mask pattern and the substrate.

[0098] Laser annealing is performed on the first conductive layer 40, the isolation layer 30, the mask pattern 20 and the substrate 10, and the internal holes of the first conductive layer 40 are improved by melting and recrystallization, so as to improve the conductivity of the first conductive layer 40 and reduce the resistance between the first conductive layer 40 and the substrate 10. At the same time, the isolation layer 30 is used to isolate the first conductive layer 40 and the mask pattern 20, so as to prevent the middle part of the mask pattern 20 from flowing together with the first conductive layer 40 and causing the top of the mask pattern 20 to collapse, that is, to prevent the mask pattern 20 from drifting, and to ensure the contour of the mask pattern 20.

[0099] In summary, the manufacturing method in the embodiment of the present disclosure uses the mask pattern 20 as a mask, etches the substrate 10 to form the boss 12, forms an isolation layer 30 on the sidewalls of the mask pattern 20 and the boss 12, forms a first conductive layer 40 in the filling hole 31 enclosed by the isolation layer 30, and anneals the first conductive layer 40 to improve the holes in the first conductive layer 40 and improve the conductive performance of the first conductive layer 40. At the same time, the isolation layer 30 isolates the first conductive layer 40 from the mask pattern 20 to prevent the mask pattern 20 and the first conductive layer 40 from melting and flowing to cause the mask pattern 20 to collapse, that is, to prevent the mask pattern 20 from drifting, and to ensure the contour of the mask pattern 20.

[0100] In addition, the distance between two adjacent mask patterns 20 in adjacent rows is smaller than the distance between two adjacent mask patterns 20 in the same row, and smaller than the distance between two mask patterns 20 opposite to each other in alternate rows. The isolation layers 30 on the side walls of two adjacent mask patterns 20 in adjacent rows and the corresponding bosses 12 are in contact, and the isolation layers 30 on the side walls of two adjacent mask patterns 20 in the same row and the corresponding bosses 12, as well as on the side walls of two mask patterns 20 opposite to each other in alternate rows, enclose the filling holes 31. On the one hand, the isolation layers 30 form a whole, improving the stability of the isolation layers 30. On the other hand, the isolation layers 30 fill the smaller gaps, and the manufacturing difficulty is low. Since the smaller gaps are filled by the isolation layers 30, the poor filling of the conductive material in the smaller gaps can be avoided, and the conductive material remaining in the gaps after etching to form the bit lines can be avoided, and the leakage problem caused by the residual conductive material can be avoided.

[0101] In some possible implementations, forming a plurality of mask patterns 20 spaced apart and arranged in an array on a substrate 10 (step S100) includes:

[0102] Step S101: providing a substrate 10 , wherein the substrate 10 has a plurality of active regions 11 disposed at intervals.

[0103] like Figure 2 and Figure 3 As shown, the substrate 10 has a plurality of active areas 11 (Active Area, referred to as AA), and the plurality of active areas 11 are arranged at intervals. For example, the semiconductor substrate 14 of the substrate 10 includes a plurality of active areas 11, and a shallow trench isolation (Shallow Trench Isolation, referred to as STI) structure isolating each active area 11, and the active area 11 is used to form a source area, a drain area, and a channel area of ​​a transistor. The third protective layer 15 covers the active area 11 and the shallow trench isolation structure, and the shallow trench isolation structure can be formed in the same deposition process as the third protective layer 15.

[0104] Step S102: forming a mask pattern 20 on the substrate 10, wherein the mask pattern 20 covers the ends of the active regions 11, and one mask pattern 20 covers the ends of two active regions 11 adjacent to each other along the first direction.

[0105] By deposition and etching, a plurality of mask patterns 20 arranged at intervals are formed on the substrate 10. Each mask pattern 20 covers the end of the active area 11, and the ends of two active areas 11 adjacent to each other along the first direction are covered with a mask pattern 20, so that each mask pattern 20 covers at least the end of one active area 11. The active areas 11 and the mask patterns 20 located in the same column along the direction are alternately arranged in sequence.

[0106] For some examples, see Figure 3 and Fig.11, forming an isolation layer 30 on the sidewalls of each mask pattern 20 and the boss 12 (step S300), comprising:

[0107] S301: forming an initial isolation layer 32, the initial isolation layer 32 covers the side walls of the mask pattern 20, the top surface of the mask pattern 20, and the side walls and bottom walls of the contact groove 13, and the initial isolation layers 32 on the side walls of two adjacent mask patterns 20 and the corresponding bosses 12 in adjacent rows are in contact with each other.

[0108] An initial isolation layer 32 is deposited on the sidewalls and top surface of the mask pattern 20 and the sidewalls and bottom wall of the contact groove 13 , wherein the sidewalls of the contact groove 13 are the sidewalls of the boss 12 , and the bottom wall of the contact groove 13 is the substrate 10 exposed between the bosses 12 .

[0109] The initial isolation layers 32 on two adjacent mask patterns 20 in adjacent rows are in contact with each other, the initial isolation layers 32 on two adjacent bosses 12 in adjacent rows are in contact with each other, and the initial isolation layer 32 on the mask pattern 20 is adapted to the initial isolation layer 32 on the corresponding boss 12, that is, the initial isolation layer 32 on the mask pattern 20 and the initial isolation layer 32 on the corresponding boss 12 have the same shape and thickness.

[0110] S302 : removing the initial isolation layer 32 located on the top surface of the mask pattern 20 and the initial isolation layer 32 located on the bottom wall of the contact groove 13 to expose the substrate 10 , and the remaining initial isolation layer 32 forms the isolation layer 30 .

[0111] The initial isolation layer 32 located on the top surface of the mask pattern 20 and the bottom wall of the contact groove 13 is removed by etching, exposing the top surface of the mask pattern 20 and the substrate 10. The remaining initial isolation layer 32 covers the sidewalls of the mask pattern 20 and the sidewalls of the boss 12, and the remaining initial isolation layer 32 forms the isolation layer 30. The isolation layer 30 is formed by deposition and etching back.

[0112] In order to increase the area of ​​the substrate 10 exposed in the filling hole 31, increase the contact area between the first conductive layer 40 and the substrate 10, and reduce the contact resistance between the first conductive layer 40 and the substrate 10, refer to Fig.12 Before forming the first conductive layer 40 (step S400), the method further includes: thinning the side surface of the isolation layer 30 of the side wall of the filling hole 31 to expand the filling hole 31, and the expanded filling hole 31 is spaced apart from the mask pattern 20 and the boss 12.

[0113] The isolation layer 30 on the side wall of the filling hole 31 is etched to thin the side of the isolation layer 30, reduce the thickness of the isolation layer 30, and expand the volume of the filling hole 31, so that the area of ​​the substrate 10 exposed in the filling hole 31 is increased. The mask pattern 20 and the boss 12 are not exposed in the enlarged filling hole 31, and the enlarged filling hole 31 is spaced apart from the mask pattern 20, and the enlarged filling hole 31 is spaced apart from the boss 12, that is, the thinned isolation layer 30 still covers the side wall of the mask pattern 20 and the side wall of the boss 12.

[0114] For some examples, see Fig.10 and Fig.13 The mask pattern 20 includes a barrier layer 21, a third conductive layer 22 and a first protective layer 23 which are stacked in sequence. After the first conductive layer 40, the isolation layer 30, the mask pattern 20 and the substrate 10 are annealed (step S500), the method further includes:

[0115] Step S600: performing a planarization process on the top surface of the first conductive layer.

[0116] The top surface of the first conductive layer 40 is planarized, for example, chemical mechanical grinding is performed on the top surface of the first conductive layer 40. After annealing, the top surface of the first conductive layer 40 is rough. By planarizing the top surface of the first conductive layer 40, the roughness of the top surface of the first conductive layer 40 can be reduced, so that the top surface of the first conductive layer 40 is flat. After the first conductive layer 40 is etched back, the top surface of the remaining first conductive layer 40 is relatively flat.

[0117] In step S700 , a portion of the isolation layer and the first conductive layer is removed, and the isolation layer and the first conductive layer located in the contact groove are retained to expose at least the side wall of the third conductive layer.

[0118] See also Fig.14 , a portion of the isolation layer 30 and a portion of the first conductive layer 40 are etched away, and the remaining isolation layer 30 and the first conductive layer 40 are at least filled in the contact groove 13 and at least the side wall of the third conductive layer 22 is exposed.

[0119] For example, Fig.14 As shown, the retained isolation layer 30 and the retained first conductive layer 40 are only filled in the contact groove 13 , and the top surfaces of the retained isolation layer 30 and the retained first conductive layer 40 are flush with the top surface of the substrate 10 .

[0120] For example, see Fig.15The reserved isolation layer 30 and the reserved first conductive layer 40 are filled in the contact groove 13 and between the barrier layers 21. The top surfaces of the reserved isolation layer 30 and the first conductive layer 40 are flush with the top surface of the barrier layer 21, so that the isolation layer 30 is in contact with the side surface of the barrier layer 21. When the isolation layer 30 and the barrier layer 21 are made of the same material, the isolation layer 30 and the barrier layer 21 are integrated, which has a better isolation and barrier effect.

[0121] Step S800: forming a second conductive layer on the retained isolation layer and the first conductive layer, wherein the second conductive layer fills the space between adjacent mask patterns and contacts the third conductive layer.

[0122] See also Fig.16 , a second conductive layer 50 is formed on the retained isolation layer 30 and the first conductive layer 40, the second conductive layer 50 fills between adjacent mask patterns 20 and contacts the third conductive layer 22, so as to subsequently form a contact plug connecting the bit line and the substrate 10. The top surface of the second conductive layer 50 may be flush with the top surface of the first protective layer 23, or the top surface of the second conductive layer 50 may be higher than the top surface of the first protective layer 23. The material of the second conductive layer 50 may be doped polysilicon to reduce the contact resistance between the second conductive layer 50 and the bit line layer thereon.

[0123] For some examples, see Figures 17 to 20 After forming the second conductive layer 50 (step S800), the method further includes:

[0124] S900: etching and removing a portion of the second conductive layer to expose the top surface and sidewalls of the first protective layer.

[0125] See also Fig.16 and Fig.17 , the second conductive layer 50 between the first protection layers 23 is removed by etching to expose the first protection layers 23 , that is, the top surface and the sidewall of the first protection layer 23 are exposed.

[0126] S1000: removing the first protection layer to expose the third conductive layer, wherein the top surface of the third conductive layer is flush with the top surface of the second conductive layer.

[0127] See also Fig.17 and Fig.18 The exposed first protection layer 23 is etched away to expose the third conductive layer 22 . The top surface of the third conductive layer 22 is flush with the top surface of the second conductive layer 50 to form a flat surface, so as to form a bit line layer on the third conductive layer 22 and the second conductive layer 50 .

[0128] S1100: forming a fourth conductive layer on the second conductive layer and the third conductive layer, and forming a second protective layer on the fourth conductive layer, the second protective layer, the fourth conductive layer, the third conductive layer and the barrier layer forming a bit line layer.

[0129] See also Fig.19 and Fig. 20 , a fourth conductive layer 60 is formed on the second conductive layer 50 and the third conductive layer 22, and a second protective layer 70 is formed on the fourth conductive layer 60. The second protective layer 70, the fourth conductive layer 60, the third conductive layer 22 and the barrier layer 21 form a bit line layer. The fourth conductive layer 60 may be a stacked layer, for example, including a diffusion barrier layer 21 and a metal layer located on the diffusion barrier layer 21.

[0130] S1200: Etching the bit line layer, the first conductive layer, the second conductive layer and the isolation layer, the bit line layer forms a plurality of bit lines which are spaced apart and extend along a first direction, the first conductive layer and the second conductive layer form a first contact layer, the isolation layer forms a second contact layer, and the second contact layer is located on two opposite sides of the first contact layer along the first direction.

[0131] Continue reading Fig.19 and Fig. 20 , etching the bit line layer, the first conductive layer 40, the second conductive layer 50 and the isolation layer 30, the bit line layer forms a plurality of bit lines, the plurality of bit lines are arranged at intervals and extend along the first direction. The retained isolation layer 30 forms a second contact layer 82, the second contact layer 82 is located on the two opposite sides of the retained first conductive layer 40 along the first direction, and the retained second conductive layer 50 is located on the retained first conductive layer 40 and the second contact layer 82. The retained first conductive layer 40 and the retained second conductive layer 50 form a first contact layer 81, the first contact layer 81 is connected to the second contact layer 82 on the two opposite sides along the first direction, and the second contact layer 82 contacts the side wall of the boss 12. Along the first direction. The two ends of the second contact layer 82 and the first contact layer 81 are aligned respectively.

[0132] The present disclosure also provides a semiconductor structure. Figure 2 , Figure 3 , Fig.19 and Fig. 20 The semiconductor structure includes a substrate 10 and a bit line contact structure. The substrate 10 has a plurality of bosses 12 and a contact groove 13 surrounding the plurality of bosses 12, that is, the plurality of bosses 12 are arranged in the contact groove 13. The plurality of bosses 12 are arranged at intervals and arranged in an array. In any three adjacent rows of bosses 12, the distance between two adjacent bosses 12 in the adjacent row is smaller than the distance between two adjacent bosses 12 in the same row, and smaller than the distance between two bosses 12 opposite to each other in alternate rows.

[0133] In some examples, the mask pattern 20 is aligned along the second direction ( Figure 2 The mask patterns 20 in adjacent rows are arranged in a staggered manner, and the mask patterns 20 in alternate rows relative to each other are arranged in a first direction ( Figure 2The mask patterns 20 are arranged in a row (in the X direction as shown) to form a row of mask patterns 20, that is, the alternate mask patterns 20 are arranged relatively along the first direction. A row of mask patterns 20 between the alternate mask patterns 20 is located at the center axis position of the two alternate mask patterns 20, and the mask pattern 20 located at the center axis position is located at the center position of the four adjacent mask patterns 20 in its adjacent row, so that the multiple mask patterns 20 are arranged in a hexagonal manner, so as to increase the arrangement density of the mask patterns 20 and improve the space utilization rate of the semiconductor structure.

[0134] The mask pattern 20 corresponds to the boss 12. Each boss 12 is provided with a mask pattern 20, and the corresponding mask pattern 20 is aligned with the boss 12. In some examples, the mask pattern 20 includes a barrier layer 21 and a third conductive layer 22 provided on the barrier layer 21.

[0135] The bit line contact structure is disposed in the contact groove 13 and connected between two adjacent bosses 12 along the first direction, that is, along the first direction, the bit line contact structure and the bosses 12 are connected alternately in sequence. The top surface of the bit line contact structure is higher than the top surface of the boss 12, that is, the bit line contact structure also extends outside the contact groove 13, and the top surface of the bit line contact structure is higher than the top surface of the substrate 10.

[0136] The bit line contact structure includes a first contact layer 81 and a second contact layer 82, wherein the first contact layer 81 is located on two opposite sides of the first contact layer 81 along the first direction, and the first contact layer 81 contacts the side wall of the boss 12. Along the first direction, the side surfaces of the first contact layer 81 and the second contact layer 82 are flush. The top surface of the first contact layer 81 is lower than the top surface of the second contact layer 82, and the top surface of the second contact layer 82 is higher than the top surface of the substrate 10. The material of the first contact layer 81 may be nitride, such as silicon nitride.

[0137] The first contact layer 81 includes a first conductive layer 40 and a second conductive layer 50. The second contact layer 82 is disposed on two opposite sides of the first conductive layer 40 along the first direction. The first conductive layer 40 contacts the substrate 10. The second conductive layer 50 is located on the first conductive layer 40 and the second contact layer 82, and the top surface of the second conductive layer 50 is higher than the top surface of the substrate 10.

[0138] like Fig. 20As shown, along the first direction, the second contact layers 82 are connected to the opposite sides of the first conductive layer 40, and the second contact layers 82 are in contact with the side walls of the boss 12. That is, the opposite sides of two adjacent bosses 12 along the first direction are both connected to the second contact layers 82, and the first conductive layer 40 is connected between the two second contact layers 82. The second conductive layer 50 is located above the second contact layer 82 and the first conductive layer 40, and the second conductive layer 50 extends outside the contact groove 13. The top surfaces of the first conductive layer 40 and the second contact layer 82 are not higher than the bottom surface of the third conductive layer 22, for example, the top surfaces of the first conductive layer 40 and the second contact layer 82 are flush with the top surface of the substrate 10 or flush with the top surface of the barrier layer 21.

[0139] The semiconductor structure further includes a plurality of bit lines arranged at intervals and extending along the first direction, each bit line correspondingly contacts a column of bit line contact structures arranged along the first direction, and each bit line correspondingly contacts a column of bosses 12 opposite to each other. The bit line includes a barrier layer 21, a third conductive layer 22, a fourth conductive layer 60 and a second protective layer 70.

[0140] The barrier layer 21 is located on the boss 12, the third conductive layer 22 is located on the barrier layer 21, and the third conductive layer 22 and the barrier layer 21 are located on opposite sides of the second conductive layer 50 along the first direction, and the third conductive layer 22 and the barrier layer 21 are both in contact with the second conductive layer 50. The third conductive layer 22 and the second conductive layer 50 are connected as a whole along the first direction, and the top surfaces of the third conductive layer 22 and the second conductive layer 50 are flush. The first conductive layer 40 is doped polysilicon to reduce the contact resistance between the first conductive layer 40 and the substrate 10, and the materials of the first conductive layer 40, the second conductive layer 50 and the third conductive layer 22 can be the same.

[0141] The fourth conductive layer 60 is located on the third conductive layer 22 and the second conductive layer 50, and the second protective layer 70 is located on the fourth conductive layer 60. The fourth conductive layer 60 may be a stacked layer including a diffusion barrier layer 21 and a metal layer located on the diffusion barrier layer 21, and the second protective layer 70 may be made of nitride.

[0142] In summary, the semiconductor structure in the embodiment of the present disclosure includes a substrate 10 and a bit line contact structure, wherein the substrate 10 has a plurality of spaced bosses 12 and a contact groove 13 surrounding the bosses 12, wherein in any three adjacent rows of bosses 12, the distance between two adjacent bosses 12 in adjacent rows is the smallest. The bit line contact structure is located in the contact groove 13, and the bit line contact structure includes a first contact layer 81 and a second contact layer 82, wherein the second contact layer 82 is located on opposite sides of the first contact layer 81 along the first direction and contacts the sidewalls of the bosses 12. By providing the second contact layer 82, the first contact layer 81 is isolated from the bosses 12, thereby preventing the first contact layer 81 from melting and flowing with other film layers, thereby ensuring the contour of the mask pattern 20.

[0143] In this specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referenced to each other. The description of reference terms such as "one implementation", "some implementations", "illustrative implementations", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the implementation or example are included in at least one implementation or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same implementation or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more implementations or examples in a suitable manner.

[0144] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: A plurality of mask patterns are formed on a substrate and arranged in an array at intervals, wherein in any three adjacent rows of the mask patterns, the distance between two adjacent mask patterns in adjacent rows is smaller than the distance between two adjacent mask patterns in the same row, and smaller than the distance between two mask patterns opposite to each other in alternate rows; Using the mask pattern as a mask, etching the substrate to form a boss corresponding to the mask pattern and a contact groove surrounding the boss in the substrate; An isolation layer is formed on the sidewall of each of the mask patterns and the bosses, the isolation layers on the sidewalls of two adjacent mask patterns and the corresponding bosses in adjacent rows are in contact with each other, and the isolation layers on the sidewalls of two adjacent mask patterns and the corresponding bosses in one row and on the sidewalls of two mask patterns and the corresponding bosses in alternate rows enclose a filling hole, wherein the filling hole exposes the substrate; forming a first conductive layer, wherein the first conductive layer covers the side surfaces of the isolation layer and completely fills the filling hole; The first conductive layer, the isolation layer, the mask pattern and the substrate are annealed.

2. The method according to claim 1, characterized in that: Forming an isolation layer on the sidewalls of each of the mask patterns and the bosses, comprising: forming an initial isolation layer, wherein the initial isolation layer covers the side walls of the mask pattern, the top surface of the mask pattern, and the side walls and bottom walls of the contact groove, and the initial isolation layers on the side walls of two adjacent mask patterns and corresponding bosses in adjacent rows are in contact with each other; The initial isolation layer located on the top surface of the mask pattern and the initial isolation layer located on the bottom wall of the contact groove are removed to expose the substrate, and the remaining initial isolation layer forms the isolation layer.

3. The method according to claim 1, characterized in that: Forming a first conductive layer includes: The first conductive layer is deposited on the side surface and the top surface of the isolation layer and the top surface of the mask pattern, the first conductive layer completely fills the filling hole, and the top surface of the first conductive layer is higher than the top surface of the mask pattern.

4. The production method according to any one of claims 1 to 3, characterized in that: Before forming the first conductive layer, the method further includes: The side surface of the isolation layer of the side wall of the filling hole is thinned to enlarge the filling hole, and the enlarged filling hole is spaced apart from the mask pattern and the boss.

5. The production method according to any one of claims 1 to 3, characterized in that: A plurality of mask patterns which are spaced apart and arranged in an array are formed on a substrate, including: Providing a substrate having a plurality of active regions spaced apart from each other; The mask pattern is formed on the substrate, the mask pattern covers the end of the active region, and one mask pattern covers the end of two active regions adjacent to each other along a first direction.

6. The method according to claim 5, characterized in that: The mask pattern includes a barrier layer, a third conductive layer and a first protective layer stacked in sequence, and after the first conductive layer, the isolation layer, the mask pattern and the substrate are annealed, the method further includes: performing a planarization process on the top surface of the first conductive layer; removing a portion of the isolation layer and the first conductive layer, and retaining the isolation layer and the first conductive layer in the contact groove, so as to expose at least a side wall of the third conductive layer; A second conductive layer is formed on the reserved isolation layer and the first conductive layer, wherein the second conductive layer fills the space between adjacent mask patterns and contacts the third conductive layer.

7. The manufacturing method according to claim 6, characterized in that: After forming the second conductive layer, the method further includes: Etching and removing a portion of the second conductive layer to expose the top surface and sidewalls of the first protective layer; removing the first protective layer to expose the third conductive layer, wherein the top surface of the third conductive layer is flush with the top surface of the second conductive layer; forming a fourth conductive layer on the second conductive layer and the third conductive layer, and forming a second protective layer on the fourth conductive layer, wherein the second protective layer, the fourth conductive layer, the third conductive layer and the barrier layer form a bit line layer; The bit line layer, the first conductive layer, the second conductive layer and the isolation layer are etched, the bit line layer forms a plurality of bit lines which are spaced apart and extend along the first direction, the first conductive layer and the second conductive layer form a first contact layer, the isolation layer forms a second contact layer, and the second contact layer is located on opposite sides of the first contact layer along the first direction.

8. A semiconductor structure, characterized in that: include: A substrate, the substrate having a plurality of bosses disposed at intervals and arranged in an array, and contact grooves surrounding the bosses, wherein in any three adjacent rows of the bosses, the distance between two adjacent bosses in an adjacent row is smaller than the distance between two adjacent bosses in the same row, and smaller than the distance between two opposite bosses in alternate rows; A bit line contact structure is disposed in the contact groove, wherein the bit line contact structure includes a first contact layer and a second contact layer, wherein the second contact layer is located at two opposite sides of the first contact layer along a first direction and contacts the side wall of the boss.

9. The semiconductor structure according to claim 8, characterized in that: The first contact layer includes a first conductive layer and a second conductive layer, the first conductive layer contacts the substrate, the second contact layer is connected to two opposite sides of the first conductive layer along the first direction, the second conductive layer is located on the first conductive layer and the first contact layer, and the top surface of the second conductive layer is higher than the top surface of the substrate.

10. The semiconductor structure according to claim 9, characterized in that: The semiconductor structure further comprises: a plurality of bit lines arranged at intervals and extending along the first direction, each of the bit lines correspondingly contacting a column of the bit line contact structures arranged along the first direction, and each of the bit lines correspondingly contacting a column of the bosses opposite to each other row; The bit line includes a blocking layer, a third conductive layer, a fourth conductive layer and a second protective layer, the blocking layer and the third conductive layer are located on the boss and are stacked in sequence, the blocking layer and the third conductive layer are located on opposite sides of the second conductive layer along the first direction and are in contact with the second conductive layer, the fourth conductive layer is located on the second conductive layer and the third conductive layer, and the second protective layer is located on the fourth conductive layer.

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