Semiconductor packaging structure and packaging method

Abstract

The invention relates to a semiconductor packaging structure and a packaging method. The semiconductor packaging structure comprises a substrate, a plurality of chips and a plurality of insulating dielectric layers, the plurality of chips are stacked on the substrate layer by layer; the plurality of insulating dielectric layers are simultaneously filled in the gaps between the chips at the bottom and the substrate and the gaps between the adjacent chips; wherein at least part of the edge of each chip is provided with a chamfer; and the plurality of insulating medium layers extend to an inclined surface formed by the chamfer. Therefore, in the process of forming the insulating dielectric layer, the filling material can fill the gaps between the chips and the substrate and between the adjacent chips more easily. Meanwhile, the contact area of the insulating dielectric layer and the chip can be increased, the binding force between the chip and the insulating dielectric layer is improved, the layering risk of the semiconductor packaging structure is reduced, and the reliability of the packaging structure is improved.

Description

Technical Field

[0001] The present disclosure relates to the semiconductor field, and in particular to a semiconductor packaging structure and a packaging method. Background Art

[0002] Molded Underfill is a technology that integrates underfill and injection molding processes, with the advantages of high output and low cost. However, as the integration level and I / O density gradually increase, the gap between adjacent bumps is getting smaller and smaller, which brings great challenges to the filling effect of molded underfill technology, and defects such as filling voids and flow marks may occur.

[0003] For example, the bump space of high bandwidth memory products (HBM) is less than 20um, and the number of bumps in high bandwidth memory products generally reaches tens of thousands. The solution in the related art is mainly to balance the flow resistance caused by the dense arrangement of bumps by increasing the clamping pressure in the compression mold process. However, the increase in clamping pressure will also increase the risk of wafer splitting. Therefore, increasing the clamping pressure is not a safe and effective solution. Summary of the invention

[0004] In view of this, the embodiments of the present disclosure provide a semiconductor packaging structure and a packaging method to improve the filling capability of the bottom filling technology and enhance the reliability of the packaging.

[0005] The technical solution of the present invention is achieved in this way:

[0006] The present embodiment discloses a semiconductor packaging structure, including: a substrate, multiple chips and multiple insulating dielectric layers; multiple chips are stacked layer by layer on the substrate; multiple insulating dielectric layers are simultaneously filled in the gap between the bottom chip and the substrate, and the gap between adjacent chips; wherein at least part of the edge of each chip is provided with a chamfer; multiple insulating dielectric layers all extend to the inclined surface formed by the chamfer.

[0007] In the above solution, the linear dimension of the chamfer along the stacking direction is less than or equal to the thickness of the chip.

[0008] In the above solution, for each chip, the inclined surface formed by the chamfer faces the substrate.

[0009] In the above solution, for the chip at the bottom, the inclined surface formed by the chamfer faces away from the substrate;

[0010] For the remaining chips, the inclined surfaces formed by the chamfers all face the substrate.

[0011] In the above scheme, the semiconductor packaging structure also includes: multiple connection structures; the chip and substrate located at the bottom, and every two adjacent chips are connected by multiple connection structures; wherein the volume of the connection structure between the chip at the bottom and the substrate is larger than the volume of the connection structure between adjacent chips.

[0012] In the above solution, each chip includes: a first region and a second region; the distribution density of the connection structure in the first region is greater than that in the second region; for each chip, a chamfer is set at the edge corresponding to the first region.

[0013] In the above solution, the chamfer angle ranges from 50 to 70 degrees.

[0014] In the above scheme, among the multiple chips, the front side of the 2n-1th chip is bonded to the front side of the 2nth chip, and the back side of the 2nth chip is bonded to the back side of the 2n+1th chip; n is a positive integer; and the back side of the 1st chip is bonded to the substrate.

[0015] The embodiment of the present disclosure also discloses a semiconductor packaging method, including: providing a substrate and a wafer; cutting the wafer to obtain multiple chips; wherein at least part of the edge of each chip is chamfered; stacking multiple chips layer by layer on the substrate; and simultaneously filling the gap between the bottom chip and the substrate, as well as the gap between adjacent chips, to form multiple insulating dielectric layers; wherein the multiple insulating dielectric layers extend to the inclined surface formed by the chamfer.

[0016] In the above scheme, the wafer is cut to obtain multiple chips, including: cutting the chip along the front side of the wafer; the front side of the chip and the chamfered surface have the same orientation; or, cutting the chip along the back side of the wafer; the front side of the chip and the chamfered surface have opposite orientations.

[0017] In the above scheme, the wafer is cut to obtain a plurality of chips, and the method further includes: cutting the wafer with a narrow knife; wherein the cutting depth of the narrow knife corresponds to the linear dimension of the chamfer; and cutting the wafer with a flat knife to obtain a plurality of chips.

[0018] In the above scheme, the semiconductor packaging method also includes: stacking multiple chips layer by layer on the substrate; connecting the bottom chip and the substrate, as well as adjacent chips, through multiple partially welded connection structures; filling the gap between the bottom chip and the substrate, as well as the gap between adjacent chips, to form multiple insulating medium layers; performing reflow soldering on the multiple partially welded connection structures to form multiple fully welded connection structures; wherein the length of the partially welded connection structure is greater than the length of the fully welded connection structure.

[0019] In the above scheme, the heating peak temperature of the reflow soldering process is higher than the heating temperature of the partially soldered connection structure; and the heating time of the reflow soldering process is longer than the heating time of the partially soldered connection structure.

[0020] In the above scheme, each chip includes: a first area and a second area; the distribution density of the connection structure in the first area is greater than the distribution density in the second area; the wafer is cut to obtain multiple chips, and it also includes: removing the metal and dielectric layers in the cutting area on the wafer; forming a patterned hard mask on the front or back side of the wafer to expose the edge corresponding to the first area to form an etching window; performing wet etching according to the patterned hard mask to form a chamfer at the position corresponding to the etching window; and cutting the wafer along the cutting area to obtain multiple chips.

[0021] The embodiment of the present disclosure discloses a semiconductor packaging structure, including: a substrate, a plurality of chips and a plurality of insulating dielectric layers; a plurality of chips, stacked layer by layer on the substrate; a plurality of insulating dielectric layers, which are simultaneously filled in the gap between the bottom chip and the substrate, and the gap between adjacent chips; wherein at least part of the edge of each chip is provided with a chamfer; and a plurality of insulating dielectric layers extend to the inclined surface formed by the chamfer. In this way, in the process of forming the insulating dielectric layer, the bell-mouth structure formed by the chamfer of the chip in the embodiment of the present disclosure and the chamfer of the substrate or the adjacent chip can add thrust to the filling material when the filling material of the dielectric layer of the insulating layer flows, and then, when the external clamping pressure remains unchanged, the filling material can more easily fill the gap between the chip and the substrate and the adjacent chips, thereby improving the filling effect of the semiconductor packaging structure. At the same time, due to the setting of the chamfer, the contact area between the insulating dielectric layer and the chip in the stacking direction is larger, and then, the bonding force between the chip and the insulating dielectric layer can be increased, thereby reducing the risk of delamination of the semiconductor packaging structure and improving the reliability of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of a semiconductor package structure provided in an embodiment of the present disclosure Figure 1 ;

[0023] Figure 2 A schematic diagram of the structure of a compression mold provided by an embodiment of the present disclosure;

[0024] Figure 3 A schematic diagram of a semiconductor package structure provided in an embodiment of the present disclosure Figure 2 ;

[0025] Figure 4A A schematic diagram of a semiconductor packaging structure of a related art;

[0026] Figure 4BA schematic diagram of a semiconductor package structure provided in an embodiment of the present disclosure Figure 3 ;

[0027] Figure 5 A fourth structural diagram of a semiconductor packaging structure provided by an embodiment of the present disclosure;

[0028] Figure 6 A schematic diagram of the structure of a chip provided in an embodiment of the present disclosure;

[0029] Figure 7 The process of the semiconductor packaging method provided by the embodiment of the present disclosure Figure 1 ;

[0030] Figure 8 Schematic diagram of the structure of the wafer provided in the embodiment of the present disclosure Figure 1 ;

[0031] Fig. 9 A schematic diagram of a semiconductor packaging method provided by an embodiment of the present disclosure Figure 1 ;

[0032] Fig. 10A A schematic diagram of a semiconductor packaging method provided by an embodiment of the present disclosure Figure 2 ;

[0033] Fig. 10B A schematic diagram of a semiconductor packaging method provided by an embodiment of the present disclosure Figure 3 ;

[0034] Fig.11A Schematic diagram 4 of a semiconductor packaging method provided by an embodiment of the present disclosure;

[0035] Fig. 11B A schematic diagram of a semiconductor packaging method provided by an embodiment of the present disclosure Figure 5 ;

[0036] Fig. 12A A schematic diagram of a semiconductor packaging method provided by an embodiment of the present disclosure Figure 6 ;

[0037] Fig. 12B A schematic diagram of a semiconductor packaging method provided by an embodiment of the present disclosure Figure 7 ;

[0038] Fig.13 The process of the semiconductor packaging method provided by the embodiment of the present disclosure Figure 2 ;

[0039] Fig.14A A schematic diagram of a semiconductor packaging method provided by an embodiment of the present disclosure Figure 8 ;

[0040] Fig. 14BA schematic diagram of a semiconductor packaging method provided by an embodiment of the present disclosure Figure 9 ;

[0041] Fig.15 Schematic diagram of the structure of the wafer provided in the embodiment of the present disclosure Figure 2 ;

[0042] Fig.16A Schematic diagram 10 of a semiconductor packaging method provided by an embodiment of the present disclosure;

[0043] Fig. 16B Schematic diagram eleven of a semiconductor packaging method provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0045] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0046] If similar descriptions of "first / second" appear in the application documents, the following description is added. In the following description, the terms "first / second / third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that "first / second / third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0048] Figure 1 is a schematic diagram of an optional semiconductor packaging structure 10 provided in an embodiment of the present disclosure, with reference to Figure 1The semiconductor package structure 10 includes: a plurality of chips 100, a substrate 200 and a plurality of insulating dielectric layers 300. The plurality of chips 100 are stacked layer by layer on the substrate 200. The plurality of insulating dielectric layers 300 are simultaneously filled in the gap between the bottom chip 100 and the substrate 200, and the gap between adjacent chips 100. At least part of the edge of each chip 100 is provided with a chamfer. The plurality of insulating dielectric layers 300 extend to the inclined surface formed by the chamfer.

[0049] In the embodiments of the present disclosure, reference Figure 1 The chip 100 may be a volatile memory semiconductor chip such as a dynamic random access memory (DRAM) or a static random access memory (SRAM). The substrate 200 may be a printed circuit board (PCB) or an interposer substrate.

[0050] Figure 2 It is a structural schematic diagram of an optional compression mold provided in an embodiment of the present disclosure. It should be noted that the filling material 30 can be a molded underfill (MUF) material. In some embodiments, the filling material 30 can be any one of materials such as BPA epoxy resin, BPF epoxy resin and aliphatic epoxy resin.

[0051] It should be noted that, in the embodiments of the present disclosure, Figure 1 and Figure 2 In the process of forming the insulating dielectric layer 300 , a compression mold 20 or other equipment is usually used to apply mold pressure to press the filling material 30 along the edge of each chip 100 into the gap between the chip 100 and the substrate 200 and the adjacent chips 100 .

[0052] Figure 3 More specifically, Figure 1 The chip 100 and the substrate 200 located at the bottom, it should be noted that, Figure 3 Omitted Figure 1 The insulating dielectric layer in.

[0053] Further, in the embodiments of the present disclosure, combined with Figure 2 and Figure 3, since the edge of each chip 100 is provided with a chamfer, when the mold clamping pressure remains unchanged, the thrust on the filling material 30 will become larger. Take the gap between the chip 100 and the substrate 200 at the bottom as an example for explanation: the chamfer of the bottom chip 100 forms a bell mouth with the substrate 200. The cross-sectional area of ​​the bell mouth section S1 is much larger than the cross-sectional area of ​​the bell mouth section S2, and the flow rate of the filling material 30 at the section S1 will be much smaller than that at the section S2. Since the pressure at the place where the flow rate of the continuous fluid is low will be higher than that at the place where the flow rate is high, the pressure at the section S1 will be much higher than the pressure at the section S2, so, according to the Bernoulli principle, in the process of the filling material 30 flowing from the section S1 to the section S2, a thrust applied to the filling material 30 will be generated, pressing the filling material 30 into the gap between the chip 100 and the substrate 200. That is to say, the bell mouth structure formed by the chamfer of the chip in the embodiment of the present disclosure and the chamfer of the substrate or the adjacent chip can add thrust to the filling material when the filling material forming the insulating layer and the dielectric layer flows. In this way, when the external mold clamping pressure remains unchanged, the filling material 30 can more easily fill the gap between the chip 100 and the substrate 200 and between adjacent chips 100 , thereby improving the filling effect of the semiconductor package structure 10 .

[0054] It should be noted that, in the embodiments of the present disclosure, reference Figure 1 The coefficients of thermal expansion (CTE) of the materials in the semiconductor package structure 10 are usually not matched, and if the bonding force between the chip 100 and the insulating dielectric layer 300 is too weak, it will easily cause the semiconductor package structure 10 to be delaminated.

[0055] It should also be noted that in the embodiments of the present disclosure, reference Figure 1 As the temperature changes, stress and strain will be generated in the semiconductor package structure, and mainly concentrated at the edge of the chip 100, which may cause the chip 100 to warp. Therefore, at the edge of the chip 100, it is necessary to increase the contact area between the chip 100 and the insulating dielectric layer 300 in the stacking direction X, and increase the bonding force between the chip 100 and the insulating dielectric layer 300 in the stacking direction X to offset the influence of the stress and strain at the edge of the chip 100.

[0056] Furthermore, if Figure 4A In the semiconductor packaging structure of the related art shown, in the stacking direction X, the front side (or back side) of the chip contacts the insulating dielectric layer, that is, in the stacking direction X, the contact area between the chip and the insulating dielectric layer is S4. Figure 4BIn the embodiment of the present disclosure shown, in the stacking direction X, the edge of the chip 100 is chamfered, and the multiple insulating dielectric layers 300 are extended to the inclined surface 111 formed by the chamfer, and the contact area between the chip 100 and the insulating dielectric layer 300 is S5, and the contact area S5 between the chip 100 and the insulating dielectric layer 300 is greater than the contact area S4 of the related art. In this way, the contact area between the insulating dielectric layer 300 and the chip 100 in the stacking direction X is larger, which can increase the bonding force between the insulating dielectric layer 300 and the chip 100, thereby reducing the risk of delamination of the semiconductor package structure 10 and improving the reliability of the semiconductor package structure 10.

[0057] In some embodiments of the present disclosure, reference Figure 3 , the linear dimension b of the chamfer along the stacking direction X is less than or equal to the thickness of the chip 100 .

[0058] In the present disclosure, continue to refer to Figure 3 In the stacking direction X, the linear dimension b of the chamfer can be smaller than the thickness of the chip 100, or can be equal to the thickness of the chip 100. In this way, the edges of the chip 100 at the bottom and the substrate 200, as well as the edges of the adjacent chips 100, are all formed into a bell-mouth shape, and the filling material can more easily fill the gaps between the chip 100 and the substrate 200 and the adjacent chips 100, thereby improving the filling effect of the semiconductor package structure 10.

[0059] In some embodiments of the present disclosure, reference Figure 1 For each chip 100 , the inclined surface 111 formed by the chamfer faces the substrate 200 .

[0060] In the embodiments of the present disclosure, reference Figure 1 For each chip 100, the chamfered inclined surface 111 faces the substrate 200. In this way, the edges of the chip 100 at the bottom and the substrate 200, as well as the edges of the adjacent chips 100, form a bell-mouth shape, and the filling material can more easily fill the gap between the chip 100 and the substrate 200 and the adjacent chips 100, thereby improving the filling effect of the semiconductor package structure 10.

[0061] Figure 5 is a schematic structural diagram of another optional semiconductor packaging structure 10 provided in an embodiment of the present disclosure. It should be noted that: Figure 5 Only the first chip 110 and the second chip 120 are exemplified. In the stacking direction X, the first chip 110 is the chip located at the bottom; the remaining chips included in the semiconductor package structure 10 can be understood with reference to the second chip 120.

[0062] In some embodiments of the present disclosure, for the bottom chip, the inclined surface formed by the chamfer faces away from the substrate, and for the remaining chips, the inclined surfaces formed by the chamfer face toward the substrate.

[0063] It should be noted that, in the embodiments of the present disclosure, reference Figure 5 In some cases, the size of the connection structure 410 for connecting the bottom chip (the first chip 110) and the substrate 200 in the semiconductor package structure 10 is larger than the connection structure 420 for connecting adjacent chips. In other words, the bump gap of the connection structure 410 is larger than that of the connection structure 420. In this way, the gap between the bottom chip (the first chip 110) and the substrate 200 is easier to fill, and thus, the flared structure may not be provided at the edge of the bottom chip (the first chip 110) and the substrate 200.

[0064] Further, in the embodiments of the present disclosure, reference is made to Figure 5 In the stacking direction X, the inclined surface 1201 corresponding to the second chip 120 faces the substrate 200, and the inclined surface 1101 corresponding to the first chip 110 faces away from the substrate 200. In this way, the chamfer of the second chip 120 and the chamfer of the first chip 110 form a bell-mouth structure. The flow velocity difference of the filling material 30 at the cross section S3 and the cross section S2 of the bell-mouth structure is larger, and the pressure difference at the cross section S3 and the cross section S2 is larger. In this way, when the external mold pressure remains unchanged, the filling material 30 can more easily fill the gap between the first chip 110 and the second chip 120, thereby further improving the filling effect of the semiconductor packaging structure 10.

[0065] In some embodiments of the present disclosure, reference Figure 1 The semiconductor package structure 10 further includes a plurality of connection structures 400 . The chip 100 at the bottom is connected to the substrate 200 , and every two adjacent chips 100 are connected via the plurality of connection structures 400 .

[0066] In the embodiments of the present disclosure, reference Figure 1 Each connection structure 400 includes a bump and a pad. In the process of stacking chips 100, the bump is welded to the corresponding pad to form the connection structure 400. The volume of the connection structure 400 between the bottom chip 100 and the substrate 200 can be equal to the volume of the connection structure 400 between adjacent chips 100.

[0067] In the embodiments of the present disclosure, reference Figure 3, the volume of the connection structure 410 between the bottom chip 100 and the substrate 200 is greater than the volume of the connection structure 420 between adjacent chips. For example, the semiconductor package structure 10 may be a package structure of a three-dimensional stack (3DS) product. In the package structure of the three-dimensional stack product, the connection structure connecting the chip at the bottom and the substrate generally uses a larger bump. Therefore, in the package structure of the three-dimensional stack product, the volume of the connection structure between the bottom chip and the substrate is greater than the volume of the connection structure between adjacent chips.

[0068] Figure 6 It is a schematic diagram of the structure of an optional chip provided in an embodiment of the present disclosure.

[0069] In some embodiments of the present disclosure, reference Figure 6 Each chip 100 includes: a first region 121 and a second region 122 ; the distribution density of the connection structure in the first region 121 is greater than the distribution density in the second region 122 ; for each chip 100 , a chamfer is set at the edge corresponding to the first region 121 .

[0070] In the embodiments of the present disclosure, reference Figure 6 For the chip 100, the distribution density of the bumps 131 in the first area 121 is greater than that in the second area 122. Correspondingly, in the stacked semiconductor package structure, the distribution density of the connection structure in the first area 121 is greater than that in the second area 122. In other words, the bump gap in the first area 121 of the chip 100 is smaller than the bump gap in the second area 122 of the chip 100. In this way, the chip 100 in the semiconductor package structure can be chamfered only at the edge corresponding to the first area 121. Thus, the structure of the chip can be further simplified while ensuring the filling effect.

[0071] In some embodiments of the present disclosure, the chamfer angle ranges from 50 to 70 degrees.

[0072] In the embodiments of the present disclosure, reference Figure 3 , the chamfer angle is a, and the range of a is 50 to 70 degrees. In this way, it can ensure that the chip 100 has a larger chamfer at the edge, and increase the area difference between the cross section S1 and the cross section S2, so that the filling material can more easily fill the gap between the chip located at the bottom (the first chip 110) and the substrate 200 and between adjacent chips, thereby further improving the filling effect of the semiconductor package structure 10.

[0073] Figure 7 is an optional flow chart of the semiconductor packaging method provided by the embodiment of the present disclosure, which will be combined with Figure 7 The steps shown are explained.

[0074] S101. Provide a substrate and a wafer.

[0075] S102, cutting the wafer to obtain a plurality of chips; wherein at least a portion of the edge of each chip is chamfered.

[0076] Figure 8 It is an optional structural schematic diagram of a wafer provided in an embodiment of the present disclosure.

[0077] In the embodiments of the present disclosure, reference Figure 8 , a wafer 500 usually forms a plurality of chips 100. Therefore, it is usually necessary to cut the wafer 500 along the cutting path 511 of the wafer 500, so as to obtain a plurality of chips 100. Among them, at least part of the edge of each chip 100 is formed with a chamfer. In this way, the trumpet-mouth structure formed by the chamfer of the chip in the embodiment of the present disclosure and the chamfer of the substrate or the adjacent chip can add thrust to the filling material when the filling material forming the insulating layer and the dielectric layer flows; when the external mold pressure remains unchanged, the filling material can more easily fill the gap between the chip 100 and the substrate and the adjacent chips 100, thereby improving the filling effect of the semiconductor packaging structure.

[0078] S103 , stacking a plurality of chips layer by layer on the substrate.

[0079] Fig. 9 is an optional structural diagram of a semiconductor packaging method provided by an embodiment of the present disclosure. It should be noted that: Fig. 9 In the description, the semiconductor package structure 10 includes four chips as an example. The number of chips included in the semiconductor package structure 10 can also be greater than 4 or less than 4, which is not limited here.

[0080] In the embodiments of the present disclosure, reference Fig. 9 On the substrate 200, a plurality of chips are stacked layer by layer along the stacking direction X. For example, along the stacking direction X, the first chip 110, the second chip 120, the third chip 130 and the fourth chip 140 are stacked in sequence. The first chip 110 and the substrate 200 as well as adjacent chips are connected via the connection structure 400.

[0081] S104, simultaneously filling the gap between the bottom chip and the substrate, and the gap between adjacent chips, to form a plurality of insulating dielectric layers; wherein the plurality of insulating dielectric layers extend to the inclined surface formed by the chamfer.

[0082] In the embodiments of the present disclosure, reference Fig. 9 , and at the same time fill the gap between the bottom chip 110 and the substrate 200, as well as the gap between adjacent chips, to form multiple insulating dielectric layers; thereby, forming Figure 1In the semiconductor package structure 10 shown, multiple insulating dielectric layers 300 extend to the chamfered inclined surface 111. In this way, the multiple insulating dielectric layers 300 extend to the chamfered inclined surface 111, which can increase the contact area between the insulating dielectric layers 300 and the chip in the stacking direction X, thereby increasing the bonding force between the chip and the insulating dielectric layers 300, reducing the risk of delamination of the semiconductor package structure 10, and improving the reliability of the semiconductor package structure 10.

[0083] In some embodiments of the present disclosure, reference Fig. 9 Among the multiple chips, the front side of the 2n-1th chip is bonded to the front side of the 2nth chip, and the back side of the 2nth chip is bonded to the back side of the 2n+1th chip; n is a positive integer; and the back side of the 1st chip is bonded to the substrate.

[0084] In the present disclosure, continue to refer to Fig. 9 , taking the semiconductor package structure 10 including four chips as an example for explanation: in the stacking direction X, the first chip 110, the second chip 120, the third chip 130 and the fourth chip 140 are stacked in sequence. The first chip 110 is the chip located at the bottom. In the process of stacking the chips layer by layer, the substrate 200 can be bonded to the back side of the first chip 110, the front side of the first chip 110 can be bonded to the front side of the second chip 120, the back side of the second chip 120 can be bonded to the back side of the third chip 130, and the front side of the third chip 130 can be bonded to the front side of the fourth chip 140.

[0085] In some embodiments of the present disclosure, S201 or S202 can be used to implement Figure 7 S102 shown will be described in conjunction with each step.

[0086] S201, cutting a chip along the front side of the wafer; the front side of the chip and the chamfered surface have the same orientation.

[0087] Fig. 10A and Fig. 10B It is a schematic diagram of the structure of an optional wafer cutting provided by an embodiment of the present disclosure.

[0088] in, Fig. 10A The positional relationship between the wafer 500 and the narrow blade 610 is shown. Fig. 10B Shows Fig. 10A The dicing method shown corresponds to the formed chip 100 .

[0089] In the present disclosure, in combination Fig. 10A and Fig. 10B The present disclosure can use a narrow knife 610 to cut the wafer 500 along the front side 510 of the wafer 500 to obtain the following Fig. 10BThe plurality of chips 100 are shown. The chamfered bevel 111 faces the front surface 112 of the chip 100 and faces away from the back surface 113 of the chip 100. Therefore, in the semiconductor package structure, the chamfered bevel 111 and the front surface 112 of the chip 100 have the same orientation.

[0090] S202, cutting a chip along the back side of the wafer; the front side of the chip and the chamfered surface have opposite directions.

[0091] Fig.11A and Fig. 11B is a schematic diagram of another optional structure of cutting wafers provided by the embodiment of the present disclosure. Fig.11A The positional relationship between the wafer 500 and the narrow blade 610 is shown. Fig. 11B Shows Fig.11A The dicing method shown corresponds to the formed chip 100 .

[0092] In the present disclosure, in combination Fig.11A and Fig. 11B The present disclosure can use a narrow knife 610 to cut the wafer 500 along the back side 520 of the wafer 500 to obtain the following Fig. 11B The plurality of chips 100 are shown. The chamfered inclined surface 111 faces the back surface 113 of the chip 100 and is away from the front surface 112 of the chip 100. Therefore, in the semiconductor package structure, the front surface 112 of the chip 100 and the chamfered inclined surface 111 have opposite directions.

[0093] That is, the chips in the semiconductor packaging structure may have different chamfers. The embodiments of the present disclosure can cut the wafer from the front or back of the wafer corresponding to the chip in the process of cutting to form the chip according to the orientation of the chamfer of the specific chip in the semiconductor packaging structure, and obtain the chamfer with the corresponding orientation. For example, Figure 5 In the semiconductor package structure 10 shown, the first chip 110 can be cut along the back side of the corresponding wafer, and the second chip 120 can be cut along the front side of the corresponding wafer.

[0094] In some embodiments of the present disclosure, S301 to S302 can be used to implement Figure 7 S102 shown will be described in conjunction with each step.

[0095] S301, using a narrow knife to cut the wafer; wherein the cutting depth of the narrow knife corresponds to the linear dimension of the chamfer.

[0096] Fig. 12A and Fig. 12B is a schematic diagram of another optional structure of cutting wafers provided by the embodiment of the present disclosure. Fig. 12A The positional relationship between the wafer 500 and the narrow blade 610 is shown. Fig. 12B The positional relationship between the wafer 500 and the flat knife 620 is shown.

[0097] In the present disclosure, in combination Fig. 10A and Fig. 12A , the present disclosure can select different cutting depths according to the preset linear dimensions of the chamfer. The cutting depth of the narrow blade 610 corresponds to the linear dimensions of the chamfer. For example, Fig. 10A The cutting depth of the medium narrow blade 610 is h1. Fig. 12A The cutting depth of the medium narrow blade 610 is h2, and h2 is smaller than h1.

[0098] S302, using a flat knife to cut the wafer to obtain a plurality of chips.

[0099] It should be noted that the reference Fig. 10A If a narrow knife 610 is used to cut through the wafer 500, the sharp corners of the narrow knife 610 may cause chipping on the product surface.

[0100] Further, in the embodiments of the present disclosure, combined with Fig. 12A and Fig. 12B The present disclosure can adopt a step-cut method, first cutting with a narrow knife 610, and then cutting through with a flat knife 620 to obtain multiple chips 100. In this way, while ensuring that the chip can improve the filling effect, the problem of product surface collapse can be avoided, and the product yield can be further improved.

[0101] Fig.13 is another optional flow chart of the semiconductor packaging method provided by the embodiment of the present disclosure, which is combined with Fig.13 The steps shown are explained.

[0102] It should be noted that Fig.13 and Figure 7 S101 and S102 are the same and will not be described here.

[0103] S105, stacking a plurality of chips layer by layer on a substrate; connecting the bottom chip and the substrate, as well as adjacent chips, through a plurality of partially welded connection structures.

[0104] Fig.14A and Fig. 14B is a schematic diagram of an optional structure for forming a connection structure provided by an embodiment of the present disclosure. Fig.14A A partially welded connection structure 430 is shown. Fig. 14B A fully welded connection 440 is shown.

[0105] It should also be noted that Fig.14A and Fig. 14BThe semiconductor package structure 10 includes two chips as an example for description. The number of chips included in the semiconductor package structure 10 can also be greater than 2 or less than 2, which is not limited here.

[0106] In the embodiment of the present disclosure, referring to FIG14 , a plurality of chips are stacked layer by layer on a substrate 200. For example, in the stacking direction X, a first chip 110 and a second chip 120 are sequentially stacked on the substrate 200. The bottom chip 110 is connected to the substrate 200, and adjacent chips are connected by a plurality of partially welded connection structures 430.

[0107] S106 , simultaneously filling the gap between the bottom chip and the substrate, and the gap between adjacent chips, to form a plurality of insulating dielectric layers.

[0108] In the present disclosure, in combination Fig.14A and Fig. 14B , and fill the gap between the bottom chip 110 and the substrate 200, as well as the gap between adjacent chips, to form multiple insulating dielectric layers. The length L1 of the partially welded connection structure 430 is greater than the length L2 of the fully welded connection structure 440. In this way, the gap between the chip and the substrate, as well as the gap between adjacent chips, will be larger, and the filling material will be easier to fill the gap between the chip and the substrate, as well as the gap between adjacent chips; thus, the filling effect of the semiconductor package structure 10 can be further improved.

[0109] S107, performing reflow soldering on the plurality of partially soldered connection structures to form a plurality of fully soldered connection structures; wherein the length of the partially soldered connection structure is greater than the length of the fully soldered connection structure.

[0110] In the present disclosure, in combination Fig.14A and Fig. 14B After forming the insulating dielectric layer, the multiple partially welded connection structures 430 are subjected to a mass reflow process to form multiple completely welded connection structures 440. Thus, the connection structures between the bottom chip and the substrate and between adjacent chips can have good conductive properties.

[0111] It can be understood that the embodiment of the present disclosure uses a partially welded connection structure to connect the chip and the substrate, and then fills the gap between the bottom chip and the substrate and between adjacent chips, and finally performs a reflow soldering process on the partially welded connection structure to form a completely welded connection structure. In this way, the filling effect of the semiconductor packaging structure can be further improved while ensuring the conductive performance of the connection structure.

[0112] In some embodiments of the present disclosure, the heating peak temperature of the reflow soldering process is higher than the heating temperature of forming a partially soldered connection structure; and the heating time of the reflow soldering process is longer than the heating time of forming a partially soldered connection structure.

[0113] In the present disclosure, in combination Fig.14A and Fig. 14B , multiple chips are stacked layer by layer on the substrate 200 along the stacking direction X, and adjacent chips are connected by partially welded connection structures 430. The multiple partially welded connection structures 430 are subjected to reflow soldering to form corresponding fully welded connection structures 440. The heating peak temperature of the reflow soldering process is higher than the heating temperature of forming the partially welded connection structure; the heating time of the reflow soldering process is longer than the heating time of forming the partially welded connection structure.

[0114] In some embodiments of the present disclosure, S401 to S404 can be used to implement Figure 7 S102 shown will be described in conjunction with each step.

[0115] S401, clearing the metal and dielectric layers in the sawing area on the wafer.

[0116] Fig.15 It is a schematic diagram of the structure of another optional wafer provided in an embodiment of the present disclosure.

[0117] In the embodiments of the present disclosure, reference Fig.15 , the metal and dielectric layers in the scribe line area 511 on the wafer 500 are removed. Thus, the metal and dielectric layers can be prevented from interfering with the subsequent wafer dicing steps.

[0118] S402, forming a patterned hard mask on the front side or the back side of the wafer to expose an edge corresponding to the first region to form an etching window.

[0119] Fig.16A and Fig. 16B It is a schematic diagram of the structure of an optional wafer cutting provided by an embodiment of the present disclosure.

[0120] in, Fig.16A shows the wafer before dicing, Fig. 16B The wafer after sawing is shown.

[0121] In the embodiment of the present disclosure, the chamfers of the specific chips in the semiconductor packaging structure have different bevels in different directions. In the process of cutting the wafer to form the chips, a patterned hard mask can be formed on the front or back side of the wafer; thus, after the subsequent cutting step is completed, a chamfer with a bevel in a corresponding direction is formed. For example, Fig.16A In the embodiment, the hard mask 710 is formed on the front side 510 of the wafer 500 so that the inclined surface formed by the chamfer of the chip faces the front side of the chip.

[0122] It should be noted that, in the embodiments of the present disclosure, reference is made to Fig.15 , each chip 100 includes: a first region 121 and a second region 122. The distribution density of the bumps 131 in the first region 121 is greater than that in the second region 122. Correspondingly, in the stacked semiconductor package structure, the distribution density of the connection structure in the first region 121 is greater than that in the second region 122. Therefore, the chip 100 in the semiconductor package structure can be chamfered only at the edge corresponding to the first region 121.

[0123] Further, in the embodiments of the present disclosure, combined with Fig.15 and Fig.16A A patterned hard mask 710 is formed on the front side 510 of the wafer 500 to expose the edge corresponding to the first region 121 to form an etching window 512. Therefore, in subsequent steps, a chamfer may be formed only at the position corresponding to the etching window 512.

[0124] S403 , performing wet etching according to the patterned hard mask to form chamfers at positions corresponding to the etching windows.

[0125] It should be noted that the hard mask can be a photoresist (PR). When etching, a hard mask can be set on either the front or back side of the wafer, and correspondingly, an etching fixture is set on the other side of the wafer. For example, Fig.16A The middle hard mask 710 is disposed on the front side 510 of the wafer 500 , and the etching fixture 720 is disposed on the back side of the wafer 500 .

[0126] In the present disclosure, in combination Fig.16A and Fig. 16B The wafer 500 is wet-etched according to the patterned hard mask 710 to form a chamfer on the wafer 500 corresponding to the etching window. The wet etching agent may be KOH, the etching angle may be 54.74°, and the width of the cutting path of the wafer 500 may be greater than 120 um.

[0127] S404, cutting the wafer along the dicing area to obtain a plurality of chips.

[0128] In the embodiment of the present disclosure, after the chamfer is formed, the wafer can be cut using a flat knife or a narrow knife to obtain multiple chips.

[0129] It is understandable that the embodiment of the present disclosure forms an etching window at a position corresponding to the area with a small bump gap, and then uses wet etching to generate a chamfer at the etching window. In this way, the range of the chamfer can be reduced while ensuring the filling effect, further simplifying the chip structure.

[0130] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0131] The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0132] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A semiconductor packaging structure, It is characterized in that include: A substrate, a plurality of chips and a plurality of insulating dielectric layers; A plurality of the chips are stacked layer by layer on the substrate; The plurality of insulating dielectric layers are simultaneously filled in the gap between the chip at the bottom and the substrate, and the gap between adjacent chips; wherein, At least part of the edge of each chip is provided with a chamfer; and the plurality of insulating dielectric layers all extend to the inclined surface formed by the chamfer.

2. The semiconductor package structure according to claim 1, It is characterized in that A linear dimension of the chamfer along the stacking direction is less than or equal to a thickness of the chip.

3. The semiconductor package structure according to claim 1 or 2, It is characterized in that For each of the chips, the inclined surface formed by the chamfer faces the substrate.

4. The semiconductor package structure according to claim 1 or 2, It is characterized in that For the chip at the bottom, the inclined surface formed by the chamfer faces away from the substrate; For the remaining chips, the inclined surfaces formed by the chamfers all face the substrate.

5. The semiconductor package structure according to claim 1 or 2, It is characterized in that The semiconductor packaging structure further includes: a plurality of connection structures; The chip at the bottom and the substrate, as well as every two adjacent chips, are connected via a plurality of the connection structures; wherein the volume of the connection structure between the chip at the bottom and the substrate is greater than the volume of the connection structure between adjacent chips.

6. The semiconductor package structure according to claim 5, It is characterized in that Each of the chips comprises: a first region and a second region; The distribution density of the connection structure in the first area is greater than the distribution density in the second area; For each of the chips, the chamfer is provided at an edge corresponding to the first region.

7. The semiconductor package structure according to claim 3, It is characterized in that The chamfer angle ranges from 50 to 70 degrees.

8. The semiconductor package structure according to claim 1, It is characterized in that Among the plurality of chips, the front side of the 2n-1th chip is bonded to the front side of the 2nth chip, and the back side of the 2nth chip is bonded to the back side of the 2n+1th chip; n is a positive integer; The reverse side of the first chip is bonded to the substrate.

9. A semiconductor packaging method, It is characterized in that include: Provide substrates and wafers; Cutting the wafer to obtain a plurality of chips; wherein at least a portion of the edge of each chip is chamfered; On the substrate, stacking a plurality of the chips layer by layer; At the same time, the gap between the chip and the substrate at the bottom and the gap between adjacent chips are filled to form a plurality of insulating dielectric layers; wherein the plurality of insulating dielectric layers extend to the inclined surface formed by the chamfer.

10. The semiconductor packaging method according to claim 9, It is characterized in that Cutting the wafer to obtain a plurality of chips comprises: The chip is cut out along the front side of the wafer; the front side of the chip and the chamfered bevel have the same orientation; or, The chip is cut out along the back side of the wafer; the front side of the chip and the chamfered slope have opposite directions.

11. The semiconductor packaging method according to claim 9, It is characterized in that Cutting the wafer to obtain a plurality of chips further comprises: Using a narrow knife to cut the wafer; wherein the cutting depth of the narrow knife corresponds to the linear dimension of the chamfer; The wafer is cut using a flat knife to obtain a plurality of the chips.

12. The semiconductor packaging method according to claim 9, It is characterized in that The semiconductor packaging method further comprises: On the substrate, a plurality of the chips are stacked layer by layer; the chip at the bottom is connected to the substrate, and adjacent chips are connected via a plurality of partially welded connection structures; At the same time, the gap between the chip and the substrate at the bottom, as well as the gap between adjacent chips, are filled to form a plurality of insulating dielectric layers; A reflow soldering process is performed on the plurality of partially soldered connection structures to form a plurality of completely soldered connection structures; wherein the length of the partially soldered connection structures is greater than the length of the completely soldered connection structures.

13. The semiconductor packaging method according to claim 12, It is characterized in that The heating peak temperature of the reflow soldering process is higher than the heating temperature of the connection structure formed by partial soldering; and the heating time of the reflow soldering process is longer than the heating time of the connection structure formed by partial soldering.

14. The semiconductor packaging method according to claim 12, It is characterized in that Each of the chips comprises: a first region and a second region; the distribution density of the connection structures in the first region is greater than the distribution density in the second region; Cutting the wafer to obtain a plurality of chips further comprises: removing the metal and dielectric layers in the scribe line area on the wafer; forming a patterned hard mask on the front side or the back side of the wafer to expose an edge corresponding to the first region to form an etching window; Performing wet etching according to the patterned hard mask to form the chamfer at a position corresponding to the etching window; The wafer is cut along the dicing area to obtain a plurality of the chips.

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