Trench field effect transistor

Abstract

The invention provides a groove type field effect transistor comprising a substrate, the substrate is provided with a plurality of grid electrode grooves which are sequentially arranged at intervals along a first direction, each grid electrode groove extends along a second direction, and the second direction is orthogonal to the first direction; gate structures, wherein each gate trench is filled with one gate structure; the plurality of first electric field shielding structures are sequentially arranged along the second direction, each first electric field shielding structure and at least the bottom wall of each gate trench have an overlapping region, and the first electric field shielding structures are narrowed at the positions close to the gate trenches, so that the on-resistance can be obviously reduced, and the on-resistance of the device can be improved. And better compromise between the on resistance and the bottom electric field shielding of the gate oxide layer is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a trench field effect transistor. Background Art

[0002] Compared with planar gate transistors, trench field effect transistors can greatly reduce the cell size and thus significantly increase the current density. For example, compared with planar gate MOSFET, the performance of trench gate metal-oxide-semiconductor field-effect transistors (MOSFET) has been greatly improved. Not only can higher channel mobility be obtained, but also the specific on-resistance can be reduced, and the on-current density and conduction performance of the device can be improved.

[0003] The gate of a trench field effect transistor is set in the trench, and the electric field is concentrated at the bottom of the trench, which can easily cause the gate oxide layer to break down, thus causing device failure. At present, multiple electric field shielding structures parallel to each other are generally used to simultaneously protect the gate oxide layer at the bottom of all trenches. This protection scheme can better protect the bottom of the gate oxide layer and prevent the bottom of the gate oxide layer from being broken down, but it will cause a large on-resistance of the device. Summary of the invention

[0004] The object of the present invention is to provide a trench field effect transistor to solve the problem of large on-resistance between the source and the drain of the existing trench field effect transistor.

[0005] In order to solve the above problems, the present invention provides a trench field effect transistor, comprising: A substrate, wherein the substrate has a plurality of gate trenches arranged in sequence and at intervals along a first direction, each of the gate trenches extending along a second direction, and the second direction is orthogonal to the first direction; A plurality of gate structures, each of the gate trenches is filled with a gate structure; A plurality of first electric field shielding structures are arranged in sequence along the second direction, each of the first electric field shielding structures extends along the first direction and has an overlapping area with at least the bottom wall of each of the gate trenches, and each of the first electric field shielding structures has a plurality of first sub-shielding structures and a plurality of second sub-shielding structures, the first sub-shielding structure is located in a middle area between two adjacent gate trenches, two adjacent first sub-shielding structures are connected through a second sub-shielding structure, and a width D1 of the first sub-shielding structure in the second direction is greater than a width D2 of the second sub-shielding structure in the second direction.

[0006] Optionally, in the trench field effect transistor, in the second direction, widths of the first sub-shielding structure beyond both sides of the second sub-shielding structure are the same.

[0007] Optionally, in the trench field effect transistor, a distance between two adjacent first sub-shielding structures is D3, D1>35% D3, and D2>10% D3.

[0008] Optionally, in the trench field effect transistor, the depth of each of the first electric field shielding structures is H, and D3≤H.

[0009] Optionally, in the trench field effect transistor, the width of each gate trench is W1, the spacing between two adjacent gate trenches is W2, and W1≤35% W2; between two adjacent gate trenches, the length of the second sub-shielding structure located on a single side of the first sub-shielding structure along the second direction is L, and L>32% W2.

[0010] Optionally, in the trench field effect transistor, the first electric field shielding structure surrounds the bottom and part of the side wall of the corresponding gate trench.

[0011] Optionally, in the trench field effect transistor, the trench field effect transistor further includes: a body region, a source contact region and an electric field shielding structure contact region, the body region and the source contact region stacked sequentially from bottom to top are provided between two adjacent gate trenches, each gate trench includes a first portion and a second portion, the first portion is a portion located above the first electric field shielding structure and not surrounded by the first electric field shielding structure, and the second portion is a portion located between two adjacent first electric field shielding structures; The electric field shielding structure contact region covers the top of the first electric field shielding structure, the first portion is adjacent to the electric field shielding structure contact region, and the second portion is adjacent to the body region and the source contact region.

[0012] Optionally, in the trench field effect transistor, the trench field effect transistor further includes a current spreading layer, and a current spreading layer is disposed at the bottom of each of the body regions.

[0013] Optionally, in the trench field effect transistor, it further includes: A second electric field shielding structure is provided at the bottom of each gate trench extending along the second direction.

[0014] Optionally, in the trench field effect transistor, the second electric field shielding structure is connected to the ground potential through the first electric field shielding structure.

[0015] In summary, the trench field effect transistor provided by the present invention comprises: a substrate, the substrate having a plurality of gate trenches arranged in sequence along a first direction, each of the gate trenches extending in a second direction, the second direction being orthogonal to the first direction; a plurality of gate structures, each of the gate trenches being filled by a gate structure; a plurality of first electric field shielding structures, the plurality of first electric field shielding structures being arranged in sequence along the second direction, each of the first electric field shielding structures extending in the first direction, having an overlapping area with at least the bottom wall of each of the gate trenches, and each of the first electric field shielding structures having a plurality of first sub-shielding structures and a plurality of second sub-shielding structures, the first sub-shielding structure being located in the middle area between two adjacent gate trenches, the two adjacent first sub-shielding structures being connected by a second sub-shielding structure, the width D1 of the first sub-shielding structure in the second direction being greater than the width D2 of the second sub-shielding structure in the second direction. In the trench field effect transistor provided by the present invention, the first electric field shielding structure is narrowed at a position close to the gate trench, which can significantly reduce the on-resistance, and achieve a better compromise between the on-resistance and the electric field shielding at the bottom of the gate oxide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a projection diagram of a trench field effect transistor in the prior art; Figure 2 A projection diagram of a trench field effect transistor provided by an embodiment of the present invention; Figure 3 A schematic diagram of the three-dimensional structure of a trench field effect transistor provided in an embodiment of the present invention; Figure 4 for Figure 3 The schematic diagram of the structure of the section AA" shown in the figure; Figure 5 for Figure 3 The schematic diagram of the structure of the section BB" shown; Figure 6 for Figure 3 The structural schematic diagram of the section of structure CC” shown; Figure 7 A comparison diagram of the on-resistance of the trench field effect transistor provided by the embodiment of the present invention and the existing trench field effect transistor; The descriptions of the reference numerals are as follows: 10-gate structure; 11-electric field shielding structure; 20 - gate structure; 21 - first electric field shielding structure; 22 - substrate; 23 - electric field shielding structure contact area; 24-body region; 25-source contact region; 26-current spreading layer; 27-second electric field shielding structure; 28-source metal layer; 200-gate trench; 201-gate; 202-gate oxide layer; 211-first sub-shielding structure; 212-second sub-shielding structure; 221 - substrate; 222 - epitaxial layer. DETAILED DESCRIPTION

[0017] As described in the background art, currently, multiple electric field shielding structures parallel to each other are used to simultaneously protect the gate oxide layers at the bottom of all trenches. Figure 1 As shown in the figure, the trench field effect transistor includes a plurality of gate structures 10 respectively filled in the trenches along a first direction, and a plurality of electric field shielding structures 11 sequentially arranged and spaced along a second direction (orthogonal to the first direction) are used to reduce the bottom electric field strength of each gate structure. Each electric field shielding structure 11 is extended along the second direction, and there is an overlapping area with the projection of each gate structure 10 on the plane formed by the orthogonality of the first direction and the second direction, so as to protect the bottom of the gate oxide layer and prevent the bottom of the gate oxide layer from being broken down. However, the technicians of the present invention found that while the electric field shielding structure 11 protects the bottom of the gate oxide layer, it also causes a large on-resistance of the device.

[0018] To this end, the present invention aims to provide a trench field effect transistor to solve the problem that after the electric field shielding structure is set in the existing trench field effect transistor, although the bottom of the gate oxide layer can be protected, it will also cause a large on-resistance of the device.

[0019] The trench field effect transistor proposed in the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis required to be shown in each drawing is different, and sometimes different proportions are used. It should be recognized that relative terms such as "above", "below", "top", "bottom", "above" and "below" shown in the drawings can be used to describe the relationship between various elements. These relative terms are intended to cover different orientations of elements other than the orientations depicted in the drawings. For example, if the device is inverted relative to the view in the drawings, for example, an element described as "above" another element will now be below the element. It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third" and the like in the specification are only used to distinguish between the various components, elements, steps, etc. in the specification, rather than to represent the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0020] In order to solve the problems existing in the prior art, an embodiment of the present invention provides a trench field effect transistor, see Figure 2 Combined with Figure 3~Figure 6 , the trench field effect transistor provided by the embodiment of the present invention comprises: A substrate 22, wherein the substrate 22 has a plurality of gate trenches 200 sequentially arranged along a first direction, each of the gate trenches 200 extending along a second direction, and the second direction is orthogonal to the first direction; A plurality of gate structures 20, each of the gate trenches 200 is filled with a gate structure 20; A plurality of first electric field shielding structures 21 are arranged in sequence along the second direction, each of the first electric field shielding structures 21 extends along the first direction and has an overlapping area with at least the bottom wall of each of the gate trenches 200, and each of the first electric field shielding structures 21 has a plurality of first sub-shielding structures 211 and a plurality of second sub-shielding structures 212, the first sub-shielding structure 211 is located in the middle area between two adjacent gate trenches 200, two adjacent first sub-shielding structures 211 are connected by a second sub-shielding structure 212, and a width D1 of the first sub-shielding structure 211 in the second direction is greater than a width D2 of the second sub-shielding structure 212 in the second direction, that is, the first electric field shielding structure 21 is narrowed at a position close to the gate trench 200.

[0021] It should be understood that each of the first electric field shielding structures 21 and at least the bottom wall of each of the gate trenches 200 have an overlapping area, which means that the projections of each of the first electric field shielding structures 21 and each of the gate trenches 200 on at least the plane formed by the orthogonality of the first direction and the second direction have an overlapping area. In addition, the middle area between each two adjacent gate trenches 200 refers to an area with an equal distance from the two adjacent gate trenches 200, and the width of the middle area in the first direction can be defined according to needs.

[0022] In the trench field effect transistor provided by the present invention, the first electric field shielding structure 21 is narrowed near the gate trench 200, which can significantly reduce the on-resistance and achieve a better compromise between the on-resistance and the electric field shielding at the bottom of the gate oxide layer.

[0023] like Figure 3As shown in , the base 22 includes a substrate 221 and an epitaxial layer 222 formed on the substrate 221. The plane formed by the orthogonality of the first direction and the second direction is parallel to the surface of the substrate 221 / the epitaxial layer 222. The height direction of the substrate 221 / the epitaxial layer 222 is defined as the third direction, and the sidewalls of each of the gate trenches 200 are parallel to the plane formed by the orthogonality of the second direction and the third direction. In this embodiment, as an example, the substrate 221 is an N+ type semiconductor substrate, the epitaxial layer 222 is an N type semiconductor layer, and the materials of the substrate 221 and the epitaxial layer 222 are both silicon carbide.

[0024] The gate trench 200 is obtained by etching the epitaxial layer 222. The etching process is well known to those skilled in the art and will not be described in detail herein. The gate trench 200 is extended along the second direction, that is, the length direction of the gate trench 200 is the second direction, and the gate trench 200 has a depth in the third direction. The portion of the epitaxial layer 222 located below the gate trench 200 is used to form a drift region of the device.

[0025] The gate structure 20 includes a gate oxide layer 202 and a gate 201. The gate oxide layer 202 is first formed in the gate trench 200 by an oxidation process or a deposition process or a process of oxidation first and then deposition. The formed gate oxide layer 202 covers the bottom wall and side wall of the gate trench 200. Then, the remaining space in the gate trench 200 is filled with a gate material to form the gate 201. The material of the gate 201 can generally be polysilicon.

[0026] The first electric field shielding structure 21 is formed by ion implantation. As an example, the conductivity type of the first electric field shielding structure 21 is P type. In this embodiment, preferably, in the second direction, the width D4 of the first sub-shielding structure 211 beyond the two sides of the second sub-shielding structure 212 is the same, so that the first electric field shielding structure 21 is arranged symmetrically as a whole, so that the uniformity of the electric field strength at the bottom of each gate trench can be ensured.

[0027] Please see again Figure 2 Combined with Figure 3 Assuming that the spacing between two adjacent first sub-shielding structures 211 is D3, and the depth of each first electric field shielding structure 21 is H, then preferably, D1>35% D3, D2>10% D3, and also preferably, D3≤H. In this way, the setting of the first electric field shielding structure 21 can be guaranteed to achieve a good electric field shielding effect.

[0028] In addition, assuming that the width of each gate trench is W1, the spacing between two adjacent gate trenches is W2, and the length of the second sub-shielding structure 212 located on a single side of the first sub-shielding structure 211 along the second direction between two adjacent gate trenches is L, then preferably, W1≤35% W2, L>32% W2, so that it can be ensured that the setting of the first electric field shielding structure 21 will not lead to a large on-resistance of the device.

[0029] like Figure 3 and Figure 4 As shown in , preferably, the first electric field shielding structure 21 surrounds the bottom and part of the sidewall of the corresponding gate trench 200. The portion of the first electric field shielding structure 21 located outside the sidewall of the gate trench 200 can change the electric field distribution on the side of the gate trench 200, thereby alleviating the electric field concentration effect of the gate dielectric layer at the bottom corner to a certain extent.

[0030] Optionally, the trench field effect transistor provided in this embodiment further includes: an electric field shielding structure contact region 23, a body region 24 and a source contact region 25, wherein the body region 24 and the source contact region 25 are stacked sequentially from bottom to top between two adjacent gate trenches 200, and the body region 24 and the source contact region 25 are respectively adjacent to the two adjacent gate trenches 200, and the body region 24 is also called the base region, which is the main body layer for forming the channel, and the body region 24 is opposite to the conductivity type of the epitaxial layer 222, as an example, the body region 24 is a P-type doped region, and the source contact region 25 is the same as the conductivity type of the epitaxial layer 222, as an example, the source contact region 25 is an N+ contact region. Each gate trench 200 includes a first part and a second part, wherein the first part is a part located above the first electric field shielding structure 21 and not surrounded by the first electric field shielding structure 21, and the second part is a part located between two adjacent first electric field shielding structures 21. The electric field shielding structure contact region 23 covers the top of the first electric field shielding structure 21, the first portion is adjacent to the electric field shielding structure contact region 23, and the second portion is adjacent to the body region 24 and the source contact region 25. The first electric field shielding structure 21 is conductively connected to the source contact region 25 through the electric field shielding structure contact region 23, thereby connecting to the ground potential. The electric field shielding structure contact region 23 is opposite to the conductivity type of the epitaxial layer 222. As an example, the electric field shielding structure contact region 23 is a P+ contact region.

[0031] Preferably, the trench field effect transistor provided in this embodiment further includes: a current spreading layer (CSL) layer 26 disposed at the bottom of the body region 24. As an example, the current spreading layer 26 is an N-type doped layer, which can make the current more uniform, minimize the current crowding at the top of the drift region, and reduce the resistance of the drift region.

[0032] Preferably, the trench transistor provided in this embodiment further includes: a second electric field shielding structure 27, wherein the bottom of each gate trench 200 is provided with a second electric field shielding structure 27 extending along the second direction, and the second electric field shielding structure 27 is conductively connected to the electric field shielding structure contact area 23 and the source contact area 25 in sequence through the first electric field shielding structure 21, so that the second electric field shielding structure 27 is also connected to the ground potential. As an example, the conductivity type of the second electric field shielding structure 27 is also P type.

[0033] Optionally, there is a gap (not shown) between the first electric field shielding structure 21 and / or the second electric field shielding structure 27 and the gate trench 200. That is, the first electric field shielding structure 21 and / or the second electric field shielding structure 27 are not in contact with the gate oxide layer 202, so that the formation of the channel is not affected, which is conducive to the flow of current. The second electric field shielding structure 27 arranged at the bottom of the gate trench 200 realizes the protection of the bottom of the gate oxide layer 202. The cooperation of the first electric field shielding structure 21 and the second electric field shielding structure 27 takes into account the electric field shielding effect at the bottom of the gate oxide layer 202 and the influence on the on-resistance of the trench field effect transistor, making the structural setting of improving the working stability and service life of the trench field effect transistor more flexible.

[0034] The ion doping concentrations of the first electric field shielding structure 21 and the second electric field shielding structure 27 are approximately equal; in actual processes, the ion doping concentrations of the two can be within the same order of magnitude. In order to improve the reliability of current conduction between the first electric field shielding structure 21 and the second electric field shielding structure 27, the second electric field shielding structure 27 can be configured to have an area overlapping with the first electric field shielding structure 21, and the area has a relatively larger ion doping concentration, so that good conductive contact can be formed between the first electric field shielding structure 21 and the second electric field shielding structure 27.

[0035] It should be understood that in some other embodiments, the substrate 221 may also be a P+ type semiconductor substrate 221, and correspondingly, the epitaxial layer 222 is a P-type semiconductor layer, and the devices arranged in the epitaxial layer 222 should also be adaptively adjusted. For example, the conductivity type of the first electric field shielding structure 21 and the second electric field shielding structure 27 is adjusted to N type, the body region 24 is adjusted to an N-type doped region, the source contact region 25 is adjusted to a P+ contact region, and so on, which will not be repeated here.

[0036] In addition, the trench field effect transistor provided in the embodiment of the present invention may further include: a source metal layer 28. The source metal layer 28 is used to realize the conductive connection between the electric field shielding structure contact area 23 and the source contact area 25 and the external circuit.

[0037] Figure 7 A comparison diagram of the on-resistance of the trench field effect transistor provided by the present invention and the existing trench field effect transistor is shown in FIG. Figure 7 It can be seen that, compared with the existing trench field effect transistor, the on-resistance of the trench field effect transistor provided by the present invention is reduced.

[0038] In summary, the trench field effect transistor provided by the embodiment of the present invention comprises: a substrate, the substrate having a plurality of gate trenches arranged in sequence along a first direction, each of the gate trenches extending in a second direction, the second direction being orthogonal to the first direction; a plurality of gate structures, each of the gate trenches being filled by a gate structure; a plurality of first electric field shielding structures, the plurality of first electric field shielding structures being arranged in sequence along the second direction, each of the first electric field shielding structures extending in the first direction, having an overlapping area with at least the bottom wall of each of the gate trenches, and each of the first electric field shielding structures having a plurality of first sub-shielding structures and a plurality of second sub-shielding structures, the first sub-shielding structure being located in the middle area between two adjacent gate trenches, the two adjacent first sub-shielding structures being connected by a second sub-shielding structure, and the width D1 of the first sub-shielding structure in the second direction being greater than the width D2 of the second sub-shielding structure in the second direction. In the trench field effect transistor provided by the embodiment of the present invention, the first electric field shielding structure is narrowed at a position close to the gate trench, which can significantly reduce the on-resistance and achieve a better compromise between the on-resistance and the electric field shielding at the bottom of the gate oxide layer.

[0039] It should also be noted that, although the present invention has been disclosed as a preferred embodiment as above, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A trench field effect transistor, characterized in that: include: A substrate, wherein the substrate has a plurality of gate trenches arranged in sequence and at intervals along a first direction, each of the gate trenches extending along a second direction, and the second direction is orthogonal to the first direction; A plurality of gate structures, each of the gate trenches is filled with a gate structure; A plurality of first electric field shielding structures are arranged in sequence along the second direction, each of the first electric field shielding structures extends along the first direction and has an overlapping area with at least the bottom wall of each of the gate trenches, and each of the first electric field shielding structures has a plurality of first sub-shielding structures and a plurality of second sub-shielding structures, the first sub-shielding structure is located in a middle area between two adjacent gate trenches, two adjacent first sub-shielding structures are connected through a second sub-shielding structure, and a width D1 of the first sub-shielding structure in the second direction is greater than a width D2 of the second sub-shielding structure in the second direction.

2. The trench field effect transistor according to claim 1, wherein: In the second direction, widths of the first sub-shielding structures beyond two sides of the second sub-shielding structures are the same.

3. The trench field effect transistor according to claim 1, wherein: The distance between two adjacent first sub-shielding structures is D3, D1>35% D3, and D2>10% D3.

4. The trench field effect transistor according to claim 3, wherein: The depth of each of the first electric field shielding structures is H, and D3≤H.

5. The trench field effect transistor according to claim 1, wherein: The width of each gate trench is W1, and the spacing between two adjacent gate trenches is W2, W1≤35% W2; between two adjacent gate trenches, the length of the second sub-shielding structure located on a single side of the first sub-shielding structure along the second direction is L, L>32%W2.

6. The trench field effect transistor according to claim 1, wherein: The first electric field shielding structure surrounds the bottom and a portion of the sidewall of the corresponding gate trench.

7. The trench field effect transistor according to claim 4, wherein: The trench field effect transistor further comprises: a body region, a source contact region and an electric field shielding structure contact region, the body region and the source contact region stacked sequentially from bottom to top are arranged between two adjacent gate trenches, each gate trench comprises a first portion and a second portion, the first portion is a portion located above the first electric field shielding structure and not surrounded by the first electric field shielding structure, and the second portion is a portion located between two adjacent first electric field shielding structures; The electric field shielding structure contact region covers the top of the first electric field shielding structure, the first portion is adjacent to the electric field shielding structure contact region, and the second portion is adjacent to the body region and the source contact region.

8. The trench field effect transistor according to claim 7, wherein: The trench field effect transistor further comprises a current spreading layer, and a current spreading layer is arranged at the bottom of each body region.

9. The trench field effect transistor according to claim 1, wherein: Also includes: A second electric field shielding structure is provided at the bottom of each gate trench extending along the second direction.

10. The trench field effect transistor according to claim 9, wherein: The second electric field shield structure is connected to a ground position through the first electric field shield structure.

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