Preparation method of solar cell and solar cell

Abstract

The invention relates to a preparation method of a solar cell and the solar cell. The preparation method of the solar cell comprises the following steps that a substrate is provided, and the substrate is provided with a front face and a back face which are oppositely arranged; preparing a tunneling oxide layer and an intrinsic silicon material layer which are stacked in sequence on the back surface of the substrate; doping the intrinsic silicon material layer through laser processing to respectively obtain a first doped silicon material layer and a second doped silicon material layer, and simultaneously forming a groove which is positioned between the first doped silicon material layer and the second doped silicon material layer and is used for separating the first doped silicon material layer and the second doped silicon material layer, and the groove penetrates through the intrinsic silicon material layer and the tunneling oxide layer along the thickness direction of the substrate. According to the preparation method of the solar cell, a relatively good preparation effect of the back contact solar cell can be realized through relatively few process steps.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a method for preparing a solar cell and a solar cell. Background Art

[0002] The back-contact cell is a solar cell structure used to improve cell efficiency. Its core design is to place all the metal electrodes of the solar cell on the back of the cell, thereby ensuring that the front of the cell is not blocked by the metal grid. This can increase the area of ​​the cell that absorbs sunlight, reduce optical losses, and improve photoelectric conversion efficiency.

[0003] In back-contact solar cells, the emitters are all placed on the back of the cell and are composed of two different types of doping regions alternating, which makes the preparation process of back-contact solar cells more complicated. Summary of the invention

[0004] Based on this, it is necessary to provide a method for preparing a solar cell and a solar cell. The method for preparing a solar cell of the present application can achieve a better preparation effect of a back-contact solar cell through fewer process steps.

[0005] In a first aspect, the present application provides a method for preparing a solar cell, comprising the following steps:

[0006] Providing a substrate having a front side and a back side disposed opposite to each other;

[0007] Preparing a tunneling oxide layer and an intrinsic silicon material layer stacked in sequence on the back side of the substrate;

[0008] The intrinsic silicon material layer is doped by laser processing to obtain a first doped silicon material layer and a second doped silicon material layer of opposite doping types, and a groove for spacing the first doped silicon material layer and the second doped silicon material layer is formed between the first doped silicon material layer and the second doped silicon material layer, and the groove penetrates the intrinsic silicon material layer and the tunneling oxide layer along the thickness direction of the substrate.

[0009] In some embodiments, doping the intrinsic silicon material layer by laser processing comprises the following steps:

[0010] Disposing a first slurry and a second slurry at different positions spaced apart on the surface of the intrinsic silicon material layer, respectively, the first slurry comprising a first doping element, the second slurry comprising a second doping element, and the first doping element and the second doping element having opposite doping types;

[0011] The first slurry and the second slurry are used to dope the intrinsic silicon material layer through laser processing.

[0012] In some embodiments, the laser power of the laser treatment is 30W~80W.

[0013] In some embodiments, the maximum width of the laser-processed spot is 100 μm to 300 μm.

[0014] In some embodiments, the spot overlap rate of the laser processing is less than 80%.

[0015] In some embodiments, the laser treatment further includes the following step: annealing the laser treated sample in a nitrogen or oxygen atmosphere.

[0016] In some embodiments, the annealing time is 5 min to 20 min.

[0017] In some embodiments, the annealing treatment is performed at a temperature of 200°C to 1000°C.

[0018] In some of the embodiments, before preparing a tunneling oxide layer and an intrinsic silicon material layer stacked in sequence on the surface of the substrate, the following step is also included: preparing a recessed portion on the back side of the substrate, wherein there is a height difference between the recessed portion and the back side of the substrate along the thickness direction of the substrate.

[0019] In some embodiments, preparing the recessed portion on the surface of the substrate comprises the following steps:

[0020] forming a mask layer on the back side of the substrate;

[0021] removing a portion of the mask layer by laser;

[0022] The back side of the substrate exposed from the mask layer is etched using an alkaline solution to form the recessed portion.

[0023] In some embodiments, a height difference between the recessed portion and the back surface of the substrate along the thickness direction of the substrate is greater than 1 μm.

[0024] In some embodiments, the thickness of the tunnel oxide layer is 1 nm to 3 nm.

[0025] In some embodiments, the intrinsic silicon material layer has a thickness of 80 nm to 300 nm.

[0026] In a second aspect, the present application provides a solar cell prepared by any of the above-mentioned methods for preparing a solar cell.

[0027] In some embodiments, the solar cell includes a substrate having a front side and a back side disposed opposite to each other, wherein the front side of the substrate has a suede structure and is provided with a first passivation anti-reflection layer;

[0028] The back side of the substrate has a recessed portion, a height difference exists between the recessed portion and the back side of the substrate along the thickness direction of the substrate, and a tunneling oxide layer, a first doped silicon material layer, and a second passivation anti-reflection layer are sequentially stacked on the recessed portion;

[0029] A tunneling oxide layer, a second doped silicon material layer, and a second passivation anti-reflection layer are sequentially stacked on the staggered back sides of the substrate and the recessed portion; the first doped silicon material layer and the second doped silicon material layer have opposite doping types; a groove is provided between the first doped silicon material layer and the second doped silicon material layer, and the groove penetrates the tunneling oxide layer along the thickness direction of the substrate; and a second passivation anti-reflection layer is provided on the groove bottom and groove wall of the groove;

[0030] The solar cell further includes a first electrode and a second electrode disposed on the second passivation anti-reflection layer, the first electrode being in electrical contact with the first doped silicon material layer, and the second electrode being in electrical contact with the second doped silicon material layer.

[0031] In the above-mentioned method for preparing solar cells, the intrinsic silicon material layer is doped by laser treatment to obtain a first doped silicon material layer and a second doped silicon material layer, respectively, and a groove for spacing the first doped silicon material layer and the second doped silicon material layer is formed between the first doped silicon material layer and the second doped silicon material layer, and the groove penetrates the intrinsic silicon material layer and the tunneling oxide layer along the thickness direction of the substrate. That is, the preparation of doped silicon material layers of different doping types on the back of the solar cell is achieved through laser treatment, and grooves are formed to achieve isolation of different types of emitters, which can reduce the production steps of the back contact cell. At the same time, the doping method of laser treatment can also improve the accuracy of the preparation of the doped area to achieve higher photoelectric conversion efficiency. The method for preparing solar cells of the present application can achieve a better preparation effect of back contact solar cells with fewer process steps. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] FIG1 is a schematic structural diagram of forming a mask layer on the back side of a substrate;

[0033] FIG2 is a schematic diagram of a structure in which a portion of the mask layer is removed based on the structure shown in FIG1 ;

[0034] FIG3 is a schematic diagram of a structure in which a recessed portion is formed and a mask layer is removed based on the structure shown in FIG2 ;

[0035] FIG4 is a schematic diagram of a structure in which a tunnel oxide layer and an intrinsic silicon material layer are formed on the basis of the structure shown in FIG3 ;

[0036] FIG5 is a schematic diagram of a structure in which a first slurry and a second slurry are formed on the basis of the structure shown in FIG4 ;

[0037] FIG6 is a schematic diagram of a structure in which a first doped silicon material layer, a second doped silicon material layer and a groove are prepared on the basis of the structure shown in FIG5 ;

[0038] FIG7 is a schematic diagram of a structure after texturing based on the structure shown in FIG6 ;

[0039] FIG8 is a schematic structural diagram of a first passivation anti-reflection layer and a second passivation anti-reflection layer formed on the basis of the structure shown in FIG7 ;

[0040] FIG. 9 is a schematic diagram showing a structure in which a first electrode and a second electrode are formed on the basis of the structure shown in FIG. 8 .

[0041] Description of Reference Numerals

[0042] 10. substrate; 20. mask layer; 30. recess; 40. tunnel oxide layer; 50. intrinsic silicon material layer; 61. first slurry; 62. second slurry; 71. first doped silicon material layer; 72. second doped silicon material layer; 80. groove; 91. first passivation anti-reflection layer; 92. second passivation anti-reflection layer; 101. first electrode; 102. second electrode. DETAILED DESCRIPTION

[0043] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0045] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0046] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, "plurality" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0047] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0048] 1 to 9, an embodiment of the present application provides a method for preparing a solar cell, comprising the following steps:

[0049] Providing a substrate 10, the substrate 10 having a front side and a back side arranged opposite to each other;

[0050] A tunneling oxide layer 40 and an intrinsic silicon material layer 50 are sequentially stacked on the back side of the substrate 10;

[0051] The intrinsic silicon material layer 50 is doped by laser processing to obtain a first doped silicon material layer 71 and a second doped silicon material layer 72 of opposite doping types, and at the same time, a groove 80 is formed between the first doped silicon material layer 71 and the second doped silicon material layer 72 to separate the first doped silicon material layer 71 and the second doped silicon material layer 72. The groove 80 penetrates the intrinsic silicon material layer 50 and the tunneling oxide layer 40 along the thickness direction of the substrate 10.

[0052] In the above-mentioned method for preparing solar cells, the intrinsic silicon material layer 50 is doped by laser processing to obtain a first doped silicon material layer 71 and a second doped silicon material layer 72, respectively, and a groove 80 is formed between the first doped silicon material layer 71 and the second doped silicon material layer 72 for spacing the first doped silicon material layer 71 and the second doped silicon material layer 72, and the groove 80 penetrates the intrinsic silicon material layer 50 and the tunneling oxide layer 40 along the thickness direction of the substrate 10. That is, the preparation of doped silicon material layers of different doping types on the back of the solar cell is achieved through laser processing, and the groove 80 is formed to achieve the isolation of different types of emitters, which can reduce the production steps of the back contact cell. At the same time, the doping method of laser processing can also improve the accuracy of the preparation of the doped area to achieve higher photoelectric conversion efficiency. The method for preparing solar cells of the present application can achieve a better preparation effect of back contact solar cells with fewer process steps.

[0053] In some embodiments, the method for preparing a solar cell comprises the following steps:

[0054] S10: providing a substrate 10 having a front side and a back side arranged opposite to each other; preparing a recessed portion 30 on the back side of the substrate 10 , and a height difference between the recessed portion 30 and the back side of the substrate 10 along the thickness direction of the substrate 10 .

[0055] In some embodiments, preparing the recessed portion 30 on the back side of the substrate 10 includes the following steps:

[0056] forming a mask layer 20 on the back side of the substrate 10;

[0057] removing a portion of the mask layer 20 by laser;

[0058] The back surface of the substrate 10 exposed from the mask layer 20 is etched using an alkaline solution to form a recessed portion 30 .

[0059] The recessed portion 30 is formed on the back side, so that a certain height difference can be formed between the recessed portion 30 and the back side of the substrate 10. The height difference is matched with the preparation thickness of each film layer, so as to facilitate the isolation between doped silicon material layers of different doping types.

[0060] 1 to 3 , FIG1 is a schematic diagram of a structure in which a mask layer 20 is formed on the back side of a substrate 10; FIG2 is a schematic diagram of a structure in which a portion of the mask layer 20 is removed based on the structure shown in FIG1 ; and FIG3 is a schematic diagram of a structure in which a recessed portion 30 is formed and the mask layer 20 is removed based on the structure shown in FIG2 .

[0061] In some embodiments, a height difference between the recessed portion 30 and the back surface of the substrate 10 along the thickness direction of the substrate 10 is 1 μm or more.

[0062] In some embodiments, the material of the mask layer 20 includes silicon oxide.

[0063] In some of the embodiments, the mask preparation method includes at least one of low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, physical vapor deposition, catalytic chemical vapor deposition and atomic layer deposition.

[0064] In some of the embodiments, a portion of the mask layer 20 is removed by laser, the laser wavelength is 532 nm, the laser power is 30 W to 80 W, the laser spot size is a square spot of 100 μm to 300 μm, and the spot overlap rate in the horizontal direction is controlled below 80%.

[0065] In some embodiments, the alkali solution includes an alkali solution and water in a volume ratio of 1:10.

[0066] In some embodiments, the alkaline solution includes at least one of NaOH and KOH.

[0067] In some embodiments, the concentration of the alkaline solution is 45 wt % to 55 wt %.

[0068] Optionally, the concentration of the alkaline solution is 45wt%, 46wt%, 47wt%, 48wt%, 49wt%, 50wt%, 51wt%, 52wt%, 53wt%, 54wt% or 55wt%, or, the concentration of the alkaline solution may be within the range between any two of the above concentrations.

[0069] In some embodiments, the temperature for etching the back side of the substrate 10 exposed from the mask layer 20 with an alkaline solution is 65° C. to 90° C.

[0070] Optionally, the temperature for etching the back side of the substrate 10 exposed to the mask layer 20 using the alkaline solution is 65°C, 70°C, 75°C, 80°C, 85°C or 90°C, or, the temperature for etching the back side of the substrate 10 exposed to the mask layer 20 using the alkaline solution can also be within the range between any two of the above temperatures.

[0071] In some embodiments, the time for etching the back side of the substrate 10 exposed from the mask layer 20 with the alkaline solution is 180s to 420s.

[0072] Optionally, the time for using alkaline solution to etch the back side of the substrate 10 exposed to the mask layer 20 is 180s, 200s, 220s, 250s, 280s, 300s, 320s, 350s, 380s, 400s or 420s, or, the time for using alkaline solution to etch the back side of the substrate 10 exposed to the mask layer 20 can also be within the range between any two of the above times.

[0073] Within the range of the process parameters for etching the back surface of the substrate 10 exposed from the mask layer 20 using the alkaline solution, a better preparation effect of the recessed portion 30 can be achieved.

[0074] In some embodiments, after forming the recessed portion 30, the following steps are further included:

[0075] The remaining mask layer 20 is removed using an acid solution.

[0076] In some embodiments, the acid solution includes hydrofluoric acid solution and water in a volume ratio of 1:20.

[0077] In some embodiments, the concentration of the hydrofluoric acid solution is 45 wt % to 50 wt %.

[0078] Optionally, the concentration of the hydrofluoric acid solution is 45wt%, 46wt%, 47wt%, 48wt%, 49wt% or 50wt%, or, the concentration of the hydrofluoric acid solution may also be within the range between any two of the above concentrations.

[0079] In some embodiments, the remaining mask layer 20 is removed using an acid solution at room temperature.

[0080] In some embodiments, the time for removing the remaining mask layer 20 using the acid solution is 60 seconds to 240 seconds.

[0081] Optionally, the time for removing the remaining mask layer 20 using acid is 60s, 80s, 100s, 120s, 140s, 160s, 180s, 200s, 220s or 240s, or the time for removing the remaining mask layer 20 using acid may also be within the range between any two of the above times.

[0082] S20 : ​​preparing a tunneling oxide layer 40 and an intrinsic silicon material layer 50 stacked in sequence on the back side of the substrate 10 .

[0083] Referring to Fig. 4, Fig. 4 is a schematic diagram of a structure in which a tunneling oxide layer 40 and an intrinsic silicon material layer 50 are formed on the basis of the structure shown in Fig. 3. It can be understood that the tunneling oxide layer 40 and the intrinsic silicon material layer 50 stacked in sequence are prepared on the back side of the substrate 10, which means that the back side of the substrate 10 and the recessed portion 30 are both provided with the tunneling oxide layer 40 and the intrinsic silicon material layer 50 stacked in sequence.

[0084] In some embodiments, the material of the tunnel oxide layer 40 includes silicon oxide.

[0085] In some embodiments, the thickness of the tunnel oxide layer 40 is 1 nm to 3 nm.

[0086] Optionally, the thickness of the tunnel oxide layer 40 is 1 nm, 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm, 2 nm, 2.2 nm, 2.4 nm, 2.6 nm, 2.8 nm or 3 nm, or the thickness of the tunnel oxide layer 40 may be within a range between any two of the above thicknesses.

[0087] In some embodiments, the tunnel oxide layer 40 is formed by low pressure chemical vapor deposition.

[0088] In some embodiments, the tunnel oxide layer 40 is deposited at a temperature of 500° C. to 800° C.

[0089] Optionally, the deposition temperature of the tunnel oxide layer 40 is 500° C., 550° C., 600° C., 650° C., 700° C., 750° C. or 800° C., or the deposition temperature of the tunnel oxide layer 40 may also be within a range between any two of the above deposition temperatures.

[0090] In some embodiments, the intrinsic silicon material layer 50 has a thickness of 80 nm to 300 nm.

[0091] Optionally, the thickness of the intrinsic silicon material layer 50 is 80 nm, 100 nm, 120 nm, 150 nm, 180 nm, 200 nm, 220 nm, 250 nm, 280 nm or 300 nm, or the thickness of the intrinsic silicon material layer 50 may also be within the range between any two of the above thicknesses.

[0092] In some embodiments, the intrinsic silicon material layer 50 is an intrinsic polysilicon layer.

[0093] In some embodiments, the intrinsic silicon material layer 50 is prepared by low pressure chemical vapor deposition.

[0094] In some embodiments, during the preparation of the intrinsic silicon material layer 50 , the silane flow rate is 300 sccm-1000 sccm.

[0095] Optionally, in the preparation of the intrinsic silicon material layer 50 , the silane flow rate is 300 sccm, 400 sccm, 500 sccm, 600 sccm, 700 sccm, 800 sccm, 900 sccm or 1000 sccm, or the silane flow rate may also be within the range between any two of the above flow rates.

[0096] In some embodiments, the deposition temperature of the intrinsic silicon material layer 50 is 500° C. to 900° C.

[0097] Optionally, the deposition temperature of the intrinsic silicon material layer 50 is 500°C, 550°C, 600°C, 650°C, 700°C, 750°C, 800°C, 850°C or 900°C, or, the deposition temperature of the intrinsic silicon material layer 50 may also be within the range between any two of the above temperatures.

[0098] S30: Disposing a first slurry 61 and a second slurry 62 at different positions on the surface of the intrinsic silicon material layer 50 respectively, wherein the first slurry 61 includes a first doping element, and the second slurry 62 includes a second doping element, and the doping types of the first doping element and the second doping element are opposite.

[0099] Referring to FIG. 5 , FIG. 5 is a schematic diagram showing a structure in which a first slurry 61 and a second slurry 62 are formed on the basis of the structure shown in FIG. 4 .

[0100] In some embodiments, before the first slurry 61 and the second slurry 62 are doped with the intrinsic silicon material layer 50 by laser processing, the following steps are also included:

[0101] The first slurry 61 and the second slurry 62 are dried and solidified.

[0102] In some embodiments, the first slurry 61 and the second slurry 62 are boron slurry and phosphorus slurry, respectively.

[0103] In some of the embodiments, the printing width of the phosphor paste is 300 μm to 500 μm.

[0104] Optionally, the printing width of the phosphor paste is 300 μm, 350 μm, 400 μm, 450 μm or 500 μm, or, the printing width of the phosphor paste may also be within a range between any two of the above widths.

[0105] In some of the embodiments, the solid content of the phosphorus slurry is 15% to 35%.

[0106] Optionally, the solid content of the phosphorus slurry is 15%, 20%, 25%, 30% or 35%, or the solid content of the phosphorus slurry may also be within a range between any two of the above solid contents.

[0107] In some embodiments, the viscosity of the phosphorus slurry is 20 Pa·s to 50 Pa·s.

[0108] Optionally, the viscosity of the phosphorus slurry is 20 Pa·s, 25 Pa·s, 30 Pa·s, 35 Pa·s, 40 Pa·s, 45 Pa·s or 50 Pa·s, or, the viscosity of the phosphorus slurry may also be within the range between any two of the above viscosities.

[0109] In some embodiments, the printing width of the boron paste is 500 μm to 700 μm.

[0110] Optionally, the printing width of the boron paste is 500 μm, 550 μm, 600 μm, 650 μm or 700 μm, or the printing width of the boron paste may also be within a range between any two of the above widths.

[0111] In some embodiments, the solid content of the boron slurry is 20% to 55%.

[0112] Optionally, the solid content of the boron slurry is 20%, 25%, 30%, 35%, 40%, 45%, 50% or 55%, or, the solid content of the boron slurry may also be within the range between any two of the above solid contents.

[0113] In some embodiments, the viscosity of the boron slurry is 20 Pa·s to 50 Pa·s.

[0114] Optionally, the viscosity of the boron slurry is 20 Pa·s, 25 Pa·s, 30 Pa·s, 35 Pa·s, 40 Pa·s, 45 Pa·s or 50 Pa·s, or, the viscosity of the boron slurry may also be within the range between any two of the above viscosities.

[0115] Within the above parameter ranges of the phosphorus paste and the boron paste, a better printing effect of the paste on the intrinsic silicon material layer 50 can be achieved, thereby achieving a more uniform doping effect through laser processing.

[0116] S40: The first slurry 61 and the second slurry 62 are doped with the intrinsic silicon material layer 50 through laser processing to obtain a first doped silicon material layer 71 and a second doped silicon material layer 72 respectively, and a groove 80 is formed between the first doped silicon material layer 71 and the second doped silicon material layer 72 to separate the first doped silicon material layer 71 and the second doped silicon material layer 72. The groove 80 penetrates the intrinsic silicon material layer 50 and the tunneling oxide layer 40 along the thickness direction of the substrate 10.

[0117] Referring to Fig. 6, Fig. 6 is a schematic diagram of the structure of the first doped silicon material layer 71, the second doped silicon material layer 72 and the groove 80 prepared on the basis of the structure shown in Fig. 5. It can be understood that the groove 80 can be prepared by laser processing in the area where the slurry is not printed between the area where the first slurry 61 is printed and the area where the second slurry is printed, thereby achieving isolation of the first doped silicon material layer 71 and the second doped silicon material layer 72.

[0118] In some embodiments, the laser power of the laser treatment is 30W~80W.

[0119] Optionally, the laser power of the laser processing is 30 W, 40 W, 50 W, 60 W, 70 W or 80 W, or, the laser power of the laser processing may also be within a range between any two of the above powers.

[0120] In some of the embodiments, the maximum width of the laser processed spot is 100 μm to 300 μm.

[0121] Optionally, the maximum width of the laser-processed light spot is 100 μm, 150 μm, 200 μm, 250 μm or 300 μm, or the maximum width of the laser-processed light spot may also be within a range between any two of the above widths.

[0122] In some of the embodiments, the spot overlap rate of the laser processing is less than 80%.

[0123] In some embodiments, the laser processed spot is a square spot.

[0124] In some embodiments, the scanning width of the laser treatment on the area where the boron paste is printed is 300 μm to 800 μm.

[0125] Optionally, the scanning width of the region where the boron paste is printed by laser treatment is 300 μm, 400 μm, 500 μm, 600 μm, 700 μm or 800 μm, or the scanning width of the region where the boron paste is printed by laser treatment may also be within the range between any two of the above widths.

[0126] In some embodiments, the scanning width of the laser processing on the area where the phosphor paste is printed is 200 μm to 600 μm.

[0127] Optionally, the scanning width of the area where the phosphor paste is printed by laser processing is 200 μm, 300 μm, 400 μm, 500 μm or 600 μm, or the scanning width of the area where the phosphor paste is printed by laser processing may also be within the range between any two of the above widths.

[0128] Within the range of the above parameters of the laser processing, a better doping effect on the intrinsic silicon material layer 50 can be achieved by the slurry.

[0129] In some embodiments, the width of the groove 80 is 100 μm to 200 μm.

[0130] Optionally, the width of the groove 80 is 100 μm, 120 μm, 140 μm, 160 μm, 180 μm or 200 μm, or the width of the groove 80 may also be within a range between any two of the above widths.

[0131] In some embodiments, the laser treatment further includes the following step: annealing the laser treated sample in a nitrogen or oxygen atmosphere.

[0132] In some embodiments, the annealing time is 5 min to 20 min.

[0133] Optionally, the annealing time is 5 min, 8 min, 10 min, 12 min, 15 min, 18 min or 20 min, or, the annealing time may also be within the range between any two of the above times.

[0134] In some embodiments, the annealing temperature is 200°C to 1000°C.

[0135] Optionally, the temperature of the annealing treatment is 200° C., 400° C., 600° C., 800° C. or 1000° C., or, the temperature of the annealing treatment may also be within a range between any two of the above temperatures.

[0136] S50: Texturing is performed on the sample after the groove 80 is prepared.

[0137] 7 is a schematic diagram of a structure after texturing based on the structure shown in FIG6 . It can be understood that texturing the sample after preparing the groove 80 can form a velvet structure on the front side of the substrate 10 and the bottom of the groove 80 .

[0138] In some of the embodiments, the sample is texturized using an alkaline solution.

[0139] In some embodiments, the texturing temperature is 70°C to 85°C.

[0140] Optionally, the texturing temperature is 70°C, 72°C, 75°C, 78°C, 80°C, 82°C or 85°C, or, the texturing temperature may also be within the range between any two of the above temperatures.

[0141] In some of the embodiments, the texturing time is 300s to 420s.

[0142] Optionally, the texturing time is 300s, 320s, 340s, 360s, 380s, 400s or 420s, or, the texturing time may also be within the range between any two of the above times.

[0143] S60: preparing a first passivation anti-reflection layer 91 and a second passivation anti-reflection layer 92 on the front side and the back side of the substrate 10 respectively.

[0144] Referring to Fig. 8, Fig. 8 is a schematic diagram of a structure in which a first passivation anti-reflection layer 91 and a second passivation anti-reflection layer 92 are formed on the basis of the structure shown in Fig. 7. It can be understood that the first passivation anti-reflection layer 91 covers the front surface of the substrate 10, and the second passivation anti-reflection layer 92 covers the back surface of the substrate 10, as well as the bottom and wall of the groove 80.

[0145] In some embodiments, the first passivation anti-reflection layer 91 includes a first passivation film and a first anti-reflection film that are stacked, and the first anti-reflection film is disposed on a surface of the first passivation film that is away from the substrate 10 .

[0146] In some embodiments, the material of the first passivation film includes aluminum oxide.

[0147] In some embodiments, the thickness of the first passivation film is 3 nm to 10 nm.

[0148] Optionally, the thickness of the first passivation film is 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm or 10 nm, or the thickness of the first passivation film may also be within a range between any two of the above thicknesses.

[0149] In some embodiments, the first passivation film is prepared by atomic layer deposition.

[0150] In some embodiments, a material of the first anti-reflection film includes at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0151] In some embodiments, the thickness of the first anti-reflection film is 70 nm to 110 nm.

[0152] Optionally, the thickness of the first anti-reflection film is 70 nm, 80 nm, 90 nm, 100 nm or 110 nm, or the thickness of the first anti-reflection film may also be within a range between any two of the above thicknesses.

[0153] In some embodiments, the refractive index of the first anti-reflection film is 2-2.4.

[0154] Optionally, the refractive index of the first anti-reflection film is 2, 2.1, 2.2, 2.3 or 2.4, or the refractive index of the first anti-reflection film may also be within a range between any two of the above reflectivities.

[0155] In some embodiments, the first anti-reflection film is prepared by plasma enhanced chemical vapor deposition.

[0156] In some embodiments, the second passivation anti-reflection layer 92 includes a second passivation film and a second anti-reflection film which are stacked, and the second anti-reflection film is disposed on a surface of the second passivation film away from the substrate 10 .

[0157] In some embodiments, the material of the second passivation film includes aluminum oxide.

[0158] In some embodiments, the second passivation film has a thickness of 3 nm to 10 nm.

[0159] Optionally, the thickness of the second passivation film is 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm or 10 nm, or the thickness of the second passivation film may also be within a range between any two of the above thicknesses.

[0160] In some embodiments, the second passivation film is prepared by atomic layer deposition.

[0161] In some embodiments, a material of the second anti-reflection film includes at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0162] In some embodiments, the second anti-reflection film has a thickness of 70 nm to 110 nm.

[0163] Optionally, the thickness of the second anti-reflection film is 70 nm, 80 nm, 90 nm, 100 nm or 110 nm, or the thickness of the second anti-reflection film may also be within a range between any two of the above thicknesses.

[0164] In some embodiments, the refractive index of the second anti-reflection film is 2-2.4.

[0165] Optionally, the refractive index of the second anti-reflection film is 2, 2.1, 2.2, 2.3 or 2.4, or the refractive index of the second anti-reflection film may also be within a range between any two of the above reflectivities.

[0166] In some embodiments, the first anti-reflection film is prepared by plasma enhanced chemical vapor deposition.

[0167] S70 : preparing a first electrode 101 and a second electrode 102 on the surface of the second passivation anti-reflection layer 92 , wherein the first electrode 101 is in electrical contact with the first doped silicon material layer 71 , and the second electrode 102 is in electrical contact with the second doped silicon material layer 72 .

[0168] Referring to FIG. 9 , FIG. 9 is a schematic diagram showing a structure in which a first electrode 101 and a second electrode 102 are formed on the basis of the structure shown in FIG. 8 .

[0169] In some embodiments, the first electrode 10191 and the second electrode 10292 are prepared by sintering silver paste.

[0170] In some embodiments, the sintering temperature is 700°C to 900°C.

[0171] Optionally, the sintering temperature is 700° C., 750° C., 800° C., 850° C. or 900° C., or the sintering temperature may also be within a range between any two of the above temperatures.

[0172] Yet another embodiment of the present application provides a solar cell, which is prepared by any of the above-mentioned methods for preparing a solar cell.

[0173] Referring again to FIG. 9 , in some embodiments, the solar cell includes a substrate 10 having a front side and a back side disposed opposite to each other, and the front side of the substrate 10 has a suede structure and is provided with a first passivation anti-reflection layer 91 ;

[0174] The back side of the substrate 10 has a recessed portion 30, and there is a height difference between the recessed portion 30 and the back side of the substrate 10 along the thickness direction of the substrate 10. The recessed portion 30 is sequentially stacked with a tunneling oxide layer 40, a first doped silicon material layer 71, and a second passivation anti-reflection layer 92;

[0175] A tunneling oxide layer 40, a second doped silicon material layer 72, and a second passivation anti-reflection layer 92 are sequentially stacked on the staggered back sides of the substrate 10 and the recessed portion 30; the first doped silicon material layer 71 and the second doped silicon material layer 72 have opposite doping types; a groove 80 is provided between the first doped silicon material layer 71 and the second doped silicon material layer 72, and the groove 80 penetrates the tunneling oxide layer 40 along the thickness direction of the substrate 10; and a second passivation anti-reflection layer 92 is provided on the groove bottom and groove wall of the groove 80;

[0176] The solar cell further includes a first electrode 101 and a second electrode 102 disposed on the second passivation anti-reflection layer 92 . The first electrode 101 is in electrical contact with the first doped silicon material layer 71 , and the second electrode 102 is in electrical contact with the second doped silicon material layer 72 .

[0177] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0178] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims, and the description and drawings may be used to interpret the contents of the claims.

Claims

1. A method for preparing a solar cell, characterized in that: The steps include: Providing a substrate having a front side and a back side disposed opposite to each other; Preparing a tunneling oxide layer and an intrinsic silicon material layer stacked in sequence on the back side of the substrate; The intrinsic silicon material layer is doped by laser processing to obtain a first doped silicon material layer and a second doped silicon material layer of opposite doping types, and a groove for spacing the first doped silicon material layer and the second doped silicon material layer is formed between the first doped silicon material layer and the second doped silicon material layer, and the groove penetrates the intrinsic silicon material layer and the tunneling oxide layer along the thickness direction of the substrate.

2. The method for preparing a solar cell according to claim 1, characterized in that: Doping the intrinsic silicon material layer by laser processing comprises the following steps: Disposing a first slurry and a second slurry at different positions spaced apart on the surface of the intrinsic silicon material layer, respectively, the first slurry comprising a first doping element, the second slurry comprising a second doping element, and the first doping element and the second doping element having opposite doping types; The first slurry and the second slurry are used to dope the intrinsic silicon material layer through laser processing.

3. The method for preparing a solar cell according to claim 1, characterized in that: The laser processing satisfies at least one of the following characteristics: (1) The laser power of the laser treatment is 30W~80W; (2) The maximum width of the laser-processed spot is 100 μm to 300 μm; (3) The spot overlap rate of the laser treatment is less than 80%.

4. The method for preparing a solar cell according to claim 1, characterized in that: The method further comprises the following steps after the laser treatment: annealing the sample after the laser treatment in a nitrogen or oxygen atmosphere.

5. The method for preparing a solar cell according to claim 3, characterized in that: The annealing time is 5 min to 20 min; and / or, The temperature of the annealing treatment is 200°C to 1000°C.

6. The method for preparing a solar cell according to claim 1, characterized in that: Before preparing the tunneling oxide layer and the intrinsic silicon material layer stacked in sequence on the surface of the substrate, the following step is also included: preparing a recessed portion on the back side of the substrate, wherein there is a height difference between the recessed portion and the back side of the substrate along the thickness direction of the substrate.

7. The method for preparing a solar cell according to claim 6, characterized in that: Preparing a recessed portion on the surface of the substrate comprises the following steps: forming a mask layer on the back side of the substrate; removing a portion of the mask layer by laser; The back side of the substrate exposed from the mask layer is etched using an alkaline solution to form the recessed portion.

8. The method for preparing a solar cell according to claim 7, characterized in that: A height difference between the recessed portion and the back surface of the substrate along the thickness direction of the substrate is greater than 1 μm; and / or, The thickness of the tunnel oxide layer is 1 nm to 3 nm; and / or, The thickness of the intrinsic silicon material layer is 80nm-300nm.

9. A solar cell, characterized in that: The solar cell is prepared by the method for preparing the solar cell according to any one of claims 1 to 8.

10. The solar cell according to claim 9, characterized in that: The invention comprises a substrate having a front side and a back side arranged opposite to each other, wherein the front side of the substrate has a suede structure and is provided with a first passivation anti-reflection layer; The back side of the substrate has a recessed portion, a height difference exists between the recessed portion and the back side of the substrate along the thickness direction of the substrate, and a tunneling oxide layer, a first doped silicon material layer, and a second passivation anti-reflection layer are sequentially stacked on the recessed portion; A tunneling oxide layer, a second doped silicon material layer, and a second passivation anti-reflection layer are sequentially stacked on the staggered back sides of the substrate and the recessed portion; the first doped silicon material layer and the second doped silicon material layer have opposite doping types; a groove is provided between the first doped silicon material layer and the second doped silicon material layer, and the groove penetrates the tunneling oxide layer along the thickness direction of the substrate; and a second passivation anti-reflection layer is provided on the groove bottom and groove wall of the groove; The solar cell further includes a first electrode and a second electrode disposed on the second passivation anti-reflection layer, the first electrode being in electrical contact with the first doped silicon material layer, and the second electrode being in electrical contact with the second doped silicon material layer.

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