FPGA (Field Programmable Gate Array) computing board
Through the interconnection bus and fault detection switching mechanism between each chip in the FPGA computing board, an uncentralized design is realized, solving the problem of work interruption of the traditional FPGA computing board during main control failure, improving stability and reducing The failure rate is also realized. The efficient parallel writing function is realized.
Patent Information
- Application Number
- CN202411261020.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-10
- Publication Date
- 2024-12-27
AI Technical Summary
Traditional FPGA computing boards fail to work when the main controller fails, and lack a failover mechanism, resulting in high system stability and failure rate.
Design an uncentralized FPGA computing board. Each FPGA chip communicates with other chips and external devices, has fault detection and main control chip switching functions, ensuring that the system can continue to operate even if the main control chip or other chip fails, and Implement parallel writing function.
It improves system stability, reduces the failure rate, and greatly reduces the writing time, avoiding the long-term consumption of traditional writing in sequence.
Smart Images
Figure CN119201555A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of computing boards, and in particular relates to an FPGA computing board. Background Art
[0002] The internal logic of traditional chips is fixed and cannot be changed once they are taped out. Compared with traditional chips, FPGA chips have higher versatility and greater flexibility. They can change the internal circuit logic at any time according to needs to meet different computing requirements. Therefore, FPGA computing boards occupy an important position with their flexible computing capabilities.
[0003] Traditional FPGA computing boards consist of a main controller and multiple FPGA chips on the board. The main controller controls the multiple FPGA chips, is responsible for the communication between the inside and outside of the computing board, and controls the on / off of each FPGA chip, as well as the burning of bit files, etc. The main controller is the core of the FPGA computing board, but in actual applications, once the main controller fails, the entire computing board will not work. Summary of the invention
[0004] Based on this, in order to solve the above technical problems, a FPGA computing board is provided.
[0005] The technical solution adopted by the present invention is as follows:
[0006] An FPGA computing board includes a plurality of FPGA chips, wherein each FPGA chip is communicatively connected with other FPGA chips and external devices, and one FPGA chip is used as a default master control chip;
[0007] After the computing board is powered on, each FPGA chip periodically identifies whether other FPGA chips have failed. When a chip other than the main control chip fails, the main control chip shields the failed chip. When the main control chip fails, the chip with the highest master control priority among other non-faulty chips is switched to the main control chip.
[0008] The present invention provides an FPGA computing board which omits a main controller and realizes a decentralized design. Each FPGA chip can be used as a controller to control other FPGA chips. Even if an FPGA chip fails, the remaining FPGA chips can continue to work, thereby improving system stability and reducing the failure rate of the computing board. BRIEF DESCRIPTION OF THE DRAWINGS
[0009] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments:
[0010] Figure 1 A schematic diagram of the structure of an FPGA computing board provided in an embodiment of the present invention. DETAILED DESCRIPTION
[0011] The following will illustrate the implementation methods of the present invention in conjunction with the drawings in the specification. It should be noted that the implementation methods involved in this specification are not exhaustive and do not represent the only implementation methods of the present invention. The following corresponding embodiments are only for the purpose of clearly illustrating the invention content of the patent of the present invention, and are not intended to limit its implementation methods. For ordinary technicians in this field, different forms of changes and modifications can be made on the basis of the description of this embodiment. All obvious changes or modifications that belong to the technical concept and invention content of the present invention are also within the scope of protection of the present invention.
[0012] like Figure 1 As shown, an embodiment of the present application provides an FPGA computing board, including multiple FPGA chips 11 and an interconnection bus 12.
[0013] Multiple FPGA chips 11 and interconnection buses 12 are arranged on the board.
[0014] Each FPGA chip 11 is communicatively connected with other FPGA chips 11 and external devices 2 via an interconnection bus 12, and one of the FPGA chips serves as a default master control chip.
[0015] The FPGA computing board has the functions of fault chip detection and main control chip switching: after the computing board is powered on, each FPGA chip periodically identifies whether other FPGA chips are faulty. When a chip other than the main control chip fails, the main control chip shields the faulty chip (no longer communicates with it) to ensure that the computing board can continue to work. When the main control chip fails, the chip with the highest master control priority among other non-faulty chips is switched to the main control chip, which also ensures that the computing board can continue to work.
[0016] In order to realize the above functions, the FPGA chip 11 is configured as follows:
[0017] S11. After the computing board is powered on, it periodically sends normal working signals to other FPGA chips.
[0018] S12. According to the received normal working signal, the FPGA chip that does not send the normal working signal is regarded as the faulty chip; when the chip is the main control chip, the faulty chip is shielded; when the chip is not the main control chip, it is determined whether the main control chip is the faulty chip, and if so, further determination /
[0019] The above functions are explained below using 6 FPGA chips as an example.
[0020] The 6 FPGA chips are numbered 1-6. After the computing board is powered on, chip No. 1 is the default master chip and controls other chips. The master priority of chips No. 2-6 decreases in sequence. That is, when chip No. 1 fails, chip No. 2 becomes the master chip. When chip No. 2 fails, chip No. 3 becomes the master chip, and so on.
[0021] Each chip will periodically send a normal working signal to other chips to indicate that it is working normally. If a chip fails, it will obviously not be able to send the signal. Therefore, each chip can identify which chips are working normally and which chips are failing based on the normal working signals received.
[0022] Assuming that chip No. 6 fails, it cannot send normal working signals. When main control chip No. 1 finds that chip No. 6 is a faulty chip, it will be shielded.
[0023] When chips 2-5 find that main control chip No. 1 is a faulty chip, chip No. 2 finds that it has the highest master control priority among chips 2-5, so it switches itself to the master control chip. At the same time, chips 3-5 find that chip No. 2 has the highest master control priority, so they use chip No. 2 as the master control chip.
[0024] The control of the main control chip over other chips may include controlling the power on or off of other chips.
[0025] The FPGA computing board also has a parallel burning function: after each FPGA chip receives the burning command, it is paired in pairs according to the preset pairing configuration. The two paired FPGA chips take turns to burn the bit file of the paired FPGA chip. After the burning is completed, if there are still chips that have not been burned, the main control chip will specify the chip to burn the bit file of the chip that has not been burned.
[0026] It should be pointed out that if the number of FPGA chips is an even number and they all work normally, there will be no chips that have not completed the programming after pairing and burning. However, since the chip may fail, that is, one of the two paired chips may be a faulty chip, it is obvious that the other chip has not completed the programming although it has been paired. In addition, for the scenario where the number of FPGA chips is an odd number and they all work normally, it is obvious that one of the chips cannot be paired. Therefore, the main control chip needs to designate a chip for burning for the chip that has not completed the programming.
[0027] In order to realize the above functions, the FPGA chip 11 is configured as follows:
[0028] S21. After receiving the programming command, determine the paired FPGA chip according to the preset pairing configuration.
[0029] S22. For the two paired FPGA chips, if both have not completed the burning, the paired FPGA chips are burned with files in turn. If one of the FPGA chips has completed the burning, only the paired FPGA chip is used to burn the files.
[0030] S23. When the present chip is the master chip, determine whether there is an unburned FPGA chip among the unshielded FPGA chips. If so, specify a paired FPGA chip for the unburned FPGA chip. If not, the burning is terminated.
[0031] In this embodiment, the strategy for specifying the paired FPGA chips may be:
[0032] If the number of FPGA chips that have not been burned is 1, any FPGA chip that has been burned is designated as a paired FPGA chip.
[0033] If the number of FPGA chips that have not been burned is an even number greater than 1, the paired FPGA chips are designated in pairs.
[0034] If the number of FPGA chips that have not completed burning is an odd number greater than 1, any FPGA chip that has completed burning is added, and the paired FPGA chips are designated in a pairing manner.
[0035] S24. Determine the paired FPGA chip according to the designation of the main control chip and execute S22.
[0036] Taking 8 chips as an example (numbered 1-8), the pairing configuration can be:
[0037] Chip 1 is paired with chip 2, chip 3 is paired with chip 4, chip 5 is paired with chip 6, and chip 7 is paired with chip 8.
[0038] According to the above configuration, each chip can determine the paired FPGA chip.
[0039] The burning process can be divided into two rounds. For example, in the first round, chip No. 1, chip No. 3, chip No. 5 and chip No. 7 are used as the active burning parties to burn the passive burning parties chip No. 2, chip No. 4, chip No. 6 and chip No. 8 respectively. In the second round, chip No. 2, chip No. 4, chip No. 6 and chip No. 8 are used as the active burning parties to burn the passive burning parties chip No. 1, chip No. 3, chip No. 5 and chip No. 7 respectively.
[0040] After the above burning process, if there is no faulty chip in chips 1-8, the burning is completed.
[0041] If chip No. 3 is a faulty chip, you need to specify a matching FPGA chip for chip No. 4. For example, you can specify chip No. 1. Since chip No. 1 has been burned, only chip No. 1 will burn chip No. 4.
[0042] If chip No. 3 and chip No. 5 are both faulty chips, you need to specify a paired FPGA chip for chip No. 4 and chip No. 6. At this time, let chip No. 4 and chip No. 6 pair with each other and take turns to burn each other.
[0043] If chip No. 3, chip No. 5 and chip No. 7 are all faulty chips, you need to specify paired FPGA chips for chip No. 4, chip No. 6 and chip No. 8. At this time, add any FPGA chip that has completed burning, and specify the paired FPGA chips in pairs. For example, you can add chip No. 1, let chip No. 1 and chip No. 4 pair each other, and chip No. 6 and chip No. 8 pair each other. Since chip No. 1 has completed burning, only chip No. 1 will burn chip No. 4, while chip No. 6 and chip 8 will take turns to burn each other.
[0044] From the above, it can be seen that the FPGA computing board provided in the embodiment of the present application omits the main controller and realizes a decentralized design. Each FPGA chip can be used as a controller to control other FPGA chips. Even if an FPGA chip fails, the remaining FPGA chips can continue to work, thereby improving the system stability and reducing the failure rate of the computing board.
[0045] In addition, the FPGA computing board of the embodiment of the present application also has a parallel programming function, which greatly reduces the time used to program the bit file. However, the traditional FPGA computing board requires the main controller to program the remaining FPGA chips in sequence, which takes a long time.
[0046] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.
Claims
1. An FPGA computing board, comprising a plurality of FPGA chips, characterized in that: Each FPGA chip is connected to other FPGA chips and external devices, and one of the FPGA chips is used as the default master chip; After the computing board is powered on, each FPGA chip periodically identifies whether other FPGA chips have failed. When a chip other than the main control chip fails, the main control chip shields the failed chip. When the main control chip fails, the chip with the highest master control priority among other non-faulty chips is switched to the main control chip.
2. The FPGA computing board according to claim 1, characterized in that: Each FPGA chip is connected to communicate with other FPGA chips and external devices through an interconnection bus.
3. The FPGA computing board according to claim 1, characterized in that: The FPGA chip is configured as follows: S11, after the computing board is powered on, it periodically sends normal working signals to other FPGA chips; S12. According to the normal working signal received, the FPGA chip that does not send the normal working signal is regarded as a faulty chip. When the chip is the main control chip, the faulty chip is shielded. When the chip is a non-main control chip, it is determined whether the main control chip is a faulty chip. If so, it is further determined whether the main control priority of the chip is the highest among all the current non-faulty chips. If so, the chip is switched to the main control chip. Otherwise, the chip with the highest main control priority among all the current non-faulty chips is used as the main control chip.
4. The FPGA computing board according to claim 1, characterized in that: After each FPGA chip receives the burning command, it is paired up according to the preset pairing configuration. The two paired FPGA chips take turns to burn the files of the paired FPGA chip. After the burning is completed, if there are still chips that have not been burned, the master control chip will designate a chip to burn the chips that have not been burned.
5. The FPGA computing board according to claim 4, characterized in that: The FPGA chip is also configured as: S21, after receiving the programming command, determining the paired FPGA chip according to the preset pairing configuration; S22, for the two paired FPGA chips, if both have not completed the burning, the paired FPGA chips are burned with files in turn; if one of the FPGA chips has completed the burning, only the paired FPGA chip is used to burn the files; S23, when the chip is the main control chip, determine whether there is an FPGA chip that has not been completed in the unshielded FPGA chip, if so, specify a paired FPGA chip for the FPGA chip that has not been completed, if not, the programming is terminated; S24. Determine the paired FPGA chip according to the designation of the main control chip and execute S22.
6. The FPGA computing board according to claim 5, characterized in that: The step of specifying a paired FPGA chip for the FPGA chip that has not completed programming further includes: If the number of FPGA chips that have not been burned is 1, any FPGA chip that has been burned is designated as a paired FPGA chip; If the number of FPGA chips that have not been burned is an even number greater than 1, the paired FPGA chips are specified in pairs; If the number of FPGA chips that have not completed burning is an odd number greater than 1, any FPGA chip that has completed burning is added, and the paired FPGA chips are designated in a pairing manner.