Method for determining scan chain in integrated circuit, integrated circuit, equipment and medium
By determining scan chains based on wiring and logic consistency, the method reduces chip area and power consumption in integrated circuits, effectively addressing the challenge of timing violations and resource consumption in scan chain reorganization.
Patent Information
- Application Number
- CN202411320211.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-20
- Publication Date
- 2024-12-27
AI Technical Summary
Existing methods for scan chain reorganization in integrated circuits lead to increased chip area consumption due to the need for additional buffers to maintain timing, especially in designs with tight winding resources or tight timing constraints.
A method for determining a scan chain by selecting target registers based on wiring and logic consistency information, allowing for the reuse of existing data paths and nodes, thereby reducing the need for additional buffers and minimizing timing violations.
This approach reduces chip area and power consumption while minimizing hold timing violations by reorganizing scan chains through multiplexing of existing data paths and nodes, thus addressing the issue of excessive local density and congestion.
Smart Images
Figure CN119203872A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of chip design, and in particular to a method for determining a scan chain in an integrated circuit, an integrated circuit, a device and a medium. Background Art
[0002] As the scale of integrated circuits increases, the testability design of integrated circuits becomes more and more important. Testability design can be achieved by adding scan chain logic outside the original data path. For integrated circuit designs with tight winding resources or tight timing caused by tight winding, scan chain reorganization is usually performed.
[0003] In the existing method, the registers are usually reorganized according to their physical locations, and registers that are close to each other are reorganized as much as possible. In order to meet the requirements of the hold time in the timing design, a buffer is added to the reorganized scan chain to maintain the timing.
[0004] However, the above method may require inserting more buffers in the scan chain, resulting in greater consumption of chip area. Summary of the invention
[0005] The purpose of the present application is to provide a method, integrated circuit, device and medium for determining a scan chain in an integrated circuit in order to reduce the area consumption of the chip while minimizing timing maintenance violations in order to address the deficiencies in the above-mentioned prior art.
[0006] To achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:
[0007] In a first aspect, an embodiment of the present application provides a method for determining a scan chain in an integrated circuit, comprising:
[0008] determining a data path in the chip that fans out from the first register;
[0009] Determine a target register from each second register according to the wiring consistency information between each second register in the chip and the data path and / or the logic consistency information between the first register and each node on the data path, wherein the wiring consistency information is used to characterize the impedance generated by the wiring on the data path on the path between the first register and the second register, and the logic consistency information is used to characterize whether the node on the data path is logically consistent with the output end of the first register;
[0010] A target scan chain from the first register to the target register is generated according to the data path fanned out by the first register.
[0011] Optionally, before determining the target register from each second register according to the wiring consistency information between each second register in the chip and the data path and / or the logic consistency information between the first register and each node on the data path, the method further includes:
[0012] According to the link multiplexing relationship between the path formed by each candidate register and the first register and the data path, each second register that meets the conditions is determined from each candidate register, wherein the candidate register is a register in the chip except the first register and the register located at the end of the data path.
[0013] Optionally, determining second registers that meet the condition from the candidate registers according to a link multiplexing relationship between a path formed by the candidate registers and the first register and the data path includes:
[0014] If a path formed by the candidate register and the first register overlaps with the data path, the candidate register is used as a second register.
[0015] Optionally, determining the target register from each second register according to the wiring consistency information between each second register in the chip and the data path and / or the logic consistency information between the first register and each node on the data path includes:
[0016] If no node exists on the data path, determining a target register from each second register according to routing consistency information between each second register and the data path;
[0017] If there is a node on the data path, the target node is determined based on the winding consistency information between each second register and the data path and the logical consistency information between the first register and each node on the data path, and the target register is determined from each second register based on the target node, wherein the output end of the target node is logically consistent with the output end of the first register, and the distance between the target node and the first register meets a preset condition.
[0018] Optionally, determining the target register from each second register according to the routing consistency information between each second register and the data path includes:
[0019] Determine a first winding distance of each second register according to a distance between a scan input port of each second register and an output end of the first register, wherein the first winding distance is positively correlated with impedance;
[0020] A target register is determined from the second registers according to the first winding distances of the second registers.
[0021] Optionally, determining the target register from each second register according to the first winding distance of each second register includes:
[0022] Determining the priority of each second register according to the first winding distance of each second register;
[0023] A target register is determined from among the second registers according to the priorities of the second registers.
[0024] Optionally, determining the target node according to the wiring consistency information between each second register and the data path and the logic consistency information between the first register and each node on the data path, and determining the target register from each second register according to the target node includes:
[0025] Determine a target node from each node according to the logic consistency information between each node on the data path and the first register and a second wiring distance between each node and an output end of the first register, wherein the second wiring distance is positively correlated with impedance;
[0026] The target register is determined from the second registers according to the distance between the scan input port of each second register and the target node.
[0027] Optionally, determining the target node from each node according to the logic consistency information between each node on the data path and the first register and the second winding distance between each node and the output end of the first register includes:
[0028] Determine candidate nodes that are logically consistent with the first register from among the nodes according to whether the digital signal of each node is logically consistent with the digital signal at the output end of the first register;
[0029] Determining the priority of each candidate node according to a second winding distance between each candidate node and the output end of the first register;
[0030] According to the priority of each candidate node, the target node is determined from the candidate nodes.
[0031] Optionally, determining the target register from each second register according to the distance between the scan input port of each second register and the output end of the target node includes:
[0032] Determining the priority of each second register according to the distance between the scan input port of each second register and the target node;
[0033] A target register is determined from the second registers according to the priorities of the second registers.
[0034] Optionally, generating a target scan chain from the first register to the target register according to the data path fanned out by the first register includes:
[0035] If no node exists on the data path, the output end of the first register is connected to the scan input port of the target register via the output end of the first register and the data path to generate the target scan chain.
[0036] Optionally, generating a target scan chain from the first register to the target register according to the data path fanned out by the first register includes:
[0037] If there is a node on the data path, the output end of the first register is connected to the scan input port of the target register via the output end of the first register and the target sub-path on the data path to generate the target scan chain, wherein the target sub-path starts from the output end of the first register and ends at the target node.
[0038] In a second aspect, an embodiment of the present application further provides an integrated circuit, comprising a plurality of registers;
[0039] The scan chains corresponding to the registers are generated based on the steps of the method for determining the scan chains in the integrated circuit described in the first aspect above.
[0040] In a third aspect, an embodiment of the present application further provides a device for determining a scan chain in an integrated circuit, comprising: a determination module and a generation module;
[0041] The determining module is used to determine a data path fanned out from the first register in the chip;
[0042] The determination module is used to determine the target register from each second register according to the wiring consistency information between each second register in the chip and the data path and / or the logic consistency information between the first register and each node on the data path, wherein the wiring consistency information is used to characterize the impedance generated by the wiring on the data path on the path between the first register and the second register, and the logic consistency information is used to characterize whether the node on the data path is logically consistent with the output end of the first register;
[0043] The generating module is used to generate a target scan chain from the first register to the target register according to the data path fanned out by the first register.
[0044] Optionally, the determination module is also used to determine second registers that meet the conditions from the candidate registers based on the link multiplexing relationship between the path formed by each candidate register and the first register and the data path, wherein the candidate registers are registers in the chip other than the first register and the register located at the end of the data path.
[0045] Optionally, the determining module is specifically configured to use the candidate register as a second register if a path formed by the candidate register and the first register overlaps with the data path.
[0046] Optionally, the determination module is specifically configured to determine the target register from each second register according to the routing consistency information between each second register and the data path if no node exists on the data path;
[0047] If there is a node on the data path, the target node is determined based on the winding consistency information between each second register and the data path and the logical consistency information between the first register and each node on the data path, and the target register is determined from each second register based on the target node, wherein the output end of the target node is logically consistent with the output end of the first register, and the distance between the target node and the first register meets a preset condition.
[0048] Optionally, the determining module is specifically configured to determine a first winding distance of each second register according to a distance between a scan input port of each second register and an output end of the first register, wherein the first winding distance is positively correlated with impedance;
[0049] A target register is determined from the second registers according to the first winding distances of the second registers.
[0050] Optionally, the determination module is specifically configured to determine the priority of each second register according to the first winding distance of each second register;
[0051] A target register is determined from the second registers according to the priorities of the second registers.
[0052] Optionally, the determination module is specifically configured to determine the target node from each node according to the logic consistency information between each node on the data path and the first register and a second winding distance between each node and an output end of the first register, wherein the second winding distance is positively correlated with the impedance;
[0053] The target register is determined from the second registers according to the distance between the scan input port of each second register and the target node.
[0054] Optionally, the determination module is specifically configured to determine candidate nodes having logical consistency with the first register from among the nodes according to whether the digital signal of each node is logically consistent with the digital signal of the output end of the first register;
[0055] Determining the priority of each candidate node according to a second winding distance between each candidate node and the output end of the first register;
[0056] According to the priority of each candidate node, the target node is determined from the candidate nodes.
[0057] Optionally, the determination module is specifically configured to determine the priority of each second register according to the distance between the scan input port of each second register and the target node;
[0058] A target register is determined from the second registers according to the priorities of the second registers.
[0059] Optionally, the generating module is specifically used to connect the output end of the first register to the scan input port of the target register via the output end of the first register and the data path to generate the target scan chain if no node exists on the data path.
[0060] Optionally, the generation module is specifically used to connect the output end of the first register to the scan input port of the target register via the output end of the first register and the target sub-path on the data path if there is a node on the data path, so as to generate the target scan chain, wherein the target sub-path starts from the output end of the first register and ends at the target node.
[0061] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising: a processor, a storage medium and a bus, wherein the storage medium stores machine-readable instructions executable by the processor. When the electronic device is running, the processor and the storage medium communicate through the bus, and the processor executes the machine-readable instructions to implement the method for determining a scan chain in an integrated circuit as provided in the first aspect.
[0062] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the method for determining a scan chain in an integrated circuit as provided in the first aspect is executed.
[0063] The beneficial effects of this application are:
[0064] The present application provides a method for determining a scan chain in an integrated circuit, an integrated circuit, a device and a medium, including: determining a data path fanned out from a first register in a chip; determining a target register from each second register according to the wiring consistency information between each second register in the chip and the data path and / or the logic consistency information between the first register and each node on the data path; generating a target scan chain from the first register to the target register according to the data path fanned out by the first register. The method determines the wiring consistency information between each second register and the data path and the logic consistency information between the node on the data path and the first register through the determined data path, so as to realize the scan chain reorganization based on the multiplexing of the data path wiring by each second register and the multiplexing of the node on the data path by each second register. Since it is the multiplexing of the existing data path and the existing nodes on the data path, the consumption of design resources can be reduced, thereby reducing the area consumption and power consumption of the chip while reducing the hold timing violation caused by the scan chain. In addition, the multiplexing of the wiring of the existing data path can reduce the number of newly added wirings, solving the problem of excessive local density and severe congestion of the chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0065] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0066] Figure 1 A schematic diagram of the structure of an integrated circuit provided in an embodiment of the present application;
[0067] Figure 2 A schematic diagram of the structure of another integrated circuit provided in an embodiment of the present application;
[0068] Figure 3 A schematic flow chart of a method for determining a scan chain in an integrated circuit provided in an embodiment of the present application;
[0069] Figure 4 A schematic diagram of the structure of another integrated circuit provided in an embodiment of the present application;
[0070] Figure 5 A schematic flow chart of another method for determining a scan chain in an integrated circuit provided in an embodiment of the present application;
[0071] Figure 6 A schematic diagram of the structure of another integrated circuit provided in an embodiment of the present application;
[0072] Figure 7A schematic flow chart of another method for determining a scan chain in an integrated circuit provided in an embodiment of the present application;
[0073] Figure 8 A schematic flow chart of another method for determining a scan chain in an integrated circuit provided in an embodiment of the present application;
[0074] Fig. 9 A schematic diagram of the structure of another integrated circuit provided in an embodiment of the present application;
[0075] Fig.10 A schematic flow chart of another method for determining a scan chain in an integrated circuit provided in an embodiment of the present application;
[0076] Fig.11 A schematic flow chart of another method for determining a scan chain in an integrated circuit provided in an embodiment of the present application;
[0077] Fig.12 A schematic diagram of the structure of another integrated circuit provided in an embodiment of the present application;
[0078] Fig.13 A schematic flow chart of another method for determining a scan chain in an integrated circuit provided in an embodiment of the present application;
[0079] Fig.14 A schematic diagram of a device for determining a scan chain in an integrated circuit provided by an embodiment of the present application;
[0080] Fig.15 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0081] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of explanation and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn in real proportion. The flowchart used in this application shows the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowchart can be implemented out of sequence, and the steps without logical context can be reversed in order or implemented simultaneously. In addition, those skilled in the art can add one or more other operations to the flowchart under the guidance of the content of the present application, or remove one or more operations from the flowchart.
[0082] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.
[0083] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features.
[0084] First, the relevant background of this plan is explained:
[0085] Generally speaking, in integrated circuit design, data is calculated and transmitted through registers. Figure 1 A schematic diagram of the structure of an integrated circuit provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the path formed by the Q output of register FF0 and the D data port of register FF1 is a simple data path between registers. Generally, the data path formed by the Q output of register FF0 to the D data port of other registers can be called the data path of register FF0 fan-out, and the data path formed by the Q output of other registers to the D data port of register FF0 can be called the data path of register FF0 fan-in. There can be multiple data paths corresponding to each register.
[0086] As the scale of integrated circuits becomes larger and larger, testability design becomes more and more important. The mainstream testability design method is to add scan chain logic in addition to the original data path, such as Figure 1 As shown, the path from the added Q output terminal of register FF0 to the SI scan input port of register FF2 can be called a scan chain.
[0087] After adding the scan chain, a certain amount of winding resources will be occupied. Therefore, for integrated circuit chip designs with tight winding resources or tight timing due to tight winding resources, the scan chain is generally reorganized.
[0088] At present, the scan chain reorganization technology is generally based on the physical location of the registers to reorganize, and the registers that are close to each other are reorganized as much as possible. After such scan chain reorganization, because there is almost no logic between the scan chains between registers, the delay between the two levels of registers on the scan chain path is generally short, which is easy to cause the violation of the hold timing. Or because the clock of the two levels of registers is unbalanced, it is also easy to cause the violation of the hold timing. In order to meet the hold time requirements in the timing design, it is achieved by adding buffers on the relevant paths in the physical design. Figure 2 A schematic diagram of the structure of another integrated circuit provided in an embodiment of the present application, compared to Figure 1 The structure of the integrated circuit shown in Figure 2 Several BUF (buffer unit) units are added.
[0089] Timing maintenance is usually repaired by inserting buffers to increase delays. For some timing paths with large timing violations, many buffers need to be inserted, which consumes a lot of chip area. In particular, the local utilization of the chip is often too high to insert buffers to repair the timing.
[0090] In view of the existence of the above-mentioned problems, the present application provides a method for determining a scan chain in an integrated circuit. Based on the calculation of the routing consistency of the path between registers and the data path and / or the calculation of the logical consistency of the nodes between registers, the end register for constituting the scan chain is selected from candidate registers, thereby realizing the reuse of the data path and the nodes on the data path, while minimizing the hold timing violations caused by the scan chain, saving the chip area consumption and power consumption of the integrated circuit.
[0091] Figure 3 A flow chart of a method for determining a scan chain in an integrated circuit provided in an embodiment of the present application; the execution subject of the method may be a computer device, such as Figure 3 As shown, the method may include:
[0092] S101 . Determine a data path that fans out from a first register in a chip.
[0093] The first register may be any register on the chip, and the first register may correspond to a fan-in data path and a fan-out data path. According to the above description, the data path sent from the first register is used as the data path fanned out of the first register, and the data path fed into the first register may be used as the data path fanned in of the first register. The first register may include multiple fan-out data paths and fan-in data paths.
[0094] This application takes one of the fan-out data paths of the first register as an example to illustrate a method for determining a scan chain around the data path.
[0095] S102 . Determine a target register from each second register according to the routing consistency information between each second register and the data path in the chip and / or the logic consistency information between the first register and each node on the data path.
[0096] The winding consistency information is used to characterize the impedance generated by the winding on the data path on the path between the first register and the second register, and the logic consistency information is used to characterize whether the node on the data path is logically consistent with the output end of the first register.
[0097] The second register may be other registers on the chip except the first register and the registers forming the data path with the first register, or may be a register that meets the conditions and is selected from other registers.
[0098] Optionally, the routing consistency information of the data path fanned out by each second register and the first register can be determined based on the routing multiplexing of each second register and the first register; the logical consistency information of the first register and each node on the data path can be determined based on the digital signal at the output end of each node on the data path and the digital signal at the output end of the first register.
[0099] In one achievable manner, the target register may be determined from each second register only based on the routing consistency information between each second register and the data path.
[0100] In another achievable manner, the target register may be determined from the second registers according to the routing consistency information between the second registers and the data path and the logic consistency information between the first register and each node on the data path.
[0101] It is worth noting that the greater the impedance generated by the routing on the data path on the path between the first register and the second register, the better the routing consistency between the second register and the data path, and the greater the delay on the path between the first register and the second register, the more conducive it is to reducing hold timing violations.
[0102] In addition, the node on the data path may be an output node of a logic unit inserted into the data path, and the logic unit includes but is not limited to a buffer unit, an inverter, etc. The logical consistency between the node and the first register may be determined by a digital signal of the node and a digital signal output from an output end of the first register.
[0103] S103 . Generate a target scan chain from the first register to the target register according to the data path fanned out by the first register.
[0104] Based on the determined target register, a target scan chain may be generated from the first register to the target register via the first register and a data path fanned out of the first register.
[0105] Optionally, when there are nodes on the data path, a target scan chain may be generated from the first register to the target register via the first register, the data path fanned out from the first register, and the nodes on the data path.
[0106] In summary, the method for determining the scan chain in the integrated circuit provided by the present embodiment includes: determining the data path fanned out from the first register in the chip; determining the target register from each second register according to the wiring consistency information between each second register and the data path in the chip and / or the logic consistency information between the first register and each node on the data path; generating the target scan chain from the first register to the target register according to the data path fanned out by the first register. The method determines the wiring consistency information between each second register and the data path and the logic consistency information between the node on the data path and the first register through the determined data path, so as to realize the scan chain reorganization based on the multiplexing of the data path wiring by each second register and the multiplexing of the node on the data path by each second register. Since it is the multiplexing of the existing data path and the existing nodes on the data path, the consumption of design resources can be reduced, thereby reducing the area consumption and power consumption of the chip while reducing the hold timing violation caused by the scan chain. And the multiplexing of the wiring of the existing data path can reduce the number of new wirings, and solve the problem of excessive local density and serious congestion of the chip.
[0107] Optionally, in step S102, before determining the target register from the second registers based on the routing consistency information between the second registers in the chip and the data path and / or the logical consistency information between the first register and each node on the data path, it also includes: determining the second registers that meet the conditions from the candidate registers based on the link multiplexing relationship between the path formed by the candidate registers and the first register and the data path, wherein the candidate registers are registers in the chip other than the first register and the register at the end of the data path.
[0108] In one achievable manner, the candidate registers may be all other registers in the chip except the first register and the register located at the end of the above-mentioned data path.
[0109] In another achievable manner, registers meeting the conditions may be screened out from all other registers except the first register and the register at the end of the data path as candidate registers to reduce the amount of subsequent calculations.
[0110] Optionally, the second registers meeting the conditions may be determined from the candidate registers according to the link multiplexing relationship between the path formed by the candidate register and the first register and the data path, wherein the candidate register for which the path formed by the candidate register and the first register and the data path have detour multiplexing may be determined as a second register.
[0111] Optionally, in the above steps, determining the second registers that meet the conditions from the candidate registers based on the link multiplexing relationship between the path formed by the candidate registers and the first register and the data path may include: if the path formed by the candidate register and the first register and the data path overlap, then using the candidate register as a second register.
[0112] In some embodiments, when the path formed by the candidate register and the first register overlaps with the fan-out data path of the first register, the candidate register may be used as a second register. The overlap here may include but is not limited to partial overlap.
[0113] Figure 4 A schematic diagram of the structure of another integrated circuit provided in an embodiment of the present application is shown in FIG. Figure 4 As shown, the Q output terminal of register FF0 to the D data port of register FF2 constitutes a fan-out data path of FF0, and the path formed by the Q output terminal of FF0 to the SI scan input port of register FF3 overlaps with the data path of FF0, and the path formed by the Q output terminal of FF0 to the SI scan input port of FF1 also overlaps with the data path of FF0. Therefore, FF1 and FF3 can both be used as a second register.
[0114] Figure 5 A flow chart of another method for determining a scan chain in an integrated circuit provided in an embodiment of the present application; optionally, in step S102, determining a target register from each second register according to the wiring consistency information between each second register and a data path in the chip and / or the logic consistency information between the first register and each node on the data path may include:
[0115] S201: If no node exists on the data path, determine a target register from the second registers according to routing consistency information between the second registers and the data path.
[0116] Figure 6 This is a schematic diagram of the structure of another integrated circuit provided in an embodiment of the present application. Figure 6As shown, in one implementable manner, there is no node on the data path. At this time, the path formed by each second register and the first register and the data path may only have routing multiplexing. Then, the target register can be determined from each second register based only on the routing consistency information of each second register and the data path.
[0117] S202. If there are nodes on the data path, determine the target node based on the routing consistency information between each second register and the data path and the logic consistency information between the first register and each node on the data path, and determine the target register from each second register based on the target node, wherein the output end of the target node is logically consistent with the output end of the first register, and the distance between the target node and the first register meets a preset condition.
[0118] In another possible implementation, reference Figure 4 , there are nodes on the data path. At this time, the path formed by each second register and the first register may not only reuse the data path routing, but also reuse the nodes on the data path. Then, the routing consistency information and the node logic consistency information can be combined to first determine the target node from each node on the data path, and then determine the target register from each second register based on the positional relationship between the target node and each second register.
[0119] The determined target node is a node that is logically consistent with the first register, and the distance between the target node and the first register meets the preset condition. In order to increase the delay on the path formed by the second register and the first register, as many multiplexing nodes as possible are required to increase the path impedance and increase the path delay.
[0120] Figure 7 A flowchart of another method for determining a scan chain in an integrated circuit provided in an embodiment of the present application; optionally, in step S201, determining a target register from each second register according to the routing consistency information between each second register and a data path may include:
[0121] S301 . Determine a first winding distance of each second register according to the distance between the scan input port of each second register and the output end of the first register, wherein the first winding distance is positively correlated with the impedance.
[0122] Optionally, the distance between the SI scan input port of each second register and the Q output terminal of the first register may be calculated respectively to obtain the first winding distance of each second register.
[0123] S302 , determining a target register from each second register according to the first winding distance of each second register.
[0124] Optionally, the target register can be determined from the second registers according to the first routing distance of each second register. The larger the first routing distance, the greater the impedance on the path formed by the second register and the first register, and the greater the delay on the path. The hold timing violation caused by the scan chain can be reduced.
[0125] Figure 8 A flow chart of another method for determining a scan chain in an integrated circuit provided in an embodiment of the present application; Optionally, in step S302, determining a target register from each second register according to the first wiring distance of each second register may include:
[0126] S401. Determine the priority of each second register according to the first winding distance of each second register.
[0127] The second registers may be prioritized according to the first winding distances of the second registers. Optionally, the second registers may be prioritized in descending order of distance.
[0128] S402: Determine a target register from the second registers according to the priorities of the second registers.
[0129] As mentioned above, the larger the first wiring distance of the second register, the greater the impedance of the path formed by the second register and the first register, the greater the delay, and the more conducive to reducing the violation of the hold timing. Therefore, according to the priority of each second register, the second register with the largest first wiring distance can be preferably determined as the target register.
[0130] However, it is worth noting that, considering that the length of the scan chain finally generated cannot be too long, in order to reduce the occupancy of routing resources, the second register with the longest data path routing multiplexing and closest to the first register can be selected as the target register from among the multiple second registers whose first routing distance meets the preset distance.
[0131] Fig. 9 A schematic diagram of the structure of another integrated circuit provided in an embodiment of the present application is shown in FIG. Fig. 9As shown, registers FF3, FF1 and FF4 are all second registers, and the first winding distance of FF4> the first winding distance of FF3> the first winding distance of FF1. Since FF1 has less wiring reuse for the data path, the delay generated is small, and it is necessary to increase the node to increase the delay. However, both FF3 and FF4 reuse more data paths, which can generate enough delay to reduce the hold timing violation. However, if only according to the winding distance, FF4 should be selected as the target register. However, since the data paths reused by FF3 and FF4 are the same, FF3 is closer to the first register, and the first winding distance of FF3 is smaller than the first winding distance of FF4. In the chip design with tight winding resources, selecting FF3 as the target register can not only reduce the hold timing violation, but also alleviate the problem of tight winding resources and save the area consumption of the chip. Therefore, FF3 can be selected as the target register. Of course, in the design where the winding resources are not tight, FF4 can also be selected as the preferred choice.
[0132] Fig.10 A flow chart of another method for determining a scan chain in an integrated circuit provided in an embodiment of the present application; optionally, in step S202, determining a target node according to the wiring consistency information between each second register and the data path and the logic consistency information between the first register and each node on the data path, and determining the target register from each second register according to the target node may include:
[0133] S501. Determine a target node from each node according to logic consistency information between each node on the data path and the first register and a second wiring distance between an output end of each node and an output end of the first register, wherein the second wiring distance is positively correlated with impedance.
[0134] Optionally, it is possible to first determine whether the logic of each node is consistent with the first register, determine the nodes that are logically consistent with the first register, and then combine the output end of the selected node with logical consistency with the second winding distance of the Q output end of the first register to determine the target node from each node.
[0135] S502 : Determine a target register from the second registers according to the distance between the scan input port of each second register and the target node.
[0136] Then, according to the distance between the SI scan input port of each second register and the target node, the target register is determined from each second register.
[0137] That is, in this method, it is necessary to first select a target node from multiple nodes on the data path based on logic consistency and routing distance; and then select a target register from the second registers based on the distance between the second register and the target node.
[0138] Fig.11 A flow chart of another method for determining a scan chain in an integrated circuit provided in an embodiment of the present application; optionally, in step S501, determining a target node from each node according to the logic consistency information between each node on the data path and the first register and the second winding distance between each node and the output end of the first register may include:
[0139] S601 . Determine candidate nodes that are logically consistent with the first register from among the nodes according to whether the digital signals of the nodes are logically consistent with the digital signal of the output terminal of the first register.
[0140] Logical consistency refers to the digital signal (such as 0 or 1) at the output of a register. After passing through some logic units, if the digital signal at the output of a node is logically consistent with the digital signal at the output of the register, then this node is a node that is logically consistent with the register.
[0141] For example, the node at the register output after passing through two inverters or a buffer can be considered a logically consistent node.
[0142] Fig.12 This is a schematic diagram of the structure of another integrated circuit provided in an embodiment of the present application. Fig.12 As shown, there are three nodes on the data path, namely, node 1, node 2 and node 3. After judging the logical consistency, it can be known that node 1, node 2 and node 3 are all logically consistent with the first register. Therefore, node 1, node 2 and node 3 can be used as candidate nodes.
[0143] S602: Determine the priority of each candidate node according to a second winding distance between each candidate node and the output terminal of the first register.
[0144] Then, the distance from each candidate node to the Q output terminal of the first register can be calculated to obtain the second winding distance of each candidate node, and the candidate nodes are prioritized in descending order according to the distance.
[0145] S603: Determine a target node from among the candidate nodes according to the priority of each candidate node.
[0146] Thus, the target node is determined from each candidate node according to the priority of each candidate node. In this embodiment, since there may be multiple candidate nodes that meet the logic consistency with the first register, the target registers that can be finally determined by different candidate nodes may be different. In order to improve the path delay as much as possible, the routing distance between each candidate node and the first register can be used as a constraint condition to select a better target node from each candidate node.
[0147] It can be seen that according to the sorting of the second winding distance, the priority of node 3 is higher than that of node 2 which is higher than that of node 1.
[0148] Fig.13 A flow chart of another method for determining a scan chain in an integrated circuit provided in an embodiment of the present application; Optionally, in step S502, determining a target register from each second register according to a distance between a scan input port of each second register and a target node may include:
[0149] S701 . Determine the priority of each second register according to the distance between the scan input port of each second register and the target node.
[0150] Optionally, based on the determined target node, the distance from the SI scan input port of each second register to the target node can be calculated to determine the priority of each second register. Similarly, the priority can be sorted from large to small according to the distance.
[0151] S702: Determine a target register from the second registers according to the priorities of the second registers.
[0152] In one achievable manner, the register closest to the target node may be determined from the second registers as the target register. In this way, while taking data path routing and node multiplexing into consideration, the length of the newly added routing is shortened as much as possible.
[0153] Of course, if there are sufficient routing resources, a second register that is slightly farther away from the target node can also be selected as the target register. In this way, the scan chain delay formed by the determined target register is larger, but the length of the newly added routing is increased. The requirements for path delay and the constraints on routing can be combined to select a more suitable target register from the second registers.
[0154] Based on the above solution, when the selected target nodes are different, the determined target registers are also different.
[0155] In one feasible manner, among the candidate nodes that meet the logical consistency with the first register, the candidate node with the farthest second winding distance from the first register can be selected as the target node, and then the second register closest to the target node can be selected from the second registers as the target register.
[0156] For example, Fig.12 As shown, when the target node is node 3, since register FF3 is closest to node 1, FF3 can be determined as the target register. When the target node is node 2, since register FF4 is closest to node 2, FF4 can be determined as the target register.
[0157] Of course, the integrated circuits shown in the above embodiments of the present application are all described by taking a limited number of registers as an example. In actual applications, there may be multiple registers, and the target register needs to be selected from all qualified second registers.
[0158] Optionally, in step S103, a target scan chain from the first register to the target register is generated according to the data path fanned out by the first register, including: if there is no node on the data path, the output end of the first register is connected to the scan input port of the target register via the output end of the first register and the data path to generate a target scan chain.
[0159] In one achievable manner, reference Fig. 9 , when there is no node on the data path and the determined target register is FF3, a scan chain consisting of FF0 and FF3 can be generated by starting from the Q output end of the first register FF0 through the data path and connecting to the S1 scan input port of FF3. This scan chain reuses part of the routing on the data path.
[0160] Optionally, in step S103, a target scan chain from the first register to the target register is generated according to the data path fanned out by the first register, including: if there is a node on the data path, the output end of the first register is connected to the scan input port of the target register via the output end of the first register and the target sub-path on the data path to generate a target scan chain, wherein the target sub-path starts from the output end of the first register and ends at the target node.
[0161] In another possible implementation, reference Fig.12 , when there is a node on the data path, the determined target node is node 3, and the determined target register is FF3, then starting from the Q output end of the first register FF0, passing through nodes 1, 2, and 3 on the data path, and connecting from node 3 to the S1 scan input port of FF3, a scan chain consisting of FF0 and FF3 is generated. This scan chain reuses part of the routing on the data path, and reuses nodes 1, 2, and 3 on the data path. Among them, the target subpath can refer to the path from the Q end of FF0 to the location of node 3.
[0162] In summary, the method for determining the scan chain in the integrated circuit provided by the present embodiment includes: determining the data path fanned out from the first register in the chip; determining the target register from each second register according to the wiring consistency information between each second register and the data path in the chip and / or the logic consistency information between the first register and each node on the data path; generating the target scan chain from the first register to the target register according to the data path fanned out by the first register. The method determines the wiring consistency information between each second register and the data path and the logic consistency information between the node on the data path and the first register through the determined data path, so as to realize the scan chain reorganization based on the multiplexing of the data path wiring by each second register and the multiplexing of the node on the data path by each second register. Since it is the multiplexing of the existing data path and the existing nodes on the data path, the consumption of design resources can be reduced, thereby reducing the area consumption and power consumption of the chip while reducing the hold timing violation caused by the scan chain. And the multiplexing of the wiring of the existing data path can reduce the number of new wirings, and solve the problem of excessive local density and serious congestion of the chip.
[0163] Optionally, the present application further provides an integrated circuit, comprising a plurality of registers; the scan chains corresponding to the respective registers are generated based on the steps of the method for determining the scan chains in the integrated circuit in the above embodiment. When any register is used as the above first register, at least one scan chain corresponding to the register can be determined according to the above method.
[0164] The following describes the apparatus, device, storage medium, etc. used to execute the method for determining the scan chain in the integrated circuit provided in the present application. The specific implementation process and technical effects are described above and will not be repeated below.
[0165] Fig.14 A schematic diagram of a device for determining a scan chain in an integrated circuit provided in an embodiment of the present application, wherein the functions implemented by the device for determining a scan chain in the integrated circuit correspond to the steps performed by the above method. The device can be understood as the above server, or a processor of the server, or can be understood as a component independent of the above server or processor that implements the functions of the present application under the control of the server, such as Fig.14 As shown, the device may include: a determination module 140, a generation module 141;
[0166] A determination module 140, configured to determine a data path in the chip that fans out from the first register;
[0167] A determination module 140 is used to determine a target register from each second register according to the wiring consistency information between each second register and the data path in the chip and / or the logic consistency information between the first register and each node on the data path, wherein the wiring consistency information is used to characterize the impedance generated by the wiring on the data path on the path between the first register and the second register, and the logic consistency information is used to characterize whether the node on the data path is logically consistent with the output end of the first register;
[0168] The generating module 141 is used to generate a target scan chain from the first register to the target register according to the data path fanned out by the first register.
[0169] Optionally, the determination module 140 is also used to determine the second registers that meet the conditions from the candidate registers according to the link multiplexing relationship between the path formed by each candidate register and the first register and the data path, wherein the candidate registers are registers in the chip other than the first register and the register at the end of the data path.
[0170] Optionally, the determination module 140 is specifically configured to use the candidate register as a second register if a path formed by the candidate register and the first register overlaps with the data path.
[0171] Optionally, the determination module 140 is specifically configured to determine the target register from each second register according to the routing consistency information between each second register and the data path if no node exists on the data path;
[0172] If there is a node on the data path, the target node is determined based on the routing consistency information between each second register and the data path and the logic consistency information between the first register and each node on the data path, and the target register is determined from each second register based on the target node, wherein the output end of the target node is logically consistent with the output end of the first register, and the distance between the target node and the first register meets a preset condition.
[0173] Optionally, the determination module 140 is specifically configured to determine a first winding distance of each second register according to a distance between a scan input port of each second register and an output end of the first register, wherein the first winding distance is positively correlated with the impedance;
[0174] A target register is determined from the second registers according to the first winding distances of the second registers.
[0175] Optionally, the determination module 140 is specifically configured to determine the priority of each second register according to the first winding distance of each second register;
[0176] A target register is determined from the second registers according to the priorities of the second registers.
[0177] Optionally, the determination module 140 is specifically configured to determine the target node from each node according to the logic consistency information between each node on the data path and the first register and the second winding distance between each node and the output end of the first register, wherein the second winding distance is positively correlated with the impedance;
[0178] The target register is determined from the second registers according to the distance between the scan input port of each second register and the target node.
[0179] Optionally, the determination module 140 is specifically configured to determine candidate nodes that are logically consistent with the first register from among the nodes according to whether the digital signals of the nodes are logically consistent with the digital signal of the output end of the first register;
[0180] Determining the priority of each candidate node according to a second winding distance between each candidate node and the output end of the first register;
[0181] According to the priority of each candidate node, the target node is determined from the candidate nodes.
[0182] Optionally, the determination module 140 is specifically configured to determine the priority of each second register according to the distance between the scan input port of each second register and the target node;
[0183] A target register is determined from the second registers according to the priorities of the second registers.
[0184] Optionally, the generating module 141 is specifically configured to connect the output end of the first register to the scan input port of the target register via the output end of the first register and the data path to generate a target scan chain if no node exists on the data path.
[0185] Optionally, the generation module 141 is specifically used to connect the output end of the first register to the scan input port of the target register via the output end of the first register and the target sub-path on the data path if there is a node on the data path, so as to generate a target scan chain, wherein the target sub-path starts from the output end of the first register and ends at the target node.
[0186] The above-mentioned device is used to execute the method provided by the aforementioned embodiment, and its implementation principle and technical effect are similar, which will not be repeated here.
[0187] The above modules may be one or more integrated circuits configured to implement the above methods, such as one or more application specific integrated circuits (ASIC), or one or more digital singnal processors (DSP), or one or more field programmable gate arrays (FPGA). For another example, when a module is implemented in the form of a processing element scheduling program code, the processing element may be a general-purpose processor, such as a central processing unit (CPU) or other processor that can call program code. For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).
[0188] The above modules can be connected or communicated with each other via a wired connection or a wireless connection. The wired connection may include a metal cable, an optical cable, a hybrid cable, etc., or any combination thereof. The wireless connection may include a connection in the form of a LAN, a WAN, Bluetooth, a ZigBee, or NFC, or any combination thereof. Two or more modules may be combined into a single module, and any one module may be divided into two or more units. Those skilled in the art will clearly understand that for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the method embodiment, and will not be repeated in this application.
[0189] Fig.15 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application, which may be a computing device with data processing capabilities.
[0190] The device may include: a processor 801 and a storage medium 802 .
[0191] The storage medium 802 is used to store programs, and the processor 801 calls the programs stored in the storage medium 802 to execute the above method embodiment. The specific implementation method and technical effect are similar and will not be repeated here.
[0192] Among them, the storage medium 802 stores program code, and when the program code is executed by the processor 801, the processor 801 executes various steps in the method for determining the scan chain in an integrated circuit according to various exemplary embodiments of the present application described in the above "Exemplary Method" section of this specification.
[0193] Processor 801 can be a general-purpose processor, such as a central processing unit (CPU), a digital signal processor (DigitalSignal Processor, DSP), an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, and can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiments of the present application. A general-purpose processor can be a microprocessor or any conventional processor, etc. The steps of the method disclosed in conjunction with the embodiments of the present application can be directly embodied as a hardware processor to be executed, or a combination of hardware and software modules in the processor can be executed.
[0194] Storage medium 802, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer executable programs and modules. Storage medium may include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type storage medium, random access storage medium (Random Access Memory, RAM), static random access storage medium (Static Random Access Memory, SRAM), programmable read-only storage medium (Programmable Read Only Memory, PROM), read-only storage medium (Read Only Memory, ROM), electrically erasable programmable read-only storage medium (Electrically Erasable Programmable Read-Only Memory, EEPROM), magnetic storage medium, disk, optical disk, etc. Storage medium is any other medium that can be used to carry or store a desired program code in the form of an instruction or data structure and can be accessed by a computer, but is not limited thereto. The storage medium 802 in the embodiment of the present application can also be a circuit or any other device that can realize a storage function, for storing program instructions and / or data.
[0195] Optionally, the present application also provides a program product, such as a computer-readable storage medium, including a program, which is used to execute the above method embodiment when executed by a processor.
[0196] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.
[0197] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0198] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional units.
[0199] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor (English: processor) to perform some steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only storage medium (English: Read-Only Memory, referred to as: ROM), random access storage medium (English: Random Access Memory, referred to as: RAM), disk or optical disk and other media that can store program code.
Claims
1. A method for determining a scan chain in an integrated circuit, characterized in that: include: determining a data path in the chip that fans out from the first register; Determine a target register from each second register according to the wiring consistency information between each second register in the chip and the data path and / or the logic consistency information between the first register and each node on the data path, wherein the wiring consistency information is used to characterize the impedance generated by the wiring on the data path on the path between the first register and the second register, and the logic consistency information is used to characterize whether the node on the data path is logically consistent with the output end of the first register; A target scan chain from the first register to the target register is generated according to the data path fanned out by the first register.
2. The method for determining a scan chain in an integrated circuit according to claim 1, characterized in that: Before determining the target register from each second register according to the routing consistency information between each second register in the chip and the data path and / or the logic consistency information between the first register and each node on the data path, the method further includes: According to the link multiplexing relationship between the path formed by each candidate register and the first register and the data path, each second register that meets the conditions is determined from each candidate register, wherein the candidate register is a register in the chip except the first register and the register located at the end of the data path.
3. The method for determining a scan chain in an integrated circuit according to claim 2, characterized in that: The determining, from the candidate registers, second registers that meet the conditions according to the link multiplexing relationship between the path formed by the candidate registers and the first register and the data path comprises: If a path formed by the candidate register and the first register overlaps with the data path, the candidate register is used as a second register.
4. The method for determining a scan chain in an integrated circuit according to claim 1, characterized in that: Determining the target register from each second register according to the wiring consistency information between each second register in the chip and the data path and / or the logic consistency information between the first register and each node on the data path includes: If no node exists on the data path, determining a target register from each second register according to routing consistency information between each second register and the data path; If there is a node on the data path, the target node is determined based on the winding consistency information between each second register and the data path and the logical consistency information between the first register and each node on the data path, and the target register is determined from each second register based on the target node, wherein the output end of the target node is logically consistent with the output end of the first register, and the distance between the target node and the first register meets a preset condition.
5. The method for determining a scan chain in an integrated circuit according to claim 4, characterized in that: The determining the target register from each second register according to the routing consistency information between each second register and the data path includes: Determine a first winding distance of each second register according to a distance between a scan input port of each second register and an output end of the first register, wherein the first winding distance is positively correlated with impedance; A target register is determined from the second registers according to the first winding distances of the second registers.
6. The method for determining a scan chain in an integrated circuit according to claim 5, characterized in that: Determining the target register from each second register according to the first winding distance of each second register includes: Determining the priority of each second register according to the first winding distance of each second register; A target register is determined from among the second registers according to the priorities of the second registers.
7. The method for determining a scan chain in an integrated circuit according to claim 4, characterized in that: The determining of the target node according to the wiring consistency information between each second register and the data path and the logic consistency information between the first register and each node on the data path, and determining the target register from each second register according to the target node, comprises: Determine a target node from each node according to the logic consistency information between each node on the data path and the first register and a second winding distance between each node and an output end of the first register, wherein the second winding distance is positively correlated with impedance; The target register is determined from the second registers according to the distance between the scan input port of each second register and the target node.
8. The method for determining a scan chain in an integrated circuit according to claim 7, characterized in that: The determining the target node from each node according to the logic consistency information between each node on the data path and the first register and the second winding distance between each node and the output end of the first register comprises: Determine candidate nodes that are logically consistent with the first register from among the nodes according to whether the digital signal of each node is logically consistent with the digital signal at the output end of the first register; Determining the priority of each candidate node according to a second winding distance between each candidate node and the output end of the first register; According to the priority of each candidate node, the target node is determined from the candidate nodes.
9. The method for determining a scan chain in an integrated circuit according to claim 7, characterized in that: Determining the target register from each second register according to the distance between the scan input port of each second register and the output end of the target node includes: Determining the priority of each second register according to the distance between the scan input port of each second register and the target node; A target register is determined from among the second registers according to the priorities of the second registers.
10. The method for determining a scan chain in an integrated circuit according to claim 4, characterized in that: The step of generating a target scan chain from the first register to the target register according to the data path fanned out by the first register includes: If no node exists on the data path, the output end of the first register is connected to the scan input port of the target register via the output end of the first register and the data path to generate the target scan chain.
11. The method for determining a scan chain in an integrated circuit according to claim 4, characterized in that: Generating a target scan chain from the first register to the target register according to the data path fanned out by the first register, comprising: If there is a node on the data path, the output end of the first register is connected to the scan input port of the target register via the output end of the first register and the target sub-path on the data path to generate the target scan chain, wherein the target sub-path starts from the output end of the first register and ends at the target node.
12. An integrated circuit, characterized in that: Includes multiple registers; The scan chains corresponding to the registers are generated based on the steps of the method for determining the scan chains in an integrated circuit according to any one of claims 1 to 11.
13. An electronic device, characterized in that: include: A processor, a storage medium and a bus, wherein the storage medium stores program instructions executable by the processor, and when the electronic device is running, the processor communicates with the storage medium via the bus, and the processor executes the program instructions to implement the method for determining a scan chain in an integrated circuit as described in any one of claims 1 to 11.
14. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by a processor, the method for determining a scan chain in an integrated circuit according to any one of claims 1 to 11 is implemented.