Semiconductor device and manufacturing method thereof
By designing the first and second openings on the substrate surface of the semiconductor device, and consuming the reaction gas using the low longitudinal etching speed of the second opening, the problem of notch effect during the etching process is solved, and the yield and reliability of the device are improved .
Patent Information
- Application Number
- CN202411296977.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-14
- Publication Date
- 2024-12-27
AI Technical Summary
In the process of etching semiconductor materials such as silicon, the gap effect is difficult to avoid, resulting in insufficient yield and failure of the device, and the prior art is difficult to effectively solve this problem.
Design a semiconductor device that forms a first opening and a second opening on the substrate surface, the area of the second opening is smaller than the first opening, and the longitudinal etching speed of the second opening is lower than the first opening, and consumes through the second opening React gas to avoid lateral etching and create gaps.
It effectively avoids the gap effect and improves the yield and reliability of semiconductor devices.
Smart Images
Figure CN119208127A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art
[0002] In the process of etching semiconductor materials such as silicon, for structures with a dielectric layer as a stop layer, such as a Silicon On Insulator (SOI) structure or a through hole with an electrostatic film at the bottom, after the etching is completed, a notch will appear at the bottom of the etched structure in contact with the dielectric layer (for example, the buried oxide layer or electrostatic film of SOI). The formation of the notch is called the "notching" effect.
[0003] Figure 1 is a cross-sectional schematic diagram of the notch structure. Figure 1 As shown, the substrate material 11 is etched using the photoresist 10 as a mask to form a hole 14. At the location where the hole 14 contacts the dielectric layer 12 at the bottom of the substrate material 11, the reaction gas used for etching diffuses laterally to form a gap 13. The appearance of the gap 13 may lead to insufficient yield or even failure of some devices.
[0004] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention
[0005] The inventors of the present application have found that it is difficult for the existing technology to deal with the notch effect. For example: when etching SOI, the buried oxide layer is used as the stop layer, so the notch effect is almost unavoidable; in the process of etching through holes in the wafer, a dielectric layer or an electrostatic film is provided on the back of the wafer, so it is also difficult to avoid the notch effect; for certain types of wafers, the notch effect can be avoided by first etching a blind hole and then thinning from the back, but this solution is relatively limited. Therefore, how to effectively alleviate the notch effect is a problem that needs to be solved urgently.
[0006] In order to solve the above-mentioned problems or at least similar problems, an embodiment of the present application provides a semiconductor device and a method for manufacturing the same, wherein the semiconductor device has a first opening and a second opening, wherein the second opening is arranged near the first opening, and the area of the second opening is smaller than the area of the first opening. Since the longitudinal etching speed of the second opening is lower than the longitudinal etching speed of the first opening, the etching reaction gas is consumed by the material in the second opening, and the etching reaction gas can be prevented from laterally etching the first opening to form a notch, thereby improving the yield and reliability of the semiconductor device.
[0007] According to one aspect of an embodiment of the present application, a semiconductor device is provided, the semiconductor device comprising:
[0008] substrate;
[0009] a first material layer formed on the back side of the substrate;
[0010] a first opening formed on a surface of the substrate and penetrating the surface and back surface of the substrate, wherein the first material layer is exposed from the first opening; and
[0011] The second opening is formed on the surface of the substrate and has a first distance from the first opening. The area of the second opening is smaller than that of the first opening.
[0012] In some embodiments, the semiconductor device further comprises:
[0013] A connecting portion is a recessed portion formed on the surface of the substrate, and the connecting portion connects the first opening and the second opening.
[0014] In some embodiments, a lateral dimension of the second opening is less than or equal to one-half of a lateral dimension of the first opening.
[0015] In some embodiments, the second opening has the same shape as the first opening.
[0016] In some embodiments, one or more second openings are formed around the first opening.
[0017] In some embodiments, two or more second openings are symmetrically distributed around the first opening.
[0018] In some embodiments, among the two or more second openings, the second opening that is farther away from the first opening has a smaller area.
[0019] According to another aspect of an embodiment of the present application, a method for manufacturing a semiconductor device is provided, the method comprising:
[0020] forming a photoresist pattern on a surface of a substrate, the photoresist pattern comprising a first opening pattern and a second opening pattern, the area of the second opening pattern being smaller than the area of the first opening pattern, and the surface of the substrate being exposed from the first opening pattern and the second opening pattern; and
[0021] Using the photoresist pattern as a mask, the surface of the substrate is etched to form a first opening corresponding to the first opening pattern and a second opening corresponding to the second opening pattern, wherein the first opening passes through the surface and back side of the substrate, a first material layer disposed on the back side is exposed from the first opening, a first distance is provided between the second opening and the first opening, and an area of the second opening is smaller than an area of the first opening.
[0022] In some embodiments, the photoresist pattern further includes a connecting portion pattern connecting the first opening pattern and the second opening pattern.
[0023] The beneficial effect of the present application is that the semiconductor device has a first opening and a second opening, the second opening is arranged near the first opening, and the area of the second opening is smaller than the area of the first opening. Since the longitudinal etching speed of the second opening is lower than the longitudinal etching speed of the first opening, the etching reaction gas is consumed by the material in the second opening, which can avoid the etching reaction gas from laterally etching the first opening to form a notch, thereby improving the yield and reliability of the semiconductor device.
[0024] With reference to the following description and accompanying drawings, the specific embodiments of the present application are disclosed in detail, indicating the way in which the principles of the present application can be adopted. It should be understood that the embodiments of the present application are not limited in scope. Within the scope of the spirit and clauses of the appended claims, the embodiments of the present application include many changes, modifications and equivalents.
[0025] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.
[0026] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation methods of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:
[0028] Figure 1 It is a cross-sectional schematic diagram of the notch structure;
[0029] Figure 2 is a top view of a semiconductor device according to an embodiment of the present application;
[0030] Figure 3 yes Figure 2 A cross-sectional view along the AA direction;
[0031] Figure 4 is a schematic diagram of another embodiment of the first opening and the second opening;
[0032] Figure 5 is a schematic diagram of another embodiment of the first opening and the second opening;
[0033] Figure 6 is a schematic diagram of yet another embodiment of the first opening and the second opening;
[0034] Figure 7 It is a schematic diagram of the distribution of functional areas and non-functional areas of a semiconductor device;
[0035] Figure 8 It is a schematic diagram of a method for manufacturing a semiconductor device of the present application. DETAILED DESCRIPTION
[0036] With reference to the accompanying drawings, the above and other features of the present application will become apparent through the following description. In the description and the accompanying drawings, specific embodiments of the present application are specifically disclosed, which show some embodiments in which the principles of the present application can be adopted. It should be understood that the present application is not limited to the described embodiments. On the contrary, the present application includes all modifications, variations and equivalents falling within the scope of the attached claims.
[0037] In the description of the various embodiments of the present application, for the convenience of description, the direction parallel to the surface of the substrate is called "lateral", the direction perpendicular to the surface of the substrate is called "longitudinal", and the longitudinal dimension of each component can be called "height", "thickness" or "depth".
[0038] It should be noted that the above-mentioned “horizontal” and “vertical” are only for the convenience of explanation and do not limit the orientation or posture of the semiconductor device of the present application during manufacturing or use.
[0039] Embodiments of the present application provide a semiconductor device and a method for manufacturing the same.
[0040] Figure 2 is a top view of a semiconductor device according to an embodiment of the present application, Figure 3 yes Figure 2 Cross-sectional view along the AA direction.
[0041] like Figure 2 and Figure 3 As shown, the semiconductor device 200 of the embodiment of the present application includes: a substrate 3 (such as Figure 3 ), a first material layer 2 (as shown) formed on the back side of the substrate 3 Figure 3 As shown), a first opening 41 and a second opening 42.
[0042] The material of the substrate 3 is, for example, silicon or other semiconductor materials. In the following description of the present application, the material of the substrate 3 is silicon as an example for description, and the content of the description is also applicable to the case where the material of the substrate 3 is other semiconductor materials.
[0043] The first material layer 2 may be a dielectric material, and when etching the substrate 3 (e.g., dry etching), there is a higher etching rate ratio between the first material layer 2 and the substrate 3, so that the first material layer 2 may serve as an etching stop layer. In some examples, the dielectric material may be silicon oxide (e.g., the substrate 3 is the top silicon of SOI, and the first material layer 2 is the buried oxide layer of SOI) or an electrostatic film, etc.
[0044] The first opening 41 is formed on the surface of the substrate 3 and penetrates the surface and the back surface of the substrate 3 , so that the first material layer 2 is exposed from the first opening 41 .
[0045] The second opening 42 is formed on the surface of the substrate 3, and has a first distance from the first opening 42, and the area of the second opening 42 is smaller than the area of the first opening 41. The area of the first opening 41 refers to the lateral area of the first opening 41 in a direction parallel to the surface of the substrate 3; the area of the second opening 42 refers to the lateral area of the second opening 42 in a direction parallel to the surface of the substrate 3.
[0046] In the present application, the area of the second opening 42 is smaller than the area of the first opening 41. According to the load effect, the etching depth of the second opening 42 is smaller than the etching depth of the first opening 41. Therefore, when the first opening 41 penetrates the surface and the back side of the substrate 3, the second opening 42 has not yet been etched through. Therefore, there is still substrate material in the second opening 42 to continuously consume the reaction gas (for example, dry etching is performed during the etching process). In this way, as long as there is still reacted material in the etching direction (that is, the second opening 42 has not yet been etched through, and there is still substrate material in the second opening 42), the reaction gas will not diffuse in other directions. Therefore, the reaction gas will not diffuse laterally in the first opening 41, thereby suppressing the notch effect in the first opening 41.
[0047] like Figure 3 As shown, in the embodiment of the present application, at the bottom of the first opening 41 , at the portion where the substrate 3 contacts the first material layer 2 , the notch structure is suppressed.
[0048] like Figure 2 and Figure 3 As shown, in some embodiments, the semiconductor device 200 further includes: a connection portion 5. The connection portion 5 is a recess formed on the surface of the substrate 3. The connection portion 5 can connect the first opening 41 and the second opening 42, thereby facilitating the distribution of the reaction gas between the first opening 41 and the second opening 42. For example, the reaction gas in the second opening 42 can easily enter the second opening 42 through the connection portion 5 to etch the second opening 42, thereby making the etching process continuous at the microscopic level.
[0049] In the present application, the lateral dimension of the second opening 42 is smaller than that of the first opening 41, and thus the area of the second opening 42 is smaller than that of the first opening 41. In some examples, the lateral dimension of the second opening 42 is less than or equal to half of the lateral dimension of the first opening 41.
[0050] like Figure 2 and Figure 3 As shown, in some embodiments, one or more second openings 42 are formed around the first opening 41. For example, Figure 2 In the embodiment, four second openings 42 are formed around the first opening 41 .
[0051] In the present application, when two or more second openings 42 are formed around one first opening 41, the two or more second openings 42 may be symmetrically distributed around the first opening 41, for example, the two or more second openings 42 are centrally symmetrical with respect to the center position of the first opening 41, or the two or more second openings 42 are axially symmetrical with respect to a straight line passing through the first opening 41. In addition, the present application is not limited thereto, and the two or more second openings 42 may also be asymmetrically distributed around the first opening 41.
[0052] In the present application, when two or more second openings 42 are formed around one first opening 41, the distances (i.e., the first distances) between the two or more second openings 42 and the first opening 41 may be different. For example, the farther the second opening 42 is from the first opening 41, the smaller the area. In addition, the present application is not limited thereto, and the areas of the plurality of second openings 42 at different distances from the first opening 41 may be the same.
[0053] In the present application, the second opening 42 and the first opening 41 may have the same shape. Figure 2 In the embodiment, the first opening 41 is circular, and the second opening 42 is also circular.
[0054] Figure 4 , Figure 5 , Figure 6 Schematic diagram of other embodiments of the first opening and the second opening.
[0055] exist Figure 4 In the embodiment, the first opening 41 and the second opening 42 are both circular. Figure 4 The plurality of second openings 42 are compared to Figure 2 The plurality of second openings 42 are distributed around the first opening 41 by being rotated by a predetermined angle (for example, the predetermined angle is 45 degrees).
[0056] exist Figure 5 In (a) and (b), the first opening 41 and the second opening 42 are both rectangular. Figure 5 In (a) and (b), the positions of the second openings 42 distributed around the first opening 41 are different.
[0057] exist Figure 3 , Figure 4 and Figure 5 In the embodiment, the first opening 41 and the second opening 42 may be holes or cavities, wherein a hole refers to an opening whose ratio of the transverse dimension to the longitudinal dimension is less than a predetermined value, and a cavity refers to an opening whose ratio of the transverse dimension to the longitudinal dimension is greater than a predetermined value.
[0058] exist Figure 6 In (a) and (b), the first opening 41 and the second opening 42 are both rectangular. Figure 6 In (a) and (b), the positions and numbers of the second openings 42 distributed around the first opening 41 are different. Figure 6 In (a) and (b), the second opening 42 and the first opening 41 are groove-shaped, and the second opening 42 is distributed on both sides of the first opening 41. The farther the second opening 42 is from the first opening 41, the smaller the area of the second opening 42 is.
[0059] In some other embodiments of the present application, the second opening 42 and the first opening 41 may also be of different shapes. For example, the first opening 41 may be rectangular, and the second opening 42 may be circular.
[0060] In the present application, the first opening 41 may be located in a functional area, and the second opening 42 may be located in a non-functional area (i.e., an invalid area), wherein the functional area may be an area for realizing a semiconductor device function, for example, an area for realizing a micro-electromechanical system (MEMS) function, or an area for realizing a circuit function. In some examples, the functional area may be an area where a movable structure is provided or an area where a circuit is provided. The non-functional area is an area not used to realize a semiconductor device function. In the present application, the first opening 41 is an opening for realizing a semiconductor device function, and the second opening 42 is an opening not used to realize a semiconductor device function, and the function of the second opening 42 is to suppress or eliminate the gap in the first opening 41.
[0061] Figure 7 It is a schematic diagram of the distribution of functional areas and non-functional areas of semiconductor devices. Figure 7 (a), (b), (c) and (d) show different distributions of functional areas and non-functional areas, wherein the non-functional area can be located at the edge and / or the middle of the functional area.
[0062] An embodiment of the present application also provides a method for manufacturing a semiconductor device.
[0063] Figure 8 is a schematic diagram of a method for manufacturing a semiconductor device of the present application, Figure 8 As shown, the method for manufacturing a semiconductor device of the present application includes:
[0064] 801. Form a photoresist pattern on a surface of a substrate, wherein the photoresist pattern includes a first opening pattern and a second opening pattern, wherein an area of the second opening pattern is smaller than an area of the first opening pattern, and a surface of the substrate is exposed from the first opening pattern and the second opening pattern;
[0065] 802. Using the photoresist pattern as a mask, etching the surface of the substrate to form a first opening corresponding to the first opening pattern and a second opening corresponding to the second opening pattern.
[0066] The first opening passes through the surface and back side of the substrate, a first material layer disposed on the back side is exposed from the first opening, a first distance is provided between the second opening and the first opening, and an area of the second opening is smaller than an area of the first opening. In some embodiments, a lateral dimension of the second opening pattern is smaller than or equal to one half of a lateral dimension of the first opening pattern.
[0067] In addition, the photoresist pattern further includes a connecting portion pattern, and the connecting portion pattern connects the first opening pattern and the second opening pattern.
[0068] For the description of the first opening and the second opening obtained in 802, reference may be made to the description of the first opening 41 and the second opening 42 described above. For the description of the photoresist pattern in 801, reference may be made to the description of the semiconductor device described above, wherein the shapes and areas of the first opening pattern, the second opening pattern and the connecting portion pattern of the photoresist pattern correspond to the first opening 41, the second opening 42 and the connecting portion 5, respectively.
[0069] In the present application, the semiconductor device has a first opening and a second opening, the second opening is arranged near the first opening, and the area of the second opening is smaller than the area of the first opening. Since the longitudinal etching speed of the second opening is lower than the longitudinal etching speed of the first opening, the etching reaction gas is consumed by the material in the second opening, which can avoid the etching reaction gas from laterally etching the first opening to form a notch, thereby improving the yield and reliability of the semiconductor device.
[0070] The present application is described above in conjunction with specific implementation methods, but it should be clear to those skilled in the art that these descriptions are exemplary and are not intended to limit the scope of protection of the present application. Those skilled in the art can make various modifications and variations to the present application based on the spirit and principles of the present application, and these modifications and variations are also within the scope of the present application.
Claims
1. A semiconductor device, characterized in that: The semiconductor device comprises: substrate; a first material layer formed on the back side of the substrate; a first opening formed on a surface of the substrate and penetrating the surface and back surface of the substrate, wherein the first material layer is exposed from the first opening; and The second opening is formed on the surface of the substrate and has a first distance from the first opening. The area of the second opening is smaller than that of the first opening.
2. The semiconductor device according to claim 1, wherein The semiconductor device further comprises: A connecting portion is a recessed portion formed on the surface of the substrate, and the connecting portion connects the first opening and the second opening.
3. The semiconductor device according to claim 1, wherein A lateral dimension of the second opening is less than or equal to half of a lateral dimension of the first opening.
4. The semiconductor device according to claim 1, wherein The second opening has the same shape as the first opening.
5. The semiconductor device according to claim 1, wherein: One or more than two second openings are formed around the first opening.
6. The semiconductor device according to claim 5, characterized in that Two or more second openings are symmetrically distributed around the first opening.
7. The semiconductor device according to claim 5, characterized in that Among the two or more second openings, the area of the second opening that is farther from the first opening is smaller.
8. A method for manufacturing a semiconductor device, characterized in that: The manufacturing method comprises: forming a photoresist pattern on a surface of a substrate, the photoresist pattern comprising a first opening pattern and a second opening pattern, the area of the second opening pattern being smaller than the area of the first opening pattern, and the surface of the substrate being exposed from the first opening pattern and the second opening pattern; and Using the photoresist pattern as a mask, etching the surface of the substrate to form a first opening corresponding to the first opening pattern and a second opening corresponding to the second opening pattern, The first opening passes through the surface and back side of the substrate, a first material layer disposed on the back side is exposed from the first opening, a first distance is provided between the second opening and the first opening, and an area of the second opening is smaller than an area of the first opening.
9. The method for manufacturing a semiconductor device according to claim 8, wherein: The photoresist pattern further includes a connection portion pattern connecting the first opening pattern and the second opening pattern.
10. The method for manufacturing a semiconductor device according to claim 8, wherein: A lateral dimension of the second opening pattern is less than or equal to one half of a lateral dimension of the first opening pattern.