Manufacturing method of gate structure of SONOS (Silicon Oxide Nitride Oxide Semiconductor) device and SONOS device
By forming a sidewall oxide layer and forming a protective oxide layer in the gate structure of the SONOS device, the damage problem of ONO structure by wet etching is solved, and the performance and reliability of the device are improved.
Patent Information
- Application Number
- CN202411330189.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-23
- Publication Date
- 2024-12-27
AI Technical Summary
When wet etching removes the hard mask layer, damages the ONO structure oxide layer of the SONOS device, reducing device performance and reliability.
When manufacturing the gate structure of SONOS devices, sidewall oxide layers are formed on both sides of the ONO structure and the polysilicon gate, and protective oxide layers are formed by high-temperature or low-temperature plasma oxidation to protect the ONO structure and sidewall oxide layers to avoid Damage caused by wet etching.
It effectively protects the ONO structure and sidewall oxide layer, improves the performance and reliability of the device, and avoids damage to the device by wet etching.
Smart Images
Figure CN119208145A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a gate structure of a SONOS device and a SONOS device. Background Art
[0002] In SONOS memory, SONOS is the abbreviation of Silicon-Oxide-Nitride-Oxide-Silicon, and ONO is the abbreviation of Oxide-Nitride-Oxide, which is the abbreviation of oxide-nitride-oxide. Information is stored in SONOS memory through the ONO layer. After the ONO structure and polysilicon gate of the SONOS device are formed, the nitrogen dioxide hard mask layer on the polysilicon gate is removed by wet etching. This process removes the oxide layer of the ONO structure, causing damage to the ONO structure, such as Figure 1 Defects such as pits generated in the middle circle affect device performance and reliability.
[0003] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Summary of the invention
[0004] The object of the present invention is to provide a method for manufacturing a gate structure of a SONOS device and a SONOS device, so as to solve the problem that when the hard mask layer is removed by wet etching, the oxide layer of the ONO structure is damaged, thereby reducing the performance and reliability of the device.
[0005] In order to solve the above technical problems, the present invention provides a method for manufacturing a gate structure of a SONOS device, comprising:
[0006] Providing a substrate, and sequentially forming an ONO structure, a polysilicon layer, and a hard mask layer on the substrate;
[0007] Patterning the hard mask layer, and etching the polysilicon layer using the patterned hard mask layer as a hard mask to form a gate;
[0008] After etching the polysilicon layer, a sidewall oxide layer is formed on both sides of the gate;
[0009] Oxidizing the gate with the sidewall oxide layer to form a protective oxide layer;
[0010] The hard mask layer is removed.
[0011] Preferably, the ONO structure is formed by sequentially stacking a first oxide layer, a second nitride layer and a third oxide layer. When depositing the third oxide layer, it is grown on the surface of the second nitride layer by thermal oxidation or low-pressure in-situ water vapor oxidation.
[0012] Preferably, the hard mask layer comprises a silicon dioxide layer and a nitrogen dioxide layer, and the thickness of the silicon dioxide layer is The thickness of the nitrogen dioxide layer is
[0013] Preferably, the thickness of the polysilicon layer is The deposition temperature when forming polysilicon is 550°C-850°C.
[0014] Preferably, after etching the polysilicon layer, forming a sidewall oxide layer on both sides of the gate comprises:
[0015] The sidewall oxide layer is formed by a rapid thermal oxidation method, wherein the temperature of the polysilicon gate sidewall oxide layer formed by the rapid thermal oxidation method is 800° C.-1000° C., and the thickness of the sidewall oxide layer is
[0016] Preferably, oxidizing the gate having the sidewall oxide layer to form the protective oxide layer comprises:
[0017] A high temperature thermal oxidation process is used to oxidize the gate having the sidewall oxide layer to form a protective oxide layer, wherein the temperature of the high temperature thermal oxidation process is 850° C.-1100° C.
[0018] Preferably, oxidizing the gate having the sidewall oxide layer to form the protective oxide layer comprises:
[0019] A low-temperature plasma oxidation method is used to oxidize the gate having the sidewall oxide layer to form a protective oxide layer, wherein the temperature of the low-temperature plasma oxidation is 25°C-400°C.
[0020] Preferably, the low-temperature plasma oxidation method has a treatment time of 5 seconds to 4 minutes, a treatment pressure of 8 mTorr to 40 mTorr, an oxygen flow rate of 130 to 270 ml / min, and a volume ratio of oxygen to helium in the range of 1:1 to 1:20.
[0021] Preferably, when the gate is oxidized by the low-temperature plasma oxidation method, a pulse mode is adopted, and the radio frequency is 200 watts to 1800 watts.
[0022] Based on the same inventive concept, the present invention further provides a SONOS device, including manufacturing a gate structure on a substrate using the above-mentioned method for manufacturing a gate structure of a SONOS device.
[0023] Compared with the prior art, the method for manufacturing the gate structure of the SONOS device of the present invention has the following advantages:
[0024] The present invention forms a protective oxide layer by oxidizing the ONO structure. When wet etching is used to remove the hard mask layer, not only the oxide layer of the ONO structure can be protected, but also the sidewall oxide layers on both sides of the gate can be protected, thereby avoiding damage to the ONO structure and the gate structure caused by wet etching, and improving device performance and reliability.
[0025] The SONOS device provided by the present invention and the method for manufacturing the gate structure of the SONOS device provided by the present invention belong to the same inventive concept. Therefore, the SONOS device provided by the present invention at least has all the advantages of the method for manufacturing the gate structure of the SONOS device provided by the present invention, and the SONOS device provided by the present invention can maintain good performance and reliability. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 It is an electron scan of a gate structure;
[0027] Figure 2 is a flow chart of a method for manufacturing a gate structure of a SONOS device in one embodiment of the present invention;
[0028] Figure 3 It is a structural schematic diagram of sequentially forming an ONO structure, a polysilicon layer and a hard mask layer on a substrate in one embodiment of the present invention;
[0029] Figure 4 is a schematic diagram of a structure in which sidewall oxide layers are formed on both sides of a polysilicon layer in one embodiment of the present invention;
[0030] Figure 5 It is a schematic diagram of a structure for setting a time for performing oxidation repair on an ONO structure to form a protective oxide layer in one embodiment of the present invention;
[0031] Figure 6 is a schematic diagram of the structure after the hard mask layer is removed in one embodiment of the present invention;
[0032] In the figure,
[0033] 100-substrate; 200-ONO structure;
[0034] 210-first oxide layer; 220-second nitride layer;
[0035] 230-third oxide layer; 300-polysilicon layer;
[0036] 400-hard mask layer; 410-silicon dioxide layer;
[0037] 420-nitrogen dioxide layer; 500-side wall oxide layer;
[0038] 600-Protective oxide layer. DETAILED DESCRIPTION
[0039] In order to make the purpose, advantages and features of the present invention clearer, the manufacturing method of the gate structure of the SONOS device and the SONOS device proposed in the present invention are further described in detail in combination with the drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be understood that the drawings in the specification do not necessarily show the specific structure of the present invention in proportion, and the illustrative features used to illustrate certain principles of the present invention in the drawings in the specification will also adopt a slightly simplified drawing method. The specific design features of the present invention disclosed herein include, for example, specific dimensions, directions, positions and shapes, which will be determined in part by the specific application and use environment. In addition, in the embodiments described below, the same figure mark is sometimes used in common between different drawings to represent the same part or a part with the same function, and its repeated description is omitted. In this specification, similar numbers and letters are used to represent similar items, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.
[0040] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.
[0041] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.
[0042] In the existing method for manufacturing the ONO gate structure of the SONOS memory, when the hard mask layer is cleaned by wet etching using phosphoric acid as a cleaning agent, not only the oxide layer of the ONO structure is damaged, but also the sidewall oxide layer 500 formed by the gate is damaged, thereby reducing the device performance and reliability.
[0043] The core idea of the present invention is to provide a method for manufacturing a gate structure of a SONOS device, which can solve the technical problem that wet etching damages the oxide layer of the ONO structure, resulting in reduced device performance and reliability.
[0044] In order to realize the above idea, the present invention provides a method for manufacturing a gate structure of a SONOS device. Figures 2 to 6 A specific implementation of a method for manufacturing a gate structure of a SONOS device is disclosed. The method for manufacturing a gate structure of a SONOS device includes the following steps S1 to S5.
[0045] Step S1: providing a substrate 100 , and sequentially forming an ONO structure 200 , a polysilicon layer 300 , and a hard mask layer 400 on the substrate 100 .
[0046] Specifically, refer to Figure 2 and Figure 3 As shown, the material of the substrate 100 can be silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, etc., or it can be silicon on insulator, germanium on insulator; or it can also be other materials, such as III-V compounds such as gallium arsenide. In this embodiment, the material of the substrate 100 is silicon. Among them, the ONO structure 200 includes a first oxide layer 210, a second nitride layer 220 and a third oxide layer 230. When forming the ONO structure 200, first, the first oxide layer 210 is deposited on the surface of the substrate 100. Then, the second nitride layer 220 is deposited on the surface of the first oxide layer 210. Finally, the third oxide layer 230 is deposited on the surface of the second nitride layer 220. When depositing the third oxide layer 230, it is grown by thermal oxidation or low-pressure in-situ water vapor oxidation. It should be noted that the thermal oxidation method or low-pressure in-situ water vapor oxidation method to grow the third oxide layer 230 on the surface of the second nitride layer 220 is a prior art. For those skilled in the art, they are already familiar with its specific process and will not be repeated here.
[0047] After the third oxide layer 230 is deposited, a polysilicon layer 300 is deposited on the surface of the third oxide layer 230. When the polysilicon layer 300 is deposited, for example, the polysilicon layer 300 can be grown by a vapor deposition method such as physical vapor deposition or chemical vapor deposition. The thickness of the deposited polysilicon layer 300 is The deposition temperature is 550° C.-850° C. That is, the thickness of the polysilicon layer 300 can be or The temperature of vapor deposition of the polysilicon layer 300 may be 550°C, 600°C, 650°C, 700°C, 750°C, 800°C, 850°C, or any value within the range of 550°C-850°C.
[0048] The hard mask layer 400 includes a silicon dioxide layer 410 and a nitrogen dioxide layer 420. After the polysilicon layer 300 is deposited, the silicon dioxide layer 410 and the nitrogen dioxide layer 420 are sequentially deposited on the surface of the polysilicon layer 300 to form the hard mask layer 400 on the surface of the polysilicon layer 300. The thickness of the silicon dioxide layer 410 is The thickness of the silicon dioxide layer 410 may be or The thickness of the nitrogen dioxide layer is or Any value in the range.
[0049] Step S2: patterning the hard mask layer, and using the patterned hard mask layer as a hard mask to etch the polysilicon layer 300 to form a gate.
[0050] Specifically, refer to Figure 2 and Figure 4 As shown, the hard mask layer is patterned, and the patterned hard mask layer is used as a hard mask to etch the polysilicon layer 300, including:
[0051] First, photoresist is spin-coated on the hard mask layer 400 .
[0052] Next, the etched pattern is transferred to the photoresist through exposure and development.
[0053] Then, etching is performed to transfer the pattern on the photoresist to the hard mask layer 400, so as to pattern the hard mask layer 400. During etching, dry etching or wet etching can be used to transfer the pattern on the photoresist to the hard mask layer 400.
[0054] Finally, the polysilicon layer 300 is etched using the patterned hard mask layer 400 as a mask.
[0055] Step S3: after etching the polysilicon layer 300 , a sidewall oxide layer 500 is formed on both sides of the gate.
[0056] Specifically, refer to Figure 2 and Figure 5As shown, after the polysilicon layer 300 is etched, a sidewall oxide layer 500 is formed on both sides of the etched polysilicon layer 300 by a rapid thermal oxidation method. The temperature of the sidewall oxide layer 500 formed by the rapid thermal oxidation method is 800° C.-1000° C., and the thickness of the sidewall oxide layer 500 is That is, the temperature for forming the sidewall oxide layer 500 can be 800° C., 850° C., 900° C., 1000° C., or any value within the range of 800° C.-1000° C. The thickness of the sidewall oxide layer 500 can be or It should be noted that the rapid thermal oxidation method is a prior art, and those skilled in the art are already familiar with its specific process steps, which will not be described in detail here.
[0057] Step S4 : oxidizing the gate with the sidewall oxide layer 500 to form a protective oxide layer 600 .
[0058] Specifically, refer to Figure 2 and Figure 5 As shown, as one of the embodiments, a high temperature thermal oxidation process is used to oxidize the gate forming the sidewall oxide layer to form a protective oxide layer 600, wherein the temperature of the high temperature thermal oxidation process is 850°C-1100°C. That is, the temperature of the high temperature thermal oxidation process can be 850°C, 900°C, 1000°C, 1100°C, or any value within the range of 850°C-1100°C. This embodiment uses a high temperature thermal oxidation process to oxidize the gate forming the sidewall oxide layer 500 to form a protective oxide layer 600. When phosphoric acid is used to remove the hard mask layer 400, the protective oxide layer 600 is first consumed without damaging the oxide layer and the sidewall oxide layer 500 of the ONO structure, thereby improving device performance and reliability.
[0059] As another embodiment, a low-temperature plasma oxidation method is used to oxidize the gate forming the sidewall oxide layer 500 for 5 seconds to 4 minutes to form a protective oxide layer 600, wherein the temperature of the low-temperature plasma oxidation is 25°C-400°C. The temperature of the low-temperature plasma oxidation is 25°C-400°C, and the processing pressure is 8 mTorr-40 mTorr. The plasma is excited by mixing oxygen and helium in a volume ratio of 1:1-1:20. The oxygen flow rate is 130-270 ml / min. The temperature of the low-temperature plasma oxidation can be 25°C, 50°C, 100°C, 150°C, 200°C, 300°C, 400°C, or any value in the range of 25°C-400°C. The processing pressure can be 8 mTorr, 15 mTorr, 30 mTorr, 40 mTorr, or any value in the range of 8 mTorr-40 mTorr. The volume ratio of the mixed gas oxygen and helium for generating low-temperature plasma can be 1:1, 1:5, 1:10, 1:20, or any ratio in the range of 1:1-1:20. The low-temperature plasma oxidation method can adopt a continuous mode or a pulse mode. When the pulse mode is adopted, the radio frequency frequency is 200 watts-1800 watts. That is, the radio frequency frequency can be 200 watts, 500 watts, 800 watts, 1500 watts, 1800 watts, or any value in the range of 200 watts-1800 watts. By adopting a low-temperature plasma oxidation method with a temperature range of 25°C-400°C, the ONO structure 200 is oxidized and repaired to form a protective oxide layer 600, thereby being able to solve the damage caused to the ONO structure 200 by wet etching and improve device performance and reliability.
[0060] Step S5: removing the hard mask layer 400 .
[0061] Specifically, refer to Figure 2 and Figure 6 As shown, when removing the hard mask layer 400, it is removed by wet etching, and the sidewall oxide layer 500 on the surface of the ONO structure layer is removed to form Figure 6 The structure shown. The wet etching solution is phosphoric acid, and the etching time is 10 minutes to 30 minutes.
[0062] In the method for manufacturing the gate structure of the SONOS device provided in this embodiment, after forming the sidewall oxide layer 500 on both sides of the gate side, a protective oxide layer 600 is formed on both sides of the sidewall oxide layer 500 and the ONO structure layer. When phosphoric acid is used to clean the hard mask layer 400, only the protective oxide layer 600 can be consumed, while the oxide layer and the sidewall oxide layer 500 in the ONO structure can be prevented from being damaged, thereby improving the device performance and reliability.
[0063] To realize the above idea, this embodiment further discloses a SONOS device, including: manufacturing a gate structure on a substrate 100 using the above-mentioned method for manufacturing a gate structure of a SONOS device.
[0064] The SONOS device provided in this embodiment and the method for manufacturing the gate structure of the SONOS device provided in this embodiment belong to the same inventive concept. Therefore, the SONOS device provided in this embodiment has at least all the advantages of the method for manufacturing the gate structure of the SONOS device provided in this embodiment, and the SONOS device provided in this embodiment can maintain good performance and reliability.
[0065] In summary, the above embodiments provide detailed descriptions of the manufacturing method of the gate structure of the SONOS device and the different configurations of the SONOS device. Of course, the above description is only a description of the preferred embodiments of the present invention, and is not any limitation to the scope of the present invention. The present invention includes but is not limited to the configurations listed in the above embodiments. Those skilled in the art can draw inferences based on the contents of the above embodiments. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A method for manufacturing a gate structure of a SONOS device, characterized in that: include: Providing a substrate, and sequentially forming an ONO structure, a polysilicon layer, and a hard mask layer on the substrate; Patterning the hard mask layer, and etching the polysilicon layer using the patterned hard mask layer as a hard mask to form a gate; After etching the polysilicon layer, a sidewall oxide layer is formed on both sides of the gate; Oxidizing the gate with the sidewall oxide layer to form a protective oxide layer; The hard mask layer is removed.
2. The method for manufacturing a gate structure of a SONOS device according to claim 1, characterized in that: The ONO structure is formed by sequentially stacking a first oxide layer, a second nitride layer and a third oxide layer. When depositing the third oxide layer, it grows on the surface of the second nitride layer by thermal oxidation or low-pressure in-situ water vapor oxidation.
3. The method for manufacturing a gate structure of a SONOS device according to claim 1, characterized in that: The hard mask layer includes a silicon dioxide layer and a nitrogen dioxide layer. The thickness of the silicon dioxide layer is The thickness of the nitrogen dioxide layer is 4. The method for manufacturing a gate structure of a SONOS device according to claim 1, characterized in that: The thickness of the polysilicon layer is The deposition temperature when forming polysilicon is 550°C-850°C.
5. The method for manufacturing a gate structure of a SONOS device according to claim 1, characterized in that: The step of forming sidewall oxide layers on both sides of the gate after etching the polysilicon layer comprises: The sidewall oxide layer is formed by a rapid thermal oxidation method, wherein the temperature of the polysilicon gate sidewall oxide layer formed by the rapid thermal oxidation method is 800° C.-1000° C., and the thickness of the sidewall oxide layer is 6. The method for manufacturing a gate structure of a SONOS device according to claim 1, characterized in that: The step of oxidizing the gate having the sidewall oxide layer to form the protective oxide layer comprises: A high temperature thermal oxidation process is used to oxidize the gate having the sidewall oxide layer to form a protective oxide layer, wherein the temperature of the high temperature thermal oxidation process is 850° C.-1100° C.
7. The method for manufacturing a gate structure of a SONOS device according to claim 1, characterized in that: The step of oxidizing the gate having the sidewall oxide layer to form the protective oxide layer comprises: A low-temperature plasma oxidation method is used to oxidize the gate having the sidewall oxide layer to form a protective oxide layer, wherein the temperature of the low-temperature plasma oxidation is 25°C-400°C.
8. The method for manufacturing a gate structure of a SONOS device according to claim 7, characterized in that: The low-temperature plasma oxidation method has a treatment time of 5 seconds to 4 minutes, a treatment pressure of 8 mTorr to 40 mTorr, an oxygen flow rate of 130 to 270 ml / min, and a volume ratio of oxygen to helium in the range of 1:1 to 1:
20.
9. The method for manufacturing a gate structure of a SONOS device according to claim 7, characterized in that: When the gate is oxidized by a low temperature plasma oxidation method, a pulse mode is adopted and the radio frequency is 200 watts to 1800 watts.
10. A SONOS device, characterized in that: include: The gate structure is manufactured on a substrate by using the method for manufacturing a gate structure of a SONOS device according to any one of claims 1 to 9.