Wafer cutting method and device, chip and storage medium

Abstract

The invention discloses a wafer cutting method and device, a chip and a storage medium. The wafer cutting method comprises the following steps: providing a wafer; the wafer comprises a functional area and a test area; the functional area surrounds the test area, the test area comprises a central area and an edge area, and the edge area surrounds the central area; the edge area of the test area is a pure silicon layer; determining a preset scribing image of the wafer; determining a plurality of scribing channels of the wafer according to a preset scribing image of the wafer; the plurality of scribing channels comprise a plurality of first scribing channels and a plurality of second scribing channels; the first scribing channel is located in the edge areas of the functional area and the test area, and the second scribing channel is located in the central area of the test area; cutting the plurality of second scribing channels for the first time to a preset depth; and cutting the plurality of first scribing channels and the plurality of cut second scribing channels for the second time. According to the invention, the yield and quality of wafer cutting can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a wafer cutting method, equipment, chip and storage medium. Background Art

[0002] Wafer Acceptance Test (WAT) is a key test in the wafer manufacturing process, also known as wafer acceptance test or wafer acceptance test, and sometimes referred to as process control monitor (PCM) in the industry. The main purpose of the WAT test is to measure the electrical parameters of specific test structures on the wafer after the wafer product is taped out and before quality inspection, so as to evaluate the quality and stability of the semiconductor manufacturing process and determine whether the wafer product meets the electrical specification requirements of the process technology platform.

[0003] The wafer can be divided into a functional area and a test area. The functional area includes functional chips, which are the final product chips, and the test area includes test chips. Due to their special material composition, the test chips in the test area will only form slight etching marks on the surface during plasma etching and dicing, and will maintain a relatively complete structure. In the subsequent packaging process, if the test area is large, it may have a significant tension effect on the UV film covering it, resulting in uneven distribution of surface tension of the UV film. This uneven tension phenomenon may further interfere with the stability and accuracy of the functional chips around the test area during the cutting process, posing a potential challenge to the yield and quality of wafer cutting. Summary of the invention

[0004] The present invention provides a wafer cutting method, equipment, chip and storage medium, which can improve the yield and quality of wafer cutting.

[0005] According to one aspect of the present invention, there is provided a wafer cutting method, comprising:

[0006] Providing a wafer; the wafer comprises a functional area and a test area; the functional area surrounds the test area, the test area comprises a central area and an edge area, and the edge area surrounds the central area; the edge area of ​​the test area is a pure silicon layer;

[0007] Determine a plurality of scribing lanes of the wafer; the plurality of scribing lanes include a plurality of first scribing lanes and a plurality of second scribing lanes; the first scribing lanes are located at the edge of the functional area and the test area, and the second scribing lanes are located at the center of the test area;

[0008] Performing a first cutting on the plurality of second dicing streets to a preset depth;

[0009] The plurality of first dicing streets and the plurality of second dicing streets after dicing are cut for a second time.

[0010] Optionally, performing a first cutting on the plurality of second scribing lanes to a preset depth includes:

[0011] The laser grooving process is used to perform a first cutting of the plurality of second scribe lines to a preset depth.

[0012] Optionally, performing a second cutting on the plurality of first dicing streets and the plurality of second dicing streets after cutting, comprises:

[0013] A plasma scribing process is used to perform a second scribing on the plurality of first scribing lanes and the plurality of second scribing lanes after being cut.

[0014] Optionally, a width of the first scribe line is less than or equal to 25 μm.

[0015] Optionally, the plurality of first scribing lanes and the plurality of second scribing lanes each include a plurality of transverse scribing lanes and a plurality of longitudinal scribing lanes; each transverse scribing lane extends along a first direction, and the plurality of transverse scribing lanes are arranged along a second direction; each longitudinal scribing lane extends along the second direction, and the plurality of longitudinal scribing lanes are arranged along the first direction; the first direction and the second direction are perpendicular to each other;

[0016] Each transverse scribing lane of the second scribing lane is located on the same straight line as one of the transverse scribing lanes of the first scribing lanes; each longitudinal scribing lane of the second scribing lane is located on the same straight line as one of the longitudinal scribing lanes of the first scribing lanes.

[0017] Optionally, performing a first cutting on the plurality of second scribing lanes to a preset depth includes:

[0018] Performing a first cutting on a plurality of transverse scribe lines of the second scribe line to a preset depth;

[0019] After the plurality of transverse scribe lines are scribe-ed, the plurality of longitudinal scribe lines of the second scribe line are cut for the first time to a preset depth.

[0020] Optionally, performing a second cutting on the plurality of first dicing streets and the plurality of second dicing streets after cutting, comprises:

[0021] Simultaneously performing a second cutting on the plurality of transverse scribe lines of the plurality of first scribe lines and the plurality of transverse scribe lines of the plurality of second scribe lines after cutting;

[0022] After the cutting of the plurality of transverse scribe lines of the plurality of first scribe lines and the plurality of transverse scribe lines of the plurality of second scribe lines is completed, the plurality of longitudinal scribe lines of the plurality of first scribe lines and the plurality of longitudinal scribe lines of the plurality of second scribe lines are cut for a second time.

[0023] According to another aspect of the present invention, there is provided a chip obtained by using the wafer cutting method described in any embodiment of the present invention.

[0024] According to another aspect of the present invention, there is provided a wafer cutting device, the wafer cutting device comprising:

[0025] at least one processor; and a memory in communication with the at least one processor; wherein,

[0026] The memory stores a computer program that can be executed by at least one processor. The computer program is executed by at least one processor so that the at least one processor can execute the wafer cutting method described in any embodiment of the present invention.

[0027] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to implement the wafer cutting method described in any embodiment of the present invention when executed by a processor.

[0028] The wafer cutting method provided by the technical solution of the embodiment of the present invention includes: providing a wafer; the wafer includes a functional area and a test area; the functional area surrounds the test area, the test area includes a central area and an edge area, and the edge area surrounds the central area; the edge area of ​​the test area is a pure silicon layer; determining multiple scribe lines of the wafer; the multiple scribe lines include multiple first scribe lines and multiple second scribe lines; the first scribe lines are located at the edge areas of the functional area and the test area, and the second scribe lines are located at the central area of ​​the test area; performing a first cutting on the multiple second scribe lines to a preset depth; and performing a second cutting on the multiple first scribe lines and the multiple second scribe lines after cutting. The first scribe line is located at the edge area of ​​the functional area and the test area. When the second scribe line in the central area of ​​the test area is cut to a preset depth, the central area of ​​the test area is far away from the functional chip in the adjacent test area, which can avoid damaging the functional chip in the adjacent test area when cutting the second scribe line in the central area. In addition, since there is a first scribe line at the edge area of ​​the test area, it can be ensured that when a second cutting is performed on multiple first scribe lines and multiple second scribe lines after cutting, the second scribe line in the central area can be disconnected from the first scribe line in the edge area, ensuring that the test area and the functional area can be divided into single chips, thereby improving the yield and quality of wafer cutting.

[0029] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0031] Figure 1 It is a flow chart of a wafer cutting method provided by an embodiment of the present invention.

[0032] Figure 2 It is a schematic diagram of an exposure area of ​​a wafer provided in an embodiment of the present invention.

[0033] Figure 3 This is a physical picture of a portion of a wafer provided by an embodiment of the present invention.

[0034] Figure 4 It is a schematic diagram of a test area provided by an embodiment of the present invention.

[0035] Figure 5 This is a physical picture of a wafer provided by an embodiment of the present invention.

[0036] Figure 6 This is another physical picture of a portion of a wafer provided by an embodiment of the present invention.

[0037] Figure 7 This is a schematic diagram of another partial wafer provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0038] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0039] It should be noted that the terms "first", "second", etc. in the present invention are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products, or devices.

[0040] The embodiment of the present invention provides a wafer cutting method. Figure 1 is a flow chart of a wafer cutting method provided by an embodiment of the present invention, with reference to Figure 1 , wafer dicing methods include:

[0041] S110, providing a wafer; the wafer includes a functional area and a test area; the functional area surrounds the test area, the test area includes a central area and an edge area, and the edge area surrounds the central area; the edge area of ​​the test area is a pure silicon layer;

[0042] in, Figure 2 is a schematic diagram of an exposure area of ​​a wafer provided by an embodiment of the present invention, Figure 3 is a physical picture of a portion of a wafer provided by an embodiment of the present invention. Figure 3 The area in the red circle is the test area 02, and the other areas are the functional area 01. Figure 2 and Figure 3 , the entire wafer is made up of dozens or even hundreds of such exposure areas (shots) to construct a complete chip array; in the exposure area, the green area is the functional area 01, which includes multiple functional chips, and the functional chips occupy most of the surface area of ​​the wafer; and the yellow area is the test area 02, which includes test chips (Test Die) for WAT testing. These test chips are specifically used for WAT testing to evaluate the quality and stability of the manufacturing process. The WAT test does not directly test the functional chips on the wafer, but tests the test chips located in the test area. The test chips can include target devices such as metal oxide semiconductor field effect transistors (MOSFETs), bipolar junction transistors (BJTs), resistors, and capacitors. Figure 4 is a schematic diagram of a test area provided by an embodiment of the present invention, with reference to Figure 4 The test area includes a central area 11 and an edge area 12. The structure in the central area 11 includes a pure silicon layer and a diversified dielectric layer. The diversified dielectric layer includes insulating layers of different materials, circuit layer metals and other non-pure silicon elements, while the edge area is only set as a pure silicon layer to facilitate subsequent cutting.

[0043] S120, determining a plurality of scribing lanes of the wafer; the plurality of scribing lanes include a plurality of first scribing lanes and a plurality of second scribing lanes; the first scribing lanes are located at the edge areas of the functional area and the test area, and the second scribing lanes are located at the center area of ​​the test area.

[0044] In order to divide the wafer into individual chips, the wafer needs to be divided into multiple dicing lanes according to the preset cutting image of the wafer. Each dicing lane needs to be cut, and dicing lanes are set between adjacent functional chips. The preset cutting image is the pattern that the wafer needs to be cut according to actual needs. Figure 5 is a physical picture of a wafer provided by an embodiment of the present invention, refer to Figure 5 , Figure 5 The left side is a physical picture of the wafer, and the right side is a partial enlarged picture of the wafer; reference Figure 4 and Figure 5When dividing the dicing lanes, the first dicing lane 10 is located in the edge area 12 of the functional area 01 and the test area 02. The first dicing lane 10 in the edge area 12 is Figure 4 In the middle red frame, the edge area 12 is set as a pure silicon layer, which can be directly used as a normal dicing path, ensuring that it can be directly cut in the subsequent cutting process; the second dicing path 20 is located in the central area 11 of the test area 02. Since the test chip 13 included in the central area 11 includes a pure silicon layer and a diversified dielectric layer, and the diversified dielectric layer includes non-pure silicon elements such as insulating layers of different materials and circuit layer metals, it is necessary to remove the non-pure silicon elements in the test chip 13 later.

[0045] S130, performing a first cutting on the plurality of second dicing streets to a preset depth.

[0046] Among them, the laser grooving process can be used to perform the first cutting of multiple second scribe lines to a preset depth, and the preset depth can be the depth at which all impure silicon elements on the second scribe lines are removed; during the laser grooving process, due to the concentrated and powerful energy, there is a risk of potential thermal damage to the surrounding chips. Figure 6 is another physical picture of a portion of a wafer provided by an embodiment of the present invention, such as Figure 6 As shown in the red circle, the two chips in the functional area 01 below the slot area are particularly susceptible to being affected, which may damage their performance. Figure 4 In the chip layout design stage, the embodiment of the present invention needs to take preventive measures to reasonably reserve sufficient space around the edge area 12 of the test area 02 as a normal dicing path to ensure that when performing the laser grooving operation in the test area 02, unnecessary heat transfer and damage to the surrounding chips can be effectively avoided, thereby ensuring the yield and product quality of the overall chip manufacturing. Figure 7 is a schematic diagram of another partial wafer provided by an embodiment of the present invention, referring to Figure 7 The second scribe line 20 is cut to a preset depth, and only a pure silicon layer exists in the second scribe line 20 after cutting; the structure in the red frame is the first scribe line in the edge area, and the first scribe line in the edge area can make the functional chip in the adjacent test area and the second scribe line in the test area be separated by a larger distance, thereby avoiding damage to the functional chip on the adjacent second scribe line when removing the impure silicon element on the second scribe line in the test area, thereby improving the yield and quality of wafer cutting.

[0047] S140, performing a second cutting on the plurality of first dicing streets and the plurality of second dicing streets after cutting.

[0048] Among them, after the first cutting of multiple second scribe lines to a preset depth, only pure silicon layer is left on the first scribe lines and the second scribe lines. The multiple first scribe lines and the multiple second scribe lines after cutting can be cut for a second time by plasma scribe, ensuring that the functional areas and test areas on the entire wafer can be accurately and evenly divided into independent single chips.

[0049] The wafer cutting method provided by the technical solution of the embodiment of the present invention includes: providing a wafer; the wafer includes a functional area and a test area; the functional area surrounds the test area, the test area includes a central area and an edge area, and the edge area surrounds the central area; the edge area of ​​the test area is a pure silicon layer; determining multiple scribe lines of the wafer; the multiple scribe lines include multiple first scribe lines and multiple second scribe lines; the first scribe lines are located at the edge areas of the functional area and the test area, and the second scribe lines are located at the central area of ​​the test area; performing a first cutting on the multiple second scribe lines to a preset depth; and performing a second cutting on the multiple first scribe lines and the multiple second scribe lines after cutting. The first scribe line is located at the edge area of ​​the functional area and the test area. When the second scribe line in the central area of ​​the test area is cut to a preset depth, the central area of ​​the test area is far away from the functional chip in the adjacent test area, which can avoid damaging the functional chip in the adjacent test area when cutting the second scribe line in the central area. In addition, since there is a first scribe line at the edge area of ​​the test area, it can be ensured that when a second cutting is performed on multiple first scribe lines and multiple second scribe lines after cutting, the second scribe line in the central area can be disconnected from the first scribe line in the edge area, ensuring that the test area and the functional area can be divided into single chips, thereby improving the yield and quality of wafer cutting.

[0050] Optionally, performing a first cutting on the plurality of second scribing lanes to a preset depth includes: performing a first cutting on the plurality of second scribing lanes to a preset depth using a laser grooving process.

[0051] Among them, the laser grooving technology uses the high energy density generated by a highly focused laser beam to accurately create fine scribe grooves in the test area along the predetermined second scribe line direction; this process penetrates deep into the pure silicon layer of the substrate, laying the foundation for subsequent processing.

[0052] Optionally, the plurality of first scribing lanes and the plurality of second scribing lanes after being cut are cut for a second time, including: using a plasma scribing process to perform a second cut on the plurality of first scribing lanes and the plurality of second scribing lanes after being cut.

[0053] Among them, the Plasma Dicing process is an efficient and precise wafer dicing method that uses advanced plasma etching technology to specifically perform deep etching on the pure silicon layer within the wafer dicing lanes. This process uses the fine control of the Bosch process to ensure that the etching depth can exceed the thickness of the subsequent thinning process that the wafer may undergo, thereby achieving precise dicing boundaries. Whether the wafer is thinned first and then plasma etched, or the boundary is defined by plasma etching before thinning, the Plasma Dicing technology can respond flexibly, demonstrating extremely high process compatibility and operational flexibility. This technology not only improves the accuracy and efficiency of wafer dicing, but also lays a solid foundation for subsequent packaging and testing.

[0054] In the process of plasma etching pure silicon (Plasma Etch Silicon), the plasma technology is highly selective and only accurately etches the pure silicon layer, while the non-pure silicon elements in the test area can effectively resist the influence of plasma etching. Therefore, when performing plasma scribing operations, the normal chip area on the wafer can be accurately cut according to the predetermined path to form independent chip units; and the WAT area, due to its non-pure silicon composition, will only leave slight etching marks on the surface, maintaining a relatively complete structure. Therefore, it is necessary to cut the non-pure silicon elements in the test area before plasma scribing the entire wafer; after completing plasma scribing, the functional area and test area on the wafer will be accurately divided into multiple independent chips.

[0055] Optionally, a width of the first scribe line is less than or equal to 25 μm.

[0056] Among them, reference Figure 5 The first scribing lane 10 includes a transverse scribing lane extending along a first direction X and a longitudinal scribing lane extending along a second direction Y. The width of the transverse scribing lane is the size of the transverse scribing lane along the second direction, and the width of the longitudinal scribing lane is the size of the longitudinal scribing lane along the first direction. The width of the first scribing lane is less than or equal to 25 μm, which can reduce the occupied space of the scribing lane and avoid damaging the functional chip adjacent to the first scribing lane when cutting the first scribing lane, thereby ensuring the quality and yield of the functional chip.

[0057] Optional, reference Figure 5The plurality of first scribing lanes 10 and the plurality of second scribing lanes 20 each include a plurality of transverse scribing lanes and a plurality of longitudinal scribing lanes; each transverse scribing lane extends along a first direction X, and the plurality of transverse scribing lanes are arranged along a second direction Y; each longitudinal scribing lane extends along a second direction Y, and the plurality of longitudinal scribing lanes are arranged along the first direction X; the first direction X and the second direction Y are perpendicular to each other; each transverse scribing lane of the second scribing lanes 20 is respectively located on the same straight line with one of the transverse scribing lanes in the first scribing lanes 10; each longitudinal scribing lane of the second scribing lanes 20 is respectively located on the same straight line with one of the longitudinal scribing lanes in the first scribing lanes 10.

[0058] Among them, multiple transverse scribing lanes are arranged at intervals, and multiple longitudinal scribing lanes are arranged at intervals; each transverse scribing lane of the second scribing lane 20 is located on the same straight line with a transverse scribing lane in the first scribing lane 10, and each transverse scribing lane of the second scribing lane 20 is arranged corresponding to a transverse scribing lane in the first scribing lane 10. Exemplarily, one transverse scribing lane in the second scribing lane 20 is selected as the first transverse scribing lane 31, and one transverse scribing lane in the first scribing lane 10 is selected as the second transverse scribing lane 32, and the first transverse scribing lane 31 and the second transverse scribing lane 32 are located on the same straight line. Each longitudinal scribing lane of the second scribing lane 20 is located on the same straight line with a longitudinal scribing lane in the first scribing lane 10, and each longitudinal scribing lane of the second scribing lane 20 is arranged corresponding to a longitudinal scribing lane in the first scribing lane 10. Exemplarily, one of the longitudinal scribing lanes in the second scribing lane 20 is selected as the first longitudinal scribing lane 41, and one of the longitudinal scribing lanes in the first scribing lane 10 is selected as the second longitudinal scribing lane 42. The first longitudinal scribing lane 41 and the second longitudinal scribing lane 42 are located on the same straight line.

[0059] Optionally, S130, performing a first cutting on the plurality of second dicing streets to a preset depth includes:

[0060] S131, performing a first cutting on a plurality of transverse scribe lines of the second scribe line to a preset depth.

[0061] S132, after the dicing of the plurality of transverse dicing lanes is completed, the plurality of longitudinal dicing lanes of the second dicing lanes are cut for the first time to a preset depth.

[0062] Among them, the horizontal scribing lanes extending along the first direction can be cut first, and after the horizontal scribing lanes are cut, the vertical scribing lanes extending along the second direction can be cut. Alternatively, the vertical scribing lanes can be cut first, and then the horizontal scribing lanes can be cut. This embodiment of the present invention does not specifically limit this until the second scribing lanes in the test area are all cut.

[0063] Optionally, S140, performing a second cutting on the plurality of first dicing streets and the cut plurality of second dicing streets, comprises:

[0064] S141 , simultaneously performing a second cutting on the plurality of transverse scribe lines of the plurality of first scribe lines and the plurality of transverse scribe lines of the plurality of second scribe lines after cutting.

[0065] S142, after the cutting of the plurality of transverse scribe lines of the plurality of first scribe lines and the plurality of transverse scribe lines of the plurality of second scribe lines after cutting is completed, simultaneously cutting the plurality of longitudinal scribe lines of the plurality of first scribe lines and the plurality of longitudinal scribe lines of the plurality of second scribe lines after cutting for a second time.

[0066] Among them, cutting can be performed according to the steps in S141-S142, or multiple longitudinal scribe lines of multiple first scribe lines and multiple longitudinal scribe lines of multiple second scribe lines after cutting can be cut simultaneously, and after the cutting is completed, multiple transverse scribe lines of multiple first scribe lines and multiple transverse scribe lines of multiple second scribe lines after cutting can be cut; cutting the first scribe lines and the second scribe lines at the same time can improve the cutting efficiency.

[0067] An embodiment of the present invention provides a chip based on the above embodiment, which is obtained by using the wafer cutting method described in any embodiment of the present invention.

[0068] A chip provided by the technical solution of the embodiment of the present invention and the wafer cutting method described in any embodiment of the present invention have the same beneficial effects.

[0069] An embodiment of the present invention provides a wafer cutting device based on the above embodiment, and the wafer cutting device includes:

[0070] at least one processor; and a memory in communication with the at least one processor; wherein,

[0071] The memory stores a computer program that can be executed by at least one processor. The computer program is executed by at least one processor so that the at least one processor can execute the wafer cutting method described in any embodiment of the present invention.

[0072] The wafer cutting device provided by the technical solution of the embodiment of the present invention and the wafer cutting method described in any embodiment of the present invention have the same beneficial effects.

[0073] An embodiment of the present invention provides a computer-readable storage medium based on the above embodiments. The computer-readable storage medium stores computer instructions. The computer instructions are used to enable a processor to implement the wafer cutting method described in any embodiment of the present invention when executed.

[0074] A computer-readable storage medium provided by the technical solution of an embodiment of the present invention has the same beneficial effects as the wafer cutting method described in any embodiment of the present invention.

[0075] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0076] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A wafer cutting method, characterized in that: include: Provide wafers; The wafer comprises a functional area and a test area; the functional area surrounds the test area, the test area comprises a central area and an edge area, the edge area surrounds the central area; the edge area of ​​the test area is a pure silicon layer; Determine a plurality of scribing lanes of the wafer; the plurality of scribing lanes include a plurality of first scribing lanes and a plurality of second scribing lanes; the first scribing lanes are located at edge areas of the functional area and the test area, and the second scribing lanes are located at a central area of ​​the test area; Performing a first cutting on the plurality of second dicing streets to a preset depth; The plurality of first dicing streets and the plurality of second dicing streets after dicing are cut for a second time.

2. The wafer cutting method according to claim 1, characterized in that: The plurality of second dicing streets are cut for the first time to a preset depth, comprising: The plurality of second scribe lines are cut to a preset depth for the first time by using a laser grooving process.

3. The wafer cutting method according to claim 1, characterized in that: Performing a second cutting on the plurality of first dicing streets and the plurality of second dicing streets after cutting, comprising: The plurality of first scribe lines and the plurality of second scribe lines that have been cut are cut for a second time using a plasma scribe process.

4. The wafer cutting method according to claim 1, characterized in that: The width of the first scribe line is less than or equal to 25 μm.

5. The wafer cutting method according to claim 1, characterized in that: The plurality of first scribing lanes and the plurality of second scribing lanes each include a plurality of transverse scribing lanes and a plurality of longitudinal scribing lanes; each of the transverse scribing lanes extends along a first direction, and the plurality of transverse scribing lanes are arranged along a second direction; each of the longitudinal scribing lanes extends along the second direction, and the plurality of longitudinal scribing lanes are arranged along the first direction; the first direction and the second direction are perpendicular to each other; Each transverse scribe line of the second scribe line is located on the same straight line as one of the first scribe lines; each longitudinal scribe line of the second scribe line is located on the same straight line as one of the first scribe lines.

6. The wafer cutting method according to claim 5, characterized in that: The plurality of second dicing streets are cut for the first time to a preset depth, comprising: Performing a first cutting on the plurality of transverse scribe lines of the second scribe line to a preset depth; After the dicing of the plurality of transverse dicing streets is completed, the plurality of longitudinal dicing streets of the second dicing street are cut for the first time to a preset depth.

7. The wafer cutting method according to claim 5, characterized in that: Performing a second cutting on the plurality of first dicing streets and the plurality of second dicing streets after cutting, comprising: Simultaneously performing a second cutting on the plurality of transverse scribe lines of the plurality of first scribe lines and the plurality of transverse scribe lines of the plurality of second scribe lines after cutting; After the cutting of the plurality of transverse scribe lines of the plurality of first scribe lines and the plurality of transverse scribe lines of the plurality of second scribe lines is completed, the plurality of longitudinal scribe lines of the plurality of first scribe lines and the plurality of longitudinal scribe lines of the plurality of second scribe lines are cut for a second time.

8. A chip, characterized in that: Obtained by the wafer cutting method according to any one of claims 1 to 7.

9. A wafer cutting device, characterized in that: The wafer cutting equipment comprises: at least one processor; and a memory in communication with the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the wafer cutting method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the wafer cutting method according to any one of claims 1 to 7 when executed.

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