Insulated gate bipolar transistor and preparation method thereof

Abstract

The invention discloses an insulated gate bipolar transistor and a preparation method thereof, the insulated gate bipolar transistor comprises a gate bus area, a built-in gate resistor area and a gate lead area, the built-in gate resistor area comprises a plurality of built-in gate resistor units, each built-in gate resistor unit is connected with the gate bus area, and the built-in gate resistor area is connected with the gate lead area. The grid lead area is connected with the grid lead area and at least one built-in grid resistor unit through an internal resistance lead; and the built-in gate resistors of the built-in gate resistor regions are adjusted through the number of the internal resistance leads and the number of the built-in gate resistor regions. The gate resistor unit comprises a plurality of gate resistor grooves, first metal and a first lead area, the first lead area is arranged on the first metal, and the first metal is connected with the gate bus area through the gate resistor grooves. By adjusting the number of the built-in gate resistor units connected with the gate lead area, the built-in gate resistors can be adjusted on the premise that plate making and tape-out are not carried out again, and time and cost are saved in the product research and development stage.

Description

Technical Field

[0001] The present invention relates to transistors and methods for making the same, and in particular to an insulated gate bipolar transistor and a method for making the same. Background Art

[0002] Insulated gate bipolar transistor (IGBT) is a new type of power electronic device that is a composite of MOS field effect transistor and bipolar transistor. It has the advantages of MOSFET, which is easy to drive and simple to control, and the advantages of power transistor, which is low on-voltage, large on-state current and low loss. It has become one of the core electronic components in modern power electronic circuits.

[0003] For photovoltaic new energy high-power application solutions with voltages above 1200V and currents above 450A, the chips in the IGBT modules need built-in gate resistors. In order to better cooperate with the specific overall solution, the resistance value of the built-in gate resistor needs to be customized according to the application test waveform and other test parameters. In the actual IGBT tape-out, especially in the new product development stage, the built-in gate resistor is usually adjusted multiple times to obtain a built-in gate resistor that meets the application requirements. At present, the mainstream technology of domestic IGBT has developed to the 1.6um platform, and the built-in gate resistor can be introduced by designing the groove layer, contact hole layer and metal layer. Therefore, if the resistance value of the built-in gate resistor is adjusted, the groove layer, contact hole layer and metal layer need to be changed again, and the tape-out is re-made. Therefore, the time period for adjusting the built-in gate resistor is long, the preparation cycle is long, and the R&D cost is high. Summary of the invention

[0004] Purpose of the invention: In order to overcome the deficiencies of the prior art, an object of the present invention is to provide an insulated gate bipolar transistor. Another object of the present invention is to provide a method for preparing an insulated gate bipolar transistor.

[0005] Technical solution: An insulated gate bipolar transistor described in the present invention includes a gate bus area, a built-in gate resistor area and a gate lead area. The built-in gate resistor area includes a plurality of built-in gate resistor units, each of which is connected to the gate bus area. The gate lead area is connected to the gate lead area and at least one built-in gate resistor unit through an internal resistance lead; the built-in gate resistance of the built-in gate resistor area is adjusted by the number of internal resistance leads and the number of built-in gate resistor areas.

[0006] Furthermore, the gate resistor unit includes a plurality of gate resistor trenches, a first metal and a first lead area, the first lead area is arranged on the first metal, and the first metal is connected to the gate bus area through the gate resistor trenches.

[0007] Furthermore, the gate resistor trenches are spaced apart from each other and parallel to each other.

[0008] Furthermore, the length of the gate resistor trench is 10-500 μm, and the number of the gate resistor trench is between 1 and 100.

[0009] Furthermore, the gate resistor trench is filled with polysilicon, and the polysilicon filled in the trench is doped with certain impurities, so that the polysilicon has a certain resistance.

[0010] Furthermore, the polysilicon is electrically connected to the gate bus region through a first contact hole, and is electrically connected to the first metal through a second contact hole.

[0011] Furthermore, the built-in gate resistance units are spaced apart from each other and parallel to each other.

[0012] Furthermore, the gate lead region includes a second metal and a second lead region, the second lead region is arranged on the second metal, and the internal resistance lead is connected to the second lead region and the first lead region.

[0013] Furthermore, the first metal and the second metal are Al, Si or Cu.

[0014] The method for preparing an insulated gate bipolar transistor of the present invention comprises the following steps:

[0015] Step 1, providing a semiconductor substrate and making a terminal ring;

[0016] Step 2: forming an active area;

[0017] Step 3, etching the trench and filling it with polysilicon to form a gate resistor trench;

[0018] Step 4: making a dielectric layer;

[0019] Step 5, etching the contact holes to form a first contact hole and a second contact hole;

[0020] Step 6: fabricate a metal layer to form a gate bus region, a first metal and a second metal;

[0021] Step 7: making a passivation layer to form a first lead area and a lead area;

[0022] Step 8: Back thinning and injection to form a back structure;

[0023] Step 9: Wire bonding, packaging and testing, setting internal resistance leads.

[0024] Beneficial effects: Compared with the prior art, the present invention has the following significant characteristics: the resistance value of the built-in gate resistor can be flexibly adjusted by adjusting the number of built-in gate resistor units connected to the gate lead area, and the built-in gate resistor can be adjusted without re-plate making and re-flowing, saving time and cost in the product development stage. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of the structure of the present invention;

[0026] Figure 2 It is a schematic diagram of a slice of the present invention;

[0027] Figure 3 is a cross-sectional view of the AA surface of the present invention;

[0028] Figure 4 It is a BB-plane cross-sectional view of the present invention;

[0029] Figure 5 It is a CC cross-sectional view of the present invention;

[0030] Figure 6 It is a DD-plane cross-sectional view of the present invention;

[0031] Figure 7 It is a cross-sectional view of the EE plane of the present invention. DETAILED DESCRIPTION

[0032] like Figure 1 , each built-in gate resistance unit 2 of the insulated gate bipolar transistor is directly connected to the gate bus area 1, at least one built-in gate resistance unit 21 is connected to the gate lead area 3 through the internal resistance lead 4, and the built-in gate resistance unit 21 includes a gate resistance groove 211, a first metal 212 and a first lead area 213. The gate resistance groove 211 is connected between the gate bus area 1 and the first metal 212, and the first lead area 213 is arranged on the first metal 212. The first metal 212 is Al, Si or Cu. The gate lead area 3 includes a second metal 31 and a second lead area 32, and the second lead area 32 is arranged on the second metal 31. The second metal 31 is Al, Si or Cu. The gate resistance groove 211 is filled with polysilicon 214, and the polysilicon 214 is electrically connected to the gate bus area 1 through the first contact hole 215, and is electrically connected to the first metal 212 through the second contact hole 216.

[0033] Usually when making power devices, the polysilicon filled in the groove will be doped with certain impurities, so that the polysilicon has a certain resistance. The shape of the gate resistor groove 211 is the same as the chip cell area. The gate resistor groove 211 is 10μm to 500μm long and the number is between 1 and 100. After the resistance value of a single gate resistor groove 211 is determined, the resistance value of the gate resistor unit 211 can be changed by the number of parallel connections. For example, when the single resistance value of the gate resistor groove 211 is 100Ω, after 10 gate resistor grooves 211 are connected in parallel, the overall resistance value of the built-in gate resistor unit 21 is 10Ω.

[0034] The gate electrical signal is transmitted to the gate bus area 1 through one or more built-in gate resistor units 21, so as to form a built-in gate resistor using the resistance of the gate resistor groove 211. The built-in gate resistor units 21 are spaced apart from each other and parallel to each other. The built-in gate resistance is flexibly adjusted by adjusting the number of internal resistance leads 4 connecting the gate lead area 3 and the built-in gate resistor unit 2. For example, when the resistance of each gate resistor groove 211 is 10Ω and the number of internal resistance leads 4 is 1, the built-in gate resistance at this time is 10Ω. When the resistance of each gate resistor groove 211 is 10Ω and the number of internal resistance leads 4 is 2, the built-in gate resistance is 5Ω. When the resistance of each gate resistor groove 211 is 10Ω and the number of internal resistance leads 4 is 4, the built-in gate resistance is about 2.5Ω. The total number of built-in gate resistor units 21 can be adjusted according to actual needs, and the total number is 2 to 10.

[0035] like Figures 2 to 7 The method for manufacturing the insulated gate bipolar transistor of this embodiment comprises the following steps:

[0036] Step 1: Provide a semiconductor substrate 5 and make a terminal ring.

[0037] Step 2: forming an active region.

[0038] Step three: etching the trench and filling it with polysilicon to form a gate resistor trench 211 .

[0039] Step 4: making a dielectric layer 6.

[0040] Step five: etching the contact holes to form the first contact hole 215 and the second contact hole 216 .

[0041] Step six: fabricating a metal layer 7 to form a gate bus region 1 , a first metal 212 and a second metal 31 .

[0042] Step seven: manufacturing a passivation layer 8 to form a first lead region 213 and a second lead region 32 .

[0043] Step 8: Thinning and injection of the back to form the back structure.

[0044] Step nine: wire bonding, packaging and testing to form a certain number of internal resistance leads 4.

Claims

1. An insulated gate bipolar transistor, characterized in that: The invention comprises a gate bus region (1), a built-in gate resistor region (2) and a gate lead region (3); the built-in gate resistor region (2) comprises a plurality of built-in gate resistor units (21), each of the built-in gate resistor units (21) is connected to the gate bus region (1); the gate lead region (3) is connected to the gate lead region (3) and at least one built-in gate resistor unit (21) via an internal resistance lead (4); and the built-in gate resistance of the built-in gate resistor region (2) is adjusted by the number of the internal resistance leads (4) and the number of the built-in gate resistor regions (2).

2. An insulated gate bipolar transistor according to claim 1, characterized in that: The gate resistor unit (21) comprises a plurality of gate resistor grooves (211), a first metal (212) and a first lead area (213); the first lead area (213) is arranged on the first metal (212); and the first metal (212) is connected to the gate bus area (1) through the gate resistor grooves (211).

3. An insulated gate bipolar transistor according to claim 2, characterized in that: The gate resistor trenches (211) are spaced apart from each other and parallel to each other.

4. The insulated gate bipolar transistor according to claim 2, characterized in that: The length of the gate resistance groove (211) is 10 to 500 μm, and the number of the gate resistance groove (211) is between 1 and 100.

5. The insulated gate bipolar transistor according to claim 2, characterized in that: The gate resistor trench (211) is filled with polysilicon (214).

6. The insulated gate bipolar transistor according to claim 5, characterized in that: The polysilicon (214) is electrically connected to the gate bus region (1) through a first contact hole (215), and is electrically connected to the first metal (212) through a second contact hole (216).

7. The insulated gate bipolar transistor according to claim 1, characterized in that: The built-in gate resistance units (21) are spaced apart from each other and are parallel to each other.

8. The insulated gate bipolar transistor according to claim 1, characterized in that: The gate lead area (3) comprises a second metal (31) and a second lead area (32); the second lead area (32) is arranged on the second metal (31); and the internal resistance lead (4) is connected to the second lead area (32) and the first lead area (213).

9. An insulated gate bipolar transistor according to claim 2 or 8, characterized in that: The first metal (212) and the second metal (31) are Al, Si or Cu.

10. The method for preparing an insulated gate bipolar transistor according to any one of claims 1 to 9, characterized in that: The following steps are involved: Step 1, providing a semiconductor substrate (5) and making a terminal ring; Step 2: forming an active area; Step 3, etching the trench and filling it with polysilicon to form a gate resistor trench (211); Step 4: making a dielectric layer (6); Step 5: etching contact holes to form a first contact hole (215) and a second contact hole (216); Step 6: manufacturing a metal layer (7) to form a gate bus region (1), a first metal (212) and a second metal (31); Step 7: manufacturing a passivation layer (8) to form a first lead region (213) and a second lead region (32); Step 8: Back thinning and injection to form a back structure; Step 9: Wire bonding, packaging and testing, setting internal resistance leads (4).

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