Back contact battery and preparation method thereof

Abstract

The invention provides a back contact cell and a preparation method thereof, and the preparation method comprises the following steps: providing a silicon substrate which is provided with a front surface and a back surface which are opposite to each other, growing a tunneling oxide layer on the back surface of the silicon substrate, and depositing a first silicon layer on the tunneling oxide layer; placing the silicon substrate on which the first silicon layer is deposited in diffusion equipment, and then carrying out crystallization treatment on the first silicon layer; after the crystallization treatment is finished, boron doping is carried out on the surface of the first silicon layer to form a p + emitter; and growing an oxide layer on the surface of the p + emitter, so that redundant boron atoms are separated out from the first silicon layer.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a back contact cell and a preparation method thereof. Background Art

[0002] In conventional photovoltaic processes, phosphorus sources are used as dopants in the n+ region, and boron sources are used as dopants in the p+ region. At the same temperature, the solubility and effective diffusion rate of phosphorus in silicon are higher than those of boron, and phosphorus can be activated at lower temperatures. Therefore, the diffusion of phosphorus is easier to control than the diffusion of boron. As a result, the phosphorus-doped n+ region has better passivation performance than the boron-doped p+ emitter, with a passivation open circuit voltage (iV) of more than 730mV. OC ), and the passivation effect of the p+ emitter is far inferior to that of the n+ region. Summary of the invention

[0003] In view of this, the present invention provides a back-contact battery and a preparation method thereof, wherein the preparation method can improve the passivation level of the p+ emitter in the back-contact battery.

[0004] The present invention provides a method for preparing a back contact battery, comprising the following steps:

[0005] Obtaining a silicon substrate, wherein the silicon substrate has a front side and a back side opposite to each other, growing a tunneling oxide layer on the back side of the silicon substrate, and then depositing a first silicon layer on the tunneling oxide layer;

[0006] Placing the silicon substrate on which the first silicon layer is deposited in a diffusion device, and then performing a crystallization process on the first silicon layer;

[0007] After the crystallization process is completed, the first silicon layer is doped with boron to form a p+ emitter;

[0008] An oxide layer is grown on the surface of the p+ emitter to allow excess boron atoms to separate from the first silicon layer.

[0009] Furthermore, the first silicon layer is deposited on the tunnel oxide layer by using an LPCVD process.

[0010] Furthermore, the step of “crystallizing the first silicon layer” includes:

[0011] The diffusion equipment is first heated to 980° C. to 1040° C., and the pressure is maintained at 500 mbar to 600 mbar during the heating process. The temperature is then maintained constant for 20 mins to 40 mins for high temperature crystallization. After the high temperature crystallization is completed, the temperature is lowered to 830° C. to 850° C.

[0012] Furthermore, the deposition temperature of the first silicon layer is 540° C. to 570° C., and the deposition thickness of the first silicon layer is 200 nm to 300 nm.

[0013] Furthermore, "growing a tunneling oxide layer on the back side of the silicon substrate" includes: growing a tunneling oxide layer on the back side of the silicon substrate by thermal oxidation, and the temperature of the thermal oxidation is 580°C to 660°C.

[0014] Furthermore, before the step of "growing a tunnel oxide layer on the back side of the silicon substrate", the silicon substrate is also pre-treated, and the pre-treatment includes cleaning and polishing.

[0015] Furthermore, the method for preparing the back contact battery further comprises:

[0016] After the excess boron atoms are precipitated from the first silicon layer, a SiO2 layer is deposited on the back side of the silicon substrate using a PECVD process.

[0017] Furthermore, the method further comprises: using a laser to open the film on the back of the silicon substrate, and then firstly placing the silicon substrate in an acidic liquid for cleaning, and then placing the silicon substrate in an alkaline liquid for etching.

[0018] Furthermore, it also includes: depositing a second silicon layer on the back side of the silicon substrate using the LPCVD process, doping phosphorus atoms in the second silicon layer, opening the back side of the silicon substrate using a laser, and cleaning and texturing the silicon substrate in an acidic liquid.

[0019] Furthermore, the method further comprises: depositing an aluminum oxide layer and a silicon nitride layer on the silicon substrate, and finally screen printing a metal grid line and sintering.

[0020] The present invention also provides a back contact battery, which is prepared by the above-mentioned preparation method.

[0021] Compared with the prior art, the present invention adds a heating-constant temperature-cooling stage before boron diffusion to crystallize the first silicon layer, so that the amorphous silicon in the first silicon layer is transformed into polycrystalline silicon with a more orderly lattice arrangement, and the compactness of the first silicon layer is improved, thereby improving the passivation effect of the p+ emitter. In conventional processes, the i-Voc of the p+ emitter after boron diffusion is generally around 700mV, and through the preparation method provided by the present invention, the passivation open circuit voltage of the p+ emitter can be optimally increased to 718mV, an increase of 18mV. And the preparation method provided by the present invention is completed in the boron diffusion equipment throughout the process, without the need to use other equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic flow chart of a preparation method according to one embodiment of the present invention. DETAILED DESCRIPTION

[0023] In order to more clearly understand the above-mentioned purposes, features and advantages of the embodiments of the present invention, the present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the features in the embodiments of the present application can be combined with each other without conflict.

[0024] In the following description, many specific details are set forth to facilitate a full understanding of the embodiments of the present invention. The described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the embodiments of the present invention.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the technical field of the embodiments of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific implementation methods and are not intended to limit the embodiments of the present invention.

[0026] In the present invention, LPCVD (Low Pressure Chemical Vapor Deposition, abbreviated as LPCVD) is low-pressure chemical vapor deposition, which is a chemical vapor deposition process performed under relatively low pressure. Its working principle involves introducing gaseous precursors into a reaction chamber under relatively low pressure. These gaseous precursors undergo chemical reactions on the surface of the wafer, thereby depositing the desired thin film.

[0027] In the present invention, PECVD (plasma enhanced chemical vapor deposition, abbreviated as PECVD) is a plasma enhanced chemical vapor deposition method, which utilizes the reaction of laughing gas (N2O) and monosilane (SiH4) to deposit a nitride oxide film at a low temperature, which contains both hydrogen and nitrogen, and can passivate surface defects of the silicon substrate to achieve chemical passivation.

[0028] See also Figure 1 In one embodiment of the present application, a method for preparing a back contact battery is provided, which comprises the following steps:

[0029] Providing a silicon substrate, wherein the silicon substrate has a front side and a back side opposite to each other, growing a tunnel oxide layer on the back side of the silicon substrate, and then depositing a first silicon layer on the tunnel oxide layer;

[0030] Placing the silicon substrate with the first silicon layer deposited thereon in a diffusion device, filling the diffusion device with an inert gas, and then performing a crystallization process on the first silicon layer;

[0031] After the crystallization process is completed, the first silicon layer is doped with boron to form a p+ emitter;

[0032] An oxide layer is grown on the surface of the p+ emitter to cause excess boron atoms to precipitate from the first silicon layer.

[0033] In some embodiments, the selected silicon substrate is an N-type silicon substrate.

[0034] In some embodiments, before the step of "growing a tunneling oxide layer on the back side of the silicon substrate", the silicon substrate is also pretreated, and the pretreatment includes cleaning and polishing the surface of the silicon substrate. For example, the silicon substrate is first immersed in deionized water to remove large particles on the surface, and a cleaning agent such as an organic solvent or a surfactant is used to immerse the silicon substrate in the cleaning agent. During the cleaning process, mechanical stirring or ultrasound can be used to promote the removal of contaminants, and then the silicon substrate is placed in a polishing machine for polishing. There are a lot of cutting damage and metal residues on the surface of the silicon substrate. These large number of defects and composite centers will cause low efficiency of the battery cell. Therefore, the battery will be cleaned before production to eliminate these composite centers. In addition, in order to ensure the uniformity of polysilicon, double-sided polishing will be performed.

[0035] In some embodiments, the specific method of "growing a tunneling oxide layer on the back side of the silicon substrate" includes: growing a tunneling oxide layer on the back side of the silicon substrate by thermal oxidation, the thermal oxidation temperature is 580°C to 660°C, and the pressure is normal pressure or -700mbar to -900mbar.

[0036] In some embodiments, the first silicon layer is deposited on the tunnel oxide layer using an LPCVD process.

[0037] In some embodiments, the deposition temperature of the first silicon layer is 540°C to 570°C, and the deposition thickness of the first silicon layer is 200nm to 300nm. Within the above temperature range, it is beneficial for the first silicon layer to be deposited better, and after high-temperature crystallization, neatly arranged polysilicon will be better formed, thereby improving the passivation level of the p+ emitter; the thickness of the first silicon layer is controlled within the above range, so that the first silicon layer has better toughness in the subsequent boron source doping step and is not easily pushed through, thereby ensuring the uniformity of the polysilicon layer after high-temperature crystallization, so as to further improve the passivation level of the p+ emitter, and enable the final back contact battery to have a lower resistance, thereby improving the passivation open circuit voltage and battery efficiency of the battery.

[0038] In some embodiments, the diffusion equipment is a boron diffuser.

[0039] In some embodiments, in the step of "filling the diffusion device with an inert gas", the inert gas is one of nitrogen, argon or helium.

[0040] In some embodiments, the step of "crystallizing the first silicon layer" includes: first heating the diffusion equipment to 980°C to 1040°C to reach the temperature required for high-temperature crystallization, maintaining the pressure at 500mbar to 600mbar during the heating process to balance the pressure and temperature in the diffusion equipment, then maintaining the temperature unchanged for 20mins to 40mins for high-temperature crystallization, and then cooling to 830°C to 850°C after the high-temperature crystallization is completed to prepare for the deposition of the boron source.

[0041] The first silicon layer deposited on the surface of the silicon substrate after the LPCVD process is in an amorphous silicon state. The heating-constant temperature-cooling process before depositing the boron source can crystallize the amorphous silicon deposited by LPCVD. The high temperature can transform the amorphous silicon into polycrystalline silicon with a neater lattice arrangement. The first silicon layer after crystallization will become denser, and the defects and recombination centers in the first silicon layer will be reduced, which can improve the passivation level of the battery emitter.

[0042] In some embodiments, the boron source includes, but is not limited to, boron trichloride, boron tribromide, trimethylboron, or ethylenediborane.

[0043] In some embodiments, the method for preparing the back-contact cell further includes: after the excess boron atoms are precipitated from the first silicon layer, depositing a SiO2 layer on the back side of the silicon substrate using a PECVD process to protect the P region.

[0044] In some embodiments, the preparation method of the above-mentioned back-contact battery also includes: using a laser to pattern the back side of the silicon substrate to open the film, etching the SiO2 layer and borosilicate glass (BSG) on the back side, and then placing the silicon substrate in an acidic liquid for cleaning, and then corroding it in an alkaline liquid to remove the BSG layer and the expansion layer generated on the front side of the silicon substrate during the boron diffusion process, and etching the N region on the back side of the silicon substrate.

[0045] In some embodiments, the preparation method of the above-mentioned back-contact battery also includes: using the LPCVD process to deposit a second silicon layer on the back side of the silicon substrate, and doping phosphorus atoms in the second silicon layer to make it an n+ back field, and then using a laser to pattern the P area and the gap area to open the film, and placing the silicon substrate in an acidic liquid for cleaning and then texturing.

[0046] In some embodiments, the method for preparing the above-mentioned back-contact battery also includes: depositing an aluminum oxide layer and a silicon nitride layer on the front and back sides of the silicon substrate for further surface passivation treatment, and finally screen-printing metal grid lines and sintering the silicon substrate.

[0047] The present invention also provides a back-contact battery prepared by the above-mentioned preparation method, wherein the back-contact battery comprises: a silicon substrate, a p+ emitter, an n+ back field and an n+ front surface field, wherein the p+ emitter and the n+ back field are located on one side of the silicon substrate, and the n+ front surface field is located on the side of the silicon substrate away from the p+ emitter and the n+ back field, the p+ emitter comprises a tunneling oxide layer and a first silicon layer doped with boron atoms, and the tunneling oxide layer and the first silicon layer doped with boron atoms are sequentially stacked on the silicon substrate, the n+ back field comprises a second silicon layer doped with phosphorus atoms, and the n+ front surface field comprises a silicon nitride layer and an aluminum oxide layer, and the silicon nitride layer and the aluminum oxide layer are sequentially stacked on the side of the silicon substrate away from the p+ emitter.

[0048] Some specific embodiments and comparative examples are listed below to illustrate the technical solution of the present application.

[0049] Example 1

[0050] Step S1: providing an N-type silicon substrate, wherein the silicon substrate has a front side and a back side opposite to each other, and pre-treating the front side and the back side of the silicon substrate, wherein the pre-treating comprises cleaning and polishing the front side and the back side of the silicon substrate;

[0051] Step S2-1: The pre-treated silicon substrate is subjected to a thermal oxidation process to grow a tunneling oxide layer (SiO2) with a thickness of 2 nm on the back side of the silicon substrate. The temperature of the thermal oxidation process is 580° C. and the pressure is normal pressure.

[0052] Step S2-2: Then, a first silicon layer is deposited on the tunnel oxide layer using the LPCVD process. The first silicon layer is an amorphous silicon film. The deposition temperature is 540° C. and the thickness of the amorphous silicon film is 200 nm.

[0053] Step S3-1: placing the silicon substrate into a furnace tube, the initial standby temperature of the furnace tube is 800° C., and the air in the furnace tube is evacuated to form a nitrogen atmosphere;

[0054] Step S3-2:

[0055] Heating: Raise the temperature of the furnace tube to 980°C to prepare for the crystallization temperature. During the heating process, nitrogen is continuously introduced to maintain a pressure of 600 mbar.

[0056] Constant temperature: Maintain a constant temperature of 980°C to crystallize the amorphous silicon film for 20 minutes;

[0057] Cooling: After high-temperature crystallization, the amorphous silicon film is transformed into a polycrystalline silicon film and cooled down to 830°C to prepare for the deposition of the boron source;

[0058] Step S4: depositing boron trichloride on the surface of the first silicon layer after the silicon substrate has been crystallized, that is, on the surface of the polycrystalline silicon film;

[0059] Step S5: doping boron atoms in boron trichloride into the polysilicon film at 940° C. to form a p+ emitter, with a doping time of 3200 s;

[0060] Step S6: using oxygen to grow an oxide layer on the surface of the polysilicon film doped with boron atoms, so that excess boron atoms are precipitated from the polysilicon film on the silicon substrate to form BSG (borosilicate glass);

[0061] Step S7: cooling down, and taking out the silicon substrate with the polycrystalline silicon film doped with boron atoms;

[0062] Step S8: using a PECVD process to deposit a SiO2 layer on the back side of the silicon substrate to protect the P region;

[0063] Step S9: using a laser to open the back of the silicon substrate to etch the mask and BSG on the N region, then firstly placing the silicon substrate in chain hydrofluoric acid for cleaning, and then performing a tank alkali polishing to remove the BSG layer and the wrap-around layer generated on the front of the silicon substrate during the boron diffusion process, and etching the N region on the back of the silicon substrate;

[0064] Step S10: using LPCVD process to deposit a polysilicon film on the back side of the silicon substrate, with a thickness of about 250 nm;

[0065] Step S11: doping phosphorus atoms into the polysilicon film deposited on the back side to make it an n+ back field;

[0066] Step S12: using a laser device to perform film opening treatment on PSG (phosphosilicate glass) in the P region and the gap (groove) region;

[0067] Step S13: Wash off the PSG in the front and back P areas and the gap area, and remove the plating area and the suede surface made on the front side;

[0068] Step S14: coating aluminum oxide film and silicon nitride film on both sides of the silicon substrate;

[0069] Step S15: screen printing metal grid lines and sintering.

[0070] Example 2

[0071] Step S1: providing an N-type silicon substrate, wherein the silicon substrate has a front side and a back side opposite to each other, and pre-treating the front side and the back side of the silicon substrate, wherein the pre-treating comprises cleaning and polishing the front side and the back side of the silicon substrate;

[0072] Step S2-1: The pre-treated silicon substrate is subjected to a thermal oxidation process to grow a tunneling oxide layer (SiO2) with a thickness of 2 nm on the back side of the silicon substrate. The temperature of the thermal oxidation process is 620° C. and the pressure is −700 mbar.

[0073] Step S2-2: Then, a first silicon layer is deposited on the tunnel oxide layer using the LPCVD process. The first silicon layer is an amorphous silicon film. The deposition temperature is 560° C. and the thickness of the amorphous silicon film is 250 nm.

[0074] Step S3-1: placing the silicon substrate into a furnace tube, the initial standby temperature of the furnace tube is 850° C., and the air in the furnace tube is evacuated to form a nitrogen atmosphere;

[0075] Step S3-2:

[0076] Heating: Raise the temperature of the furnace tube to 1040°C to prepare for the crystallization temperature. During the heating process, nitrogen is continuously introduced to maintain a pressure of 600 mbar.

[0077] Constant temperature: Maintain a constant temperature of 1040°C to perform high-temperature crystallization on the amorphous silicon film for 30 minutes;

[0078] Cooling: After high-temperature crystallization, the amorphous silicon film is transformed into a polycrystalline silicon film and cooled down to 840°C to prepare for the deposition of the boron source;

[0079] Step S4: depositing boron trichloride on the surface of the first silicon layer after the silicon substrate has been crystallized, that is, on the surface of the polycrystalline silicon film;

[0080] Step S5: doping boron atoms in boron trichloride into the polysilicon film of the silicon substrate at 940° C. to form a p+ emitter, with a doping time of 3200 s;

[0081] Step S6: using oxygen to grow an oxide layer on the surface of the polysilicon film doped with boron atoms, so that excess boron atoms are precipitated from the polysilicon film on the silicon substrate to form BSG (borosilicate glass);

[0082] Step S7: cooling down, and taking out the silicon substrate with the polycrystalline silicon film doped with boron atoms;

[0083] Step S8: using a PECVD process to deposit a SiO2 layer on the back side of the silicon substrate to protect the P region;

[0084] Step S9: using a laser to open the back of the silicon substrate to etch the mask and BSG on the N region, then firstly placing the silicon substrate in chain hydrofluoric acid for cleaning, and then performing a tank alkali polishing to remove the BSG layer and the wrap-around layer generated on the front of the silicon substrate during the boron diffusion process, and etching the N region on the back of the silicon substrate;

[0085] Step S10: using LPCVD process to deposit a polysilicon film on the back side of the silicon substrate, with a thickness of about 250 nm;

[0086] Step S11: doping phosphorus atoms into the polysilicon film deposited on the back side to make it an n+ back field;

[0087] Step S12: using a laser device to perform film opening treatment on PSG (phosphosilicate glass) in the P region and the gap (groove) region;

[0088] Step S13: Wash off the PSG in the front and back P areas and the gap area, and remove the plating area and the suede surface made on the front side;

[0089] Step S14: coating aluminum oxide film and silicon nitride film on both sides of the silicon substrate;

[0090] Step S15: screen printing metal grid lines and sintering.

[0091] Example 3

[0092] Step S1: providing an N-type silicon substrate, wherein the silicon substrate has a front side and a back side opposite to each other, and pre-treating the front side and the back side of the silicon substrate, wherein the pre-treating comprises cleaning and polishing both sides of the silicon substrate;

[0093] Step S2-1: The pre-treated silicon substrate is subjected to a thermal oxidation process to grow a tunneling oxide layer (SiO2) with a thickness of 2 nm on the back side of the silicon substrate. The temperature of the thermal oxidation process is 660° C. and the pressure is −900 mbar.

[0094] Step S2-2: Then, a first silicon layer is deposited on the tunnel oxide layer using the LPCVD process. The first silicon layer is an amorphous silicon film. The deposition temperature is 570° C. and the thickness of the amorphous silicon film is 300 nm.

[0095] Step S3-1: placing the silicon substrate into a furnace tube, the initial standby temperature of the furnace tube is 800° C., and the air in the furnace tube is evacuated to form a nitrogen atmosphere;

[0096] Step S3-2:

[0097] Heating: Raise the temperature of the furnace tube to 1020°C to prepare for the crystallization temperature. During the heating process, nitrogen is continuously introduced to maintain a pressure of 600 mbar.

[0098] Constant temperature: Maintain a constant temperature of 1020°C to perform high-temperature crystallization on the amorphous silicon film for 40 minutes;

[0099] Cooling: After high-temperature crystallization, the amorphous silicon film is transformed into a polycrystalline silicon film and cooled down to 830°C to prepare for the deposition of the boron source;

[0100] Step S4: depositing boron trichloride on the surface of the first silicon layer after the silicon substrate has been crystallized, that is, on the surface of the polycrystalline silicon film;

[0101] Step S5: doping boron atoms in boron trichloride into the polysilicon film of the silicon substrate at 940° C. to form a p+ emitter, with a doping time of 3200 s;

[0102] Step S6: using oxygen to grow an oxide layer on the surface of the polycrystalline silicon film doped with boron atoms, so that excess boron atoms are precipitated from the polycrystalline silicon film on the silicon substrate to form BSG (borosilicate glass);

[0103] Step S7: cooling down, and taking out the silicon substrate with the polycrystalline silicon film doped with boron atoms;

[0104] Step S8: using a PECVD process to deposit a SiO2 layer on the back side of the silicon substrate to protect the P region;

[0105] Step S9: using a laser to open the back side of the silicon substrate to etch the mask and BSG on the N region, then cleaning the silicon substrate in chain hydrofluoric acid, and then performing a tank alkali polishing to remove the BSG layer and the wrapping on the front side, and etching the N region on the back side;

[0106] Step S10: using LPCVD process to deposit a polysilicon film on the back side of the silicon substrate, with a thickness of about 250 nm;

[0107] Step S11: doping phosphorus atoms into the polysilicon film deposited on the back side to make it an N region;

[0108] Step S12: using a laser device to perform film opening treatment on PSG (phosphosilicate glass) in the P region and the gap (groove) region;

[0109] Step S13: Wash off the PSG in the front and back P areas and the gap area, and remove the wrap-around plating and the suede surface made on the front side;

[0110] Step S14: coating aluminum oxide film and silicon nitride film on both sides of the silicon substrate;

[0111] Step S15: screen printing metal grid lines and sintering.

[0112] Example 4

[0113] The only difference between Example 4 and Example 1 is that the constant temperature time of Example 4 is 10 minutes.

[0114] Example 5

[0115] The only difference between Example 5 and Example 1 is that in step S2-2 of Example 5, the deposition temperature is 500° C., and the rest of the preparation methods and parameters are consistent with those of Example 1.

[0116] Example 6

[0117] The only difference between Example 6 and Example 1 is that in step S2-2 of Example 6, the deposition temperature is 620° C., and the rest of the preparation methods and parameters are consistent with those of Example 1.

[0118] Example 7

[0119] The only difference between Example 7 and Example 1 is that in step S2-2 of Example 7, the deposition thickness is 150 nm, and the rest of the preparation methods and parameters are consistent with those of Example 1.

[0120] Example 8

[0121] The only difference between Example 8 and Example 1 is that in step S2-2 of Example 8, the deposition thickness is 400 nm, and the rest of the preparation methods and parameters are consistent with those of Example 1.

[0122] Comparative Example 1

[0123] Compared with Example 1, the only difference is that in step S2-2 of Comparative Example 1, there is no heating-constant temperature-cooling stage, and the rest of the preparation method and parameters are consistent with Example 1.

[0124] <Testing Equipment>

[0125] Passivation open circuit voltage (iV OC ): Minority Carrier Lifetime Tester, model WCT-120.

[0126] Battery efficiency: Autevi battery efficiency sorting machine.

[0127] The above-mentioned instruments were used to test the passivation open circuit voltage and battery efficiency of Examples 1 to 8 and Comparative Example 1, respectively.

[0128] <Test Results>

[0129] Table 1 shows the test results of Examples 1 to 8 and Comparative Example 1.

[0130] Table 1.

[0131]

[0132]

[0133] It can be seen from the above table that, compared with the comparative example, each embodiment adds a crystallization treatment to the silicon layer before depositing the boron source in the boron diffusion process, which can effectively increase the density of the P-region silicon layer, thereby improving the passivation open circuit voltage of the p+ emitter and the battery efficiency.

[0134] It can be seen from the data results of Example 1 and Example 4 that in the crystallization process of Example 4, the constant temperature time is insufficient and the degree of transformation of the amorphous silicon film into polycrystalline silicon is low, resulting in low passivation open circuit voltage and battery efficiency of Example 4.

[0135] It can be seen from the data results of Example 1 and Example 5 that the deposition temperature of the first silicon layer in Example 5 is too low, and the deposition effect of the amorphous silicon film is poor, which affects its subsequent conversion to a polycrystalline silicon film and further affects the passivation open circuit voltage.

[0136] It can be seen from the data results of Example 1 and Example 6 that the deposition temperature of the first silicon layer in Example 6 is too high, which will also affect the deposition effect of the amorphous silicon film, thereby affecting the passivation open circuit voltage of Example 6.

[0137] It can be seen from the data results of Example 1 and Example 7 that the deposition thickness of the first silicon layer in Example 7 is too thin, resulting in the polysilicon film being too thin after crystallization, which is easily pushed through in the subsequent boron diffusion process, thereby affecting the passivation open circuit voltage and battery efficiency.

[0138] It can be seen from the data results of Example 1 and Example 8 that the deposition thickness of the first silicon layer in Example 8 is too thick, resulting in a large resistance of Example 8, and thus the passivation open circuit voltage and battery efficiency of Example 8 are low.

[0139] It can be seen from the data results of Comparative Example 1 and Example 1 that Comparative Example 1 has not undergone crystallization treatment, and its passivation open circuit voltage and battery efficiency are poor.

[0140] The above implementation modes are only used to illustrate the technical solutions of the embodiments of the present invention and are not intended to limit the present invention. Although the embodiments of the present invention are described in detail with reference to the above preferred implementation modes, those skilled in the art should understand that the technical solutions of the embodiments of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing a back contact battery, characterized in that: The following steps are involved: Providing a silicon substrate, wherein the silicon substrate has a front side and a back side opposite to each other, growing a tunnel oxide layer on the back side of the silicon substrate, and then depositing a first silicon layer on the tunnel oxide layer; Placing the silicon substrate on which the first silicon layer is deposited in a diffusion device, and then performing a crystallization process on the first silicon layer; After the crystallization process is completed, the first silicon layer is doped with boron to form a p+ emitter; An oxide layer is grown on the surface of the p+ emitter to allow excess boron atoms to separate from the first silicon layer.

2. The method for preparing a back contact battery according to claim 1, characterized in that: The first silicon layer is deposited on the tunnel oxide layer by using an LPCVD process.

3. The method for preparing a back contact battery according to claim 1, characterized in that: The step of “crystallizing the first silicon layer” comprises: The diffusion equipment is first heated to 980° C. to 1040° C., and the pressure is maintained at 500 mbar to 600 mbar during the heating process. The temperature is then maintained constant for 20 mins to 40 mins for high temperature crystallization. After the high temperature crystallization is completed, the temperature is lowered to 830° C. to 850° C.

4. The method for preparing a back contact battery according to claim 1, characterized in that: The deposition temperature of the first silicon layer is 540° C. to 570° C., and the deposition thickness of the first silicon layer is 200 nm to 300 nm.

5. The method for preparing a back contact battery according to claim 1, characterized in that: "Growing a tunneling oxide layer on the back side of the silicon substrate" includes: growing a tunneling oxide layer on the back side of the silicon substrate by thermal oxidation, wherein the temperature of the thermal oxidation is 580°C to 660°C.

6. The method for preparing a back contact battery according to claim 1, characterized in that: Before the step of "growing a tunneling oxide layer on the back side of the silicon substrate", the silicon substrate is also pre-treated, and the pre-treatment includes cleaning and polishing.

7. The method for preparing a back contact battery according to claim 1, characterized in that: Also includes: After the excess boron atoms are precipitated from the first silicon layer, a SiO2 layer is deposited on the back side of the silicon substrate using a PECVD process.

8. The method for preparing a back contact battery according to claim 7, characterized in that: Also includes: The back side of the silicon substrate is opened by laser, and then the silicon substrate is firstly placed in an acidic liquid for cleaning and then placed in an alkaline liquid for etching.

9. The method for preparing a back contact battery according to claim 8, characterized in that: Also includes: A second silicon layer is deposited on the back side of the silicon substrate by using the LPCVD process, and phosphorus atoms are doped in the second silicon layer. The back side of the silicon substrate is opened by using a laser, and the silicon substrate is cleaned in an acidic liquid and then textured.

10. The method for preparing a back contact battery according to claim 9, characterized in that: Also includes: An aluminum oxide layer and a silicon nitride layer are deposited on the silicon substrate, and finally metal grid lines are screen-printed and sintered.

11. A back contact battery, characterized in that: The back contact cell is prepared by the preparation method according to any one of claims 1 to 10.

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