High-precision self-locking oscillator circuit
By introducing a self-locking control mechanism in the oscillator circuit, the frequency-dividing clock signal is used to generate control voltage and current, the problem of existing oscillators being easily disturbed during high-frequency output is solved, and high accuracy, stability and cost reduction are achieved effect.
Patent Information
- Application Number
- CN202411357026.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-27
- Publication Date
- 2024-12-27
AI Technical Summary
Existing oscillators are susceptible to temperature and power interference when outputting high-frequency clock signals and require additional reference frequency or reference voltage, lacking a high-precision oscillator circuit that is not affected by these.
A high-precision self-locking oscillator circuit is designed, including a control voltage generation unit, a current source unit, a clock signal generation unit and a frequency divider unit. By generating control voltage and control current through the frequency divider clock signal, self-locking control is realized. Ensure that the clock signal is positively correlated with the control current and does not require an external reference frequency or reference voltage.
The output of high-precision, high-frequency clock signals is realized, and the stability is not affected by temperature and power supply, reducing costs and no additional auxiliary signal input is required.
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Figure CN119210348A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of oscillator circuits, and in particular to a high-precision self-locking oscillator circuit. Background Art
[0002] In the IC field, the oscillator is an important component of the chip, which is used to provide clock signals to other circuit modules in the chip, such as CPU, ROM and bus communication modules. During the use of the oscillator, the stability and frequency of the clock signal it generates are crucial to the oscillator.
[0003] The mainstream oscillators currently include ring oscillators, relaxation oscillators, and phase-locked loops. Among them:
[0004] In actual use, the ring oscillator has the advantages of simple structure and high output frequency, but it is easily affected by temperature and power supply and has poor accuracy.
[0005] Although the relaxation oscillator is not easily affected by temperature and power supply in actual use and has high accuracy, the oscillator frequency is affected by the delay of the comparator, and its actual flip point will deviate from the designed theoretical flip point. The higher the frequency, the greater the impact. Therefore, the relaxation oscillator cannot output a higher frequency and is generally used in low-speed oscillator applications.
[0006] Although the phase-locked loop can output a very high-frequency clock signal in actual use, and the output frequency is not easily affected by temperature and power supply, it requires a precise reference frequency. Currently, a crystal oscillator is commonly used to provide the reference frequency, which greatly increases the cost.
[0007] Combining the advantages and disadvantages of the above three oscillators, there is currently a lack of an oscillator circuit that can output a higher frequency, whose generated clock signal is not easily affected by temperature and power supply, and does not require additional input of any auxiliary signals such as reference frequency or reference voltage. Summary of the invention
[0008] In view of the shortcomings of the background technology, the present invention provides a high-precision self-locking oscillator circuit. The technical problem to be solved is that there is currently a lack of an oscillator circuit that can output a higher frequency, whose generated clock signal is not easily affected by temperature and power supply, and does not require additional input of any auxiliary signals such as reference frequency or reference voltage.
[0009] In order to solve the above technical problems, the present invention provides the following technical solutions: a high-precision self-locking oscillator circuit, comprising a control voltage generating unit, a current source unit, a clock signal generating unit and a frequency divider unit;
[0010] The frequency divider unit is electrically connected to the clock signal generating unit, divides the frequency of the clock signal output by the clock signal generating unit, and outputs a frequency-divided clock signal;
[0011] The control voltage generating unit is electrically connected to the frequency divider unit and generates a control voltage based on the frequency-divided clock signal;
[0012] The current source unit is electrically connected to the control voltage generating unit, and generates a control current based on the control voltage;
[0013] The clock signal generating unit is electrically connected to the current source unit, and generates the clock signal based on the control current. The clock signal is positively correlated with the control current.
[0014] In a certain embodiment, the control voltage generating unit includes a control clock generating unit, a MOS transistor P1, a MOS transistor N1, a MOS transistor N2, a capacitor C1 and a capacitor C2;
[0015] The control clock generating unit generates a control clock signal CK1, a control clock signal CK2 and a control clock signal CK3 based on the divided clock signal;
[0016] The frequencies of the control clock signal CK1, the control clock signal CK2 and the control clock signal CK3 are all the same as the frequency of the divided clock signal; the waveform of the control clock signal CK1 is opposite to that of the divided clock signal;
[0017] The rising edge timing of the control clock signal CK1 is the same as the rising edge timing of the control clock signal CK2, and the falling edge timing of the control clock signal CK2 is the same as the rising edge timing of the control clock signal CK3; in the same cycle, the sum of the high level time of the control clock signal CK2 and the high level time of the control clock signal CK3 is the same as the high level time of the control clock signal CK1;
[0018] The source of the MOS transistor P1 is used to input the current I2, the gate of the MOS transistor P1 is used to input the control clock signal CK1, the drain of the MOS transistor P1 is electrically connected to the drain of the MOS transistor N1, one end of the capacitor C1 and the source of the MOS transistor N2 respectively, the other end of the capacitor C1 is grounded, the gate of the MOS transistor N3 is used to input the control clock signal CK3, the gate of the MOS transistor N2 is used to input the control clock signal CK2, and the drain of the MOS transistor N2 is grounded through the capacitor C2 for outputting the control voltage.
[0019] In a certain embodiment, the control clock generating unit includes a delay unit, an inverter INVN1, an XOR gate XOR1, an OR gate OR1, a first D flip-flop D1 and an AND gate AND1;
[0020] The input end of the inverter INV1 is electrically connected to the first input end of the XOR gate XOR1, the input end of the delay unit and the first input end of the OR gate OR1 respectively, and is used to input the divided clock signal;
[0021] The output end of the inverter INV1 is electrically connected to the D input end of the first D flip-flop D1 and the first input end of the AND gate AND1 respectively, for outputting the control clock signal CK1;
[0022] The output end of the delay unit is electrically connected to the second input end of the XOR gate XOR1; the output end of the XOR gate XOR1 is electrically connected to the second input end of the OR gate OR1 and the clock input end of the first D flip-flop D1 respectively; the output end of the OR gate OR1 is used to output the control clock signal CK2; the QN output end of the first D flip-flop D1 is electrically connected to the second input end of the AND gate AND1, and the output end of the AND gate AND1 outputs the control clock signal CK3.
[0023] In some implementations, the capacitance of the capacitor C1 is greater than the capacitance of the capacitor C2.
[0024] In a certain embodiment, the current source unit includes an operational amplifier OP, a MOS tube N3, a resistor R and a first current mirror unit, the positive input end of the operational amplifier OP is used to input the control voltage, the negative input end of the operational amplifier OP is electrically connected to the source of the MOS tube N3 and one end of the resistor R respectively, the other end of the resistor R is grounded, and the output end of the operational amplifier OP is electrically connected to the gate of the MOS tube N3; the first current mirror unit is electrically connected to the drain of the MOS tube N3, and generates the control current and the current I2 based on the current flowing through the resistor R.
[0025] In a certain embodiment, the first current mirror unit includes a MOS transistor P2, a MOS transistor P3 and a MOS transistor P4; the source of the MOS transistor P2, the source of the MOS transistor P3 and the source of the MOS transistor P4 are all used to be electrically connected to the power supply vdd, the gate of the MOS transistor P2 is respectively electrically connected to the drain of the MOS transistor P2, the drain of the MOS transistor N3, the gate of the MOS transistor P3 and the gate of the MOS transistor P4, the drain of the MOS transistor P3 is used to output the control current, and the drain of the MOS transistor P4 is used to output the current I2.
[0026] In a certain implementation manner, the clock signal generating unit includes a second current mirror unit, a ring oscillator, a MOS transistor P12, a MOS transistor P13, a MOS transistor N9, a MOS transistor N10 and a buffer;
[0027] The second current mirror unit provides a driving current for each inverter of the ring oscillator based on the control current; the output end of the tail inverter of the ring oscillator is electrically connected to the gate of the MOS tube N9, the input end of the tail inverter is electrically connected to the gate of the MOS tube N10, and the source of the MOS tube N9 and the source of the MOS tube N10 are both grounded; the drain of the MOS tube N9 is electrically connected to the drain of the MOS tube P12 and the gate of the MOS tube P13 respectively, the drain of the MOS tube N10 is electrically connected to the drain of the MOS tube P13, the gate of the MOS tube P12 and the input end of the buffer buffer respectively, the output end of the buffer buffer is used to output the clock signal, and the source of the MOS tube P12 and the source of the MOS tube P13 are used to be electrically connected to the power supply vdd.
[0028] In certain embodiments, the ring oscillator includes three inverters.
[0029] In some implementation manner, the second current mirror unit includes a MOS transistor N4, a MOS transistor N5, a MOS transistor P5, a MOS transistor P6, a MOS transistor P7, and a MOS transistor P8;
[0030] The drain of the MOS tube N4 is electrically connected to the gate of the MOS tube N4 and the gate of the MOS tube N5 respectively, and is used to input the control current. The source of the MOS tube N4 and the source of the MOS tube N5 are both grounded. The drain of the MOS tube N5 is electrically connected to the drain of the MOS tube P5, the gate of the MOS tube P5, the gate of the MOS tube P6, the gate of the MOS tube P7 and the gate of the MOS tube P8 respectively. The source of the MOS tube P5, the source of the MOS tube P6, the source of the MOS tube P7 and the source of the MOS tube P8 are all electrically connected to the power supply vdd. The drain of the MOS tube P6, the drain of the MOS tube P7 and the drain of the MOS tube P8 respectively provide driving current for the three inverters of the ring oscillator.
[0031] In a certain embodiment, the divider unit includes M second D flip-flops D2, M is a positive integer, and the M second D flip-flops D2 are connected in sequence, and the sequential connection is that the Q output end of the front-end second D flip-flop D2 is electrically connected to the clock end of the rear-end second D flip-flop D2, and the D input end of each second D flip-flop D2 is electrically connected to its own QN output end, the clock end of the head-end second D flip-flop D2 is used to input the clock signal, and the Q output end of the rear-end second D flip-flop D2 is used to output the divided clock signal.
[0032] Compared with the prior art, the present invention has the following beneficial effects: in actual use, the clock signal finally output by the present invention is related to the control current, and the control current is generated by the frequency divider unit dividing the clock signal, the control voltage generating unit generating the control voltage based on the divided clock signal and finally the current source unit generating the control voltage based on the control voltage, so the whole oscillator circuit realizes self-locking control with high precision, and the circuit does not need additional reference frequency or reference voltage. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] Figure 1 It is a schematic diagram of the structure of the present invention in the embodiment;
[0034] Figure 2 is a circuit diagram of a control voltage generating unit in an embodiment;
[0035] Figure 3 for Figure 2 Waveform diagram of relevant nodes in ;
[0036] Figure 4 is a circuit diagram of a current source unit in an embodiment;
[0037] Figure 5 is a circuit diagram of a clock signal generating unit in an embodiment;
[0038] Figure 6 is a circuit diagram of a frequency divider unit in an embodiment;
[0039] Figure 7 It is a short-time waveform simulation diagram of the circuit simulation of the present invention in the embodiment;
[0040] Figure 8 It is a waveform simulation diagram of a long time during the circuit simulation of the present invention in the embodiment. DETAILED DESCRIPTION
[0041] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.
[0042] In order to provide an oscillator circuit that can output a higher frequency, whose generated clock signal is not easily affected by temperature and power supply and does not require any additional input of auxiliary signals such as reference frequency or reference voltage, such as Figure 1 As shown, this embodiment provides a high-precision self-locking oscillator circuit, including a control voltage generating unit 1, a current source unit 2, a clock signal generating unit 3 and a frequency divider unit 4;
[0043] The frequency divider unit 4 is electrically connected to the clock signal generating unit 3, and divides the frequency of the clock signal FOSC output by the clock signal generating unit 3 to output the divided clock signal CK;
[0044] The control voltage generating unit 1 is electrically connected to the frequency divider unit 3 and generates a control voltage Vref based on the divided clock signal CK;
[0045] The current source unit 2 is electrically connected to the control voltage generating unit 1 and generates a control current I1 based on the control voltage Vref;
[0046] The clock signal generating unit 3 is electrically connected to the current source unit 2 , and generates a clock signal FOSC based on the control current I1 . The clock signal FOSC is positively correlated with the control current I1 .
[0047] In actual use, the clock signal FOSC finally output by the present invention is related to the control current I1, and the control current I1 is generated by the divider unit 4 dividing the clock signal FOSC, the control voltage generating unit 1 generating the control voltage Vref based on the divided clock signal CK, and finally by the current source unit 2 based on the control voltage Vref. Therefore, the entire oscillator circuit realizes self-locking control with high precision, and the circuit does not require an additional reference frequency or reference voltage, thereby reducing costs.
[0048] Specifically, in this embodiment, Figure 2 As shown, the control voltage generating unit 1 includes a control clock generating unit 10, a MOS transistor P1, a MOS transistor N1, a MOS transistor N2, a capacitor C1 and a capacitor C2;
[0049] The control clock generating unit 10 generates a control clock signal CK1, a control clock signal CK2 and a control clock signal CK3 based on the divided clock signal CK;
[0050] The frequencies of the control clock signal CK1, the control clock signal CK2 and the control clock signal CK3 are all the same as the frequency of the divided clock signal CK; the waveform of the control clock signal CK1 is opposite to that of the divided clock signal CK;
[0051] The rising edge timing of the control clock signal CK1 is the same as the rising edge timing of the control clock signal CK2, and the falling edge timing of the control clock signal CK2 is the same as the rising edge timing of the control clock signal CK3; in the same cycle, the sum of the high level time of the control clock signal CK2 and the high level time of the control clock signal CK3 is the same as the high level time of the control clock signal CK1;
[0052] The source of the MOS transistor P1 is used to input the current I2, the gate of the MOS transistor P1 is used to input the control clock signal CK1, the drain of the MOS transistor P1 is electrically connected to the drain of the MOS transistor N1, one end of the capacitor C1 and the source of the MOS transistor N2 respectively, the other end of the capacitor C1 is grounded, the gate of the MOS transistor N3 is used to input the control clock signal CK3, the gate of the MOS transistor N2 is used to input the control clock signal CK2, and the drain of the MOS transistor N2 is grounded through the capacitor C2 for outputting the control voltage.
[0053] More specifically, in Figure 2 In the embodiment, the control clock generating unit 10 includes a delay unit, an inverter INVN1, an XOR gate XOR1, an OR gate OR1, a first D flip-flop D1 and an AND gate AND1;
[0054] The input end of the inverter INV1 is electrically connected to the first input end of the XOR gate XOR1, the input end of the delay unit and the first input end of the OR gate OR1 respectively, and is used to input the frequency-divided clock signal;
[0055] The output end of the inverter INV1 is electrically connected to the D input end of the first D flip-flop D1 and the first input end of the AND gate AND1 respectively, and is used to output the control clock signal CK1;
[0056] The output end of the delay unit is electrically connected to the second input end of the XOR gate XOR1; the output end of the XOR gate XOR1 is electrically connected to the second input end of the OR gate OR1 and the clock input end of the first D flip-flop D1 respectively; the output end of the OR gate OR1 is used to output the control clock signal CK2; the QN output end of the first D flip-flop D1 is electrically connected to the second input end of the AND gate AND1, and the output end of the AND gate AND1 outputs the control clock signal CK3.
[0057] In addition, in this embodiment, the capacitance of the capacitor C1 is greater than the capacitance of the capacitor C2.
[0058] right Figure 2 The circuit is analyzed as follows:
[0059] first Figure 2 The waveform of the relevant signal of the circuit is as follows Figure 3 As shown, from Figure 3 It can be seen that a complete cycle of the control clock signal CK1 consists of t1, t2 and t3, where:
[0060] At t1 stage:
[0061] Control clock signal CK1 = 0, then MOS tube P1 is turned on, and current I2 charges capacitor C1;
[0062] Control clock signal CK2 = 0, MOS tube N2 is turned off;
[0063] Control clock signal CK3 = 0, MOS tube N1 is turned off;
[0064] At t2 stage:
[0065] Control clock signal CK1 = 0, at this time MOS tube P1 is turned off, and the voltage Vc1 on capacitor C1 = (I2*t1) / C1;
[0066] Control clock signal CK2 = 1, MOS tube N2 is turned on, capacitor C1 and capacitor C2 are connected, here it is designed that C1>>C2, capacitor C2 mainly plays the role of noise filtering;
[0067] Control clock signal CK3 = 0, MOS tube N1 is turned off;
[0068] At t3 stage:
[0069] Control clock signal CK1 = 0, at this time MOS tube P1 is turned off;
[0070] Control clock signal CK2 = 0, MOS tube N2 is turned off;
[0071] The control clock signal CK3 = 1, the MOS tube N1 is turned on, and the charge on the capacitor C1 is discharged. In this stage, Vc1 = 0.
[0072] Combining the above process, the control voltage Vref is inversely proportional to the divided clock signal CK, and its calculation formula is as follows:
[0073]
[0074] Where Fck is the magnitude of the divided clock signal CK, and its calculation formula is as follows: Fck = FOSC / M, M is the frequency division number of the divider unit 4, and the calculation formula of Fck is brought into the calculation common of the control voltage Vref, and the following can be obtained:
[0075]
[0076] Therefore, when the clock signal FOSC is larger, the control voltage Vref is smaller.
[0077] Specifically, in this embodiment, the circuit of the current source unit 2 is as follows: Figure 4 As shown, it includes an operational amplifier OP, a MOS tube N3, a resistor R and a first current mirror unit 20. The positive input terminal of the operational amplifier OP is used to input a control voltage. The negative input terminal of the operational amplifier OP is electrically connected to the source of the MOS tube N3 and one end of the resistor R respectively. The other end of the resistor R is grounded. The output terminal of the operational amplifier OP is electrically connected to the gate of the MOS tube N3. The first current mirror unit 20 is electrically connected to the drain of the MOS tube N3, and generates a control current I1 and a current I2 based on the current flowing through the resistor R.
[0078] More specifically, the first current mirror unit 20 includes a MOS transistor P2, a MOS transistor P3 and a MOS transistor P4; the source of the MOS transistor P2, the source of the MOS transistor P3 and the source of the MOS transistor P4 are all used to be electrically connected to the power supply vdd, the gate of the MOS transistor P2 is respectively electrically connected to the drain of the MOS transistor P2, the drain of the MOS transistor N3, the gate of the MOS transistor P3 and the gate of the MOS transistor P4, the drain of the MOS transistor P3 is used to output the control current I1, and the drain of the MOS transistor P4 is used to output the current I2.
[0079] right Figure 4 The circuit is analyzed as follows:
[0080] Since the operational amplifier OP adopts negative feedback connection, it can be known that Vn = Vref (virtual short), then Iref = Vn / R = Vref / R;
[0081] For the MOS transistor P2, it is assumed that the groove width of the MOS transistor P2 = Wp2, and the groove length of the MOS transistor P2 = Lp2;
[0082] For the MOS transistor P3, it is assumed that the groove width of the MOS transistor P3 = Wp3, and the groove length of the MOS transistor P3 = Lp3;
[0083] For the MOS transistor P4, it is assumed that the groove width of the MOS transistor P4 = Wp4, and the groove length of the MOS transistor P4 = Lp4;
[0084] Since the sources of MOS tubes P2, P3 and P4 are all connected to the power supply vdd, and the gates are connected, MOS tube P2 is analyzed. Since the gate and drain of MOS tube P2 are connected, it can be known that MOS tube P2 is in the saturation region, and the current expression is as follows:
[0085]
[0086] Since the gate and source of MOS tubes P3, MOS tubes P4 and MOS tubes P2 are connected together, their gate voltage and source voltage are equal, and the Vgs of MOS tubes P3, MOS tubes P4 and MOS tubes P2 are equal, so we get
[0087]
[0088] Therefore, by setting the sizes of the MOS transistor P4 and the MOS transistor P2, I2 / Iref can be made a multiple, and it is assumed here that I2=N*Iref.
[0089] Specifically, in this embodiment, the circuit of the clock signal generating unit 3 is as follows: Figure 5As shown, it includes a second current mirror unit 30, a ring oscillator 31, a MOS transistor P12, a MOS transistor P13, a MOS transistor N9, a MOS transistor N10 and a buffer;
[0090] The second current mirror unit 30 provides a driving current for each inverter of the ring oscillator 31 based on the control current I1; the output end of the tail inverter of the ring oscillator 31 is electrically connected to the gate of the MOS transistor N9, the input end of the tail inverter is electrically connected to the gate of the MOS transistor N10, and the source of the MOS transistor N9 and the source of the MOS transistor N10 are both grounded; the drain of the MOS transistor N9 is electrically connected to the drain of the MOS transistor P12 and the gate of the MOS transistor P13 respectively, the drain of the MOS transistor N10 is electrically connected to the drain of the MOS transistor P13, the gate of the MOS transistor P12 and the input end of the buffer buffer respectively, the output end of the buffer buffer is used to output the clock signal FOSC, the source of the MOS transistor P12 and the source of the MOS transistor P13 are used to be electrically connected to the power supply vdd.
[0091] Specifically, in this embodiment, the ring oscillator 31 includes three inverters, wherein MOS transistor P9 and MOS transistor N6 form an inverter, MOS transistor P10 and MOS transistor N7 form an inverter, and MOS transistor P11 and MOS transistor N8 form an inverter. In some implementations, the number of inverters in the ring oscillator 31 can be adjusted according to actual needs.
[0092] Assuming that the number of inverters in the ring oscillator 31 is K, the clock signal FOSC=K*I1.
[0093] Specifically, in this embodiment, the second current mirror unit 30 includes a MOS transistor N4, a MOS transistor N5, a MOS transistor P5, a MOS transistor P6, a MOS transistor P7 and a MOS transistor P8;
[0094] The drain of the MOS transistor N4 is electrically connected to the gate of the MOS transistor N4 and the gate of the MOS transistor N5 respectively, and is used to input a control current. The source of the MOS transistor N4 and the source of the MOS transistor N5 are both grounded. The drain of the MOS transistor N5 is electrically connected to the drain of the MOS transistor P5, the gate of the MOS transistor P5, the gate of the MOS transistor P6, the gate of the MOS transistor P7, and the gate of the MOS transistor P8 respectively. The source of the MOS transistor P5, the source of the MOS transistor P6, the source of the MOS transistor P7, and the source of the MOS transistor P8 are all electrically connected to the power supply vdd. The drain of the MOS transistor P6, the drain of the MOS transistor P7, and the drain of the MOS transistor P8 respectively provide driving current for the three inverters of the ring oscillator 31.
[0095] Specifically, in this embodiment, Figure 5The clock signal generating unit 3 shown is a current-controlled clock generating circuit, that is, the clock signal FOSC is proportional to the control current I1. In some embodiments, the clock signal generating unit 3 can also be designed as a voltage-controlled clock generating circuit, in which case the clock signal FOSC is inversely proportional to the control current I1.
[0096] Specifically, in this embodiment, the circuit of the frequency divider unit 4 is as follows: Figure 6 As shown, it includes M second D flip-flops D2, M is a positive integer, and the M second D flip-flops D2 are connected in sequence, and the connection is such that the Q output end of the front second D flip-flop D2 is electrically connected to the clock end of the rear second D flip-flop D2, and the D input end of each second D flip-flop D2 is electrically connected to its own QN output end. The clock end of the head second D flip-flop D2 is used to input the clock signal, and the Q output end of the rear second D flip-flop D2 is used to output the divided clock signal CK.
[0097] Combining the above circuits for analysis, the formula for the clock signal FOSC is derived as follows:
[0098]
[0099] I2=I2=N*Iref
[0100] Iref=Vref / R
[0101] Can get,
[0102]
[0103] Eliminating the common divisor on both sides gives:
[0104]
[0105] From this formula, it can be obtained that the frequency of the clock signal FOSC is related to the set current multiple N, the frequency division coefficient M, the capacitor C1 and the resistor R, where N and M are constants, and the capacitor C1 and the resistor R are less affected by temperature and voltage, so the final output clock signal Fosc is a relatively stable frequency.
[0106] In actual use, the circuit of the present invention includes the following three working stages:
[0107] The first working stage is the oscillation start-up stage, at which the frequency of the clock signal FOSC is very low, the control voltage Vref continues to rise, the control current I1 and the current I2 continue to rise, and then the clock signal FOSC gradually increases;
[0108] The second working stage is the overshoot stage, at which the clock signal FOSC is higher than the design value, and the control voltage Vref begins to decrease. At this time, the control current I1 and the current I2 decrease, and the frequency of the clock signal FOSC decreases;
[0109] The third working phase is a stable phase, in which the frequency of the clock signal FOSC is equal to the design value, the control voltage Vref is stable, and the control currents I1 and I2 are stable.
[0110] The overall circuit of the present invention is simulated, and the frequency of the clock signal Fosc is designed to be 180 MHZ. The simulation results of the short time and the long time are as follows: Figure 7 and Figure 8 As shown, from Figure 7 and Figure 8 It can be seen that the control voltage Vref first rises, then overshoots and then drops, and finally stabilizes. After reaching stability, the control voltage Vref is 1.212V, and the frequency of the clock signal FOSC is 180MHZ, which is impossible to achieve using a relaxation oscillator (0.18um process).
[0111] In summary, the circuit of the present invention does not require an external reference voltage, reference current, and reference frequency, has low cost, and can achieve the same temperature characteristics and voltage characteristics as a relaxation oscillator, but the output frequency is significantly higher than that of the existing relaxation oscillator. Finally, the output frequency can be as high as that of a ring oscillator, but the stability is much better than that of a ring oscillator.
[0112] The above is based on the present invention as an inspiration. Through the above description, relevant staff can make various changes and modifications without departing from the technical idea of this invention. The technical scope of this invention is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.
Claims
1. A high-precision self-locking oscillator circuit, characterized in that: It includes a control voltage generating unit, a current source unit, a clock signal generating unit and a frequency divider unit; The frequency divider unit is electrically connected to the clock signal generating unit, divides the frequency of the clock signal output by the clock signal generating unit, and outputs a frequency-divided clock signal; The control voltage generating unit is electrically connected to the frequency divider unit and generates a control voltage based on the frequency-divided clock signal; The current source unit is electrically connected to the control voltage generating unit, and generates a control current based on the control voltage; The clock signal generating unit is electrically connected to the current source unit, and generates the clock signal based on the control current.
2. A high-precision self-locking oscillator circuit according to claim 1, characterized in that: The control voltage generating unit includes a control clock generating unit, a MOS transistor P1, a MOS transistor N1, a MOS transistor N2, a capacitor C1 and a capacitor C2; The control clock generating unit generates a control clock signal CK1, a control clock signal CK2 and a control clock signal CK3 based on the divided clock signal; The frequencies of the control clock signal CK1, the control clock signal CK2 and the control clock signal CK3 are all the same as the frequency of the divided clock signal; the waveform of the control clock signal CK1 is opposite to that of the divided clock signal; The rising edge timing of the control clock signal CK1 is the same as the rising edge timing of the control clock signal CK2, and the falling edge timing of the control clock signal CK2 is the same as the rising edge timing of the control clock signal CK3; in the same cycle, the sum of the high level time of the control clock signal CK2 and the high level time of the control clock signal CK3 is the same as the high level time of the control clock signal CK1; The source of the MOS transistor P1 is used to input the current I2, the gate of the MOS transistor P1 is used to input the control clock signal CK1, the drain of the MOS transistor P1 is electrically connected to the drain of the MOS transistor N1, one end of the capacitor C1 and the source of the MOS transistor N2 respectively, the other end of the capacitor C1 is grounded, the gate of the MOS transistor N3 is used to input the control clock signal CK3, the gate of the MOS transistor N2 is used to input the control clock signal CK2, and the drain of the MOS transistor N2 is grounded through the capacitor C2 for outputting the control voltage.
3. A high-precision self-locking oscillator circuit according to claim 2, characterized in that: The control clock generating unit includes a delay unit, an inverter INVN1, an XOR gate XOR1, an OR gate OR1, a first D flip-flop D1 and an AND gate AND1; The input end of the inverter INV1 is electrically connected to the first input end of the XOR gate XOR1, the input end of the delay unit and the first input end of the OR gate OR1 respectively, and is used to input the divided clock signal; The output end of the inverter INV1 is electrically connected to the D input end of the first D flip-flop D1 and the first input end of the AND gate AND1 respectively, for outputting the control clock signal CK1; The output end of the delay unit is electrically connected to the second input end of the XOR gate XOR1; the output end of the XOR gate XOR1 is electrically connected to the second input end of the OR gate OR1 and the clock input end of the first D flip-flop D1 respectively; the output end of the OR gate OR1 is used to output the control clock signal CK2; the QN output end of the first D flip-flop D1 is electrically connected to the second input end of the AND gate AND1, and the output end of the AND gate AND1 outputs the control clock signal CK3.
4. A high-precision self-locking oscillator circuit according to claim 2, characterized in that: The capacitance of the capacitor C1 is greater than the capacitance of the capacitor C2.
5. A high-precision self-locking oscillator circuit according to any one of claims 2 to 4, characterized in that: The current source unit includes an operational amplifier OP, a MOS tube N3, a resistor R and a first current mirror unit. The positive input end of the operational amplifier OP is used to input the control voltage. The negative input end of the operational amplifier OP is electrically connected to the source of the MOS tube N3 and one end of the resistor R respectively. The other end of the resistor R is grounded. The output end of the operational amplifier OP is electrically connected to the gate of the MOS tube N3. The first current mirror unit is electrically connected to the drain of the MOS tube N3, and generates the control current and the current I2 based on the current flowing through the resistor R.
6. A high-precision self-locking oscillator circuit according to claim 5, characterized in that: The first current mirror unit includes a MOS transistor P2, a MOS transistor P3 and a MOS transistor P4; the source of the MOS transistor P2, the source of the MOS transistor P3 and the source of the MOS transistor P4 are all used to be electrically connected to the power supply vdd, the gate of the MOS transistor P2 is respectively electrically connected to the drain of the MOS transistor P2, the drain of the MOS transistor N3, the gate of the MOS transistor P3 and the gate of the MOS transistor P4, the drain of the MOS transistor P3 is used to output the control current, and the drain of the MOS transistor P4 is used to output the current I2.
7. A high-precision self-locking oscillator circuit according to claim 1, characterized in that: The clock signal is positively correlated with the control current; The clock signal generating unit includes a second current mirror unit, a ring oscillator, a MOS transistor P12, a MOS transistor P13, a MOS transistor N9, a MOS transistor N10 and a buffer; The second current mirror unit provides a driving current for each inverter of the ring oscillator based on the control current; the output end of the tail inverter of the ring oscillator is electrically connected to the gate of the MOS tube N9, the input end of the tail inverter is electrically connected to the gate of the MOS tube N10, and the source of the MOS tube N9 and the source of the MOS tube N10 are both grounded; the drain of the MOS tube N9 is electrically connected to the drain of the MOS tube P12 and the gate of the MOS tube P13 respectively, the drain of the MOS tube N10 is electrically connected to the drain of the MOS tube P13, the gate of the MOS tube P12 and the input end of the buffer buffer respectively, the output end of the buffer buffer is used to output the clock signal, and the source of the MOS tube P12 and the source of the MOS tube P13 are used to be electrically connected to the power supply vdd.
8. A high-precision self-locking oscillator circuit according to claim 7, characterized in that: The ring oscillator includes three inverters.
9. A high-precision self-locking oscillator circuit according to claim 8, characterized in that: The second current mirror unit includes a MOS transistor N4, a MOS transistor N5, a MOS transistor P5, a MOS transistor P6, a MOS transistor P7 and a MOS transistor P8; The drain of the MOS transistor N4 is electrically connected to the gate of the MOS transistor N4 and the gate of the MOS transistor N5 respectively, and is used to input the control current. The source of the MOS transistor N4 and the source of the MOS transistor N5 are both grounded. The drain of the MOS transistor N5 is electrically connected to the drain of the MOS transistor P5, the gate of the MOS transistor P5, the gate of the MOS transistor P6, the gate of the MOS transistor P7, and the gate of the MOS transistor P8 respectively. The source of the MOS transistor P5, the source of the MOS transistor P6, the source of the MOS transistor P7, and the source of the MOS transistor P8 are all electrically connected to the power supply vdd. The drain of the MOS transistor P6, the drain of the MOS transistor P7, and the drain of the MOS transistor P8 respectively provide driving current for the three inverters of the ring oscillator.
10. A high-precision self-locking oscillator circuit according to claim 7, characterized in that: The frequency divider unit includes M second D flip-flops D2, M is a positive integer, and the M second D flip-flops D2 are connected in sequence, and the sequential connection is that the Q output end of the front second D flip-flop D2 is electrically connected to the clock end of the rear second D flip-flop D2, and the D input end of each second D flip-flop D2 is electrically connected to its own QN output end. The clock end of the head second D flip-flop D2 is used to input the clock signal, and the Q output end of the rear second D flip-flop D2 is used to output the divided clock signal.