Memory and preparation method thereof
By synchronously forming through holes in the interlayer dielectric layer and forming a storage structure, the complexity of RRAM embedded CMOS is solved, the process flow is simplified, cost and time is reduced, and efficiency and market competitiveness are improved.
Patent Information
- Application Number
- CN202411349959.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-25
- Publication Date
- 2024-12-27
AI Technical Summary
The process of embedding variable resistive memory (RRAM) into CMOS is complicated, resulting in increased production costs and time.
By synchronously forming through holes based on the same mask in the interlayer dielectric layer and forming them in the conductive structure and storage structure, the process flow is simplified and the use of masks is reduced, and the integration of RRAM and CMOS logic gate is achieved.
It reduces the production cost and time, improves efficiency, simplifies the process flow, ensures the electrical performance of the memory, and improves market competitiveness and production cycle.
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Figure CN119212401A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to semiconductor device manufacturing technology, and in particular to a memory and a method for preparing the same. Background Art
[0002] Resistive Random Access Memory (RRAM) is a new type of non-volatile memory. It applies pulse voltage to the metal oxide film in the RRAM to generate a large resistance difference to store digital signals "0" and "1" to store data. RRAM has the advantages of low power consumption, high rewrite speed and simple structure. It is usually a sandwich structure composed of metal-insulator-metal structure.
[0003] Unlike flash memory, RRAM does not rely on charge to store information, so there is no problem of electron leakage due to the thin tunneling layer. It is one of the most promising new memories in the future. As RRAM becomes mainstream, we will see highly intelligent system solutions supported by large-capacity embedded memory and efficient microcontrollers that can realize new applications between networked devices. RRAM is the development trend of the future and one of the forces that will eventually make the highly praised Internet of Things a reality. However, the process of embedding variable resistance memory into CMOS is very complicated. It is necessary to make the CMOS part after making the variable resistance memory separately, which increases the preparation cost and preparation time. Summary of the invention
[0004] The purpose of this application is to provide a memory and a method for preparing the same, which can at least reduce the preparation cost and preparation time of embedding RRAM into CMOS. To achieve the purpose of this application, this application provides the following technical solutions:
[0005] In a first aspect, the present application provides a method for preparing a memory, comprising: providing a substrate, the substrate comprising a first region and a second region arranged at intervals along a first direction parallel to a top surface of the substrate; the top surface of the substrate comprising a dielectric layer partially located in the first region and partially located in the second region; forming an interlayer dielectric layer on the dielectric layer; based on the same mask, synchronously forming a first through hole located in the first region and a second through hole located in the second region, the first through hole and the second through hole both penetrating the interlayer dielectric layer and the dielectric layer along the second direction; after forming a conductive structure in the first through hole, forming a storage structure in the second through hole, the storage structure comprising a first electrode, a resistive layer and a second electrode stacked in sequence along the second direction.
[0006] In the memory preparation method in the above embodiment, it includes providing a substrate and a dielectric layer located on the top surface of the substrate; then forming an interlayer dielectric layer on the dielectric layer; and finally forming a conductive structure and a storage structure in the interlayer dielectric layer. In this preparation method, the conductive structure is formed once in the first through hole by synchronously forming a first through hole and a second through hole in the interlayer dielectric layer based on the same mask. When preparing the storage structure, it is only necessary to etch back and reopen the second through hole, and fill the second through hole in sequence to form a first electrode, a resistive layer, and a second electrode, and the preparation of the storage structure can be completed. The number of masks used is saved. At the same time, with the help of specific architectural technology, RRAM is integrated into the logic circuit. Without increasing the excess volume, by stacking RRAM on the logic gate of CMOS, it is possible to increase memory storage on the basis of CMOS ultra-dense logic.
[0007] This new preparation method can simplify the production process, reduce costs, improve efficiency, and ensure that the total stacking thickness of RRAM meets its electrical performance requirements.
[0008] In some embodiments, forming the first through hole and the second through hole also includes: forming a patterned photoresist layer on the top surface of the interlayer dielectric layer based on the same mask, the patterned photoresist layer including a first opening located in the first area and a second opening located in the second area, the first opening is used to define the first through hole, and the second opening is used to define the second through hole; patterning the interlayer dielectric layer based on the patterned photoresist layer to form a first initial through hole located in the first area and a second initial through hole located in the second area; etching and increasing the openings of the first initial through hole and the second initial through hole to obtain the first through hole and the second through hole with a "T-shaped" longitudinal cross-section.
[0009] In some embodiments, the second through hole includes a step therein;
[0010] In some embodiments, forming a storage structure in the second through hole includes forming a first electrode in the second through hole to fill the step plane opening in the second through hole; and sequentially forming a resistive layer and a second electrode above the first electrode in the second through hole.
[0011] In some embodiments, forming a resistive layer and a second electrode includes: filling a resistive material above the first electrode in the second through hole; etching back the resistive material to obtain a resistive layer whose top surface is lower than the top surface of the interlayer dielectric layer; filling an electrode material above the resistive layer in the second through hole; and planarizing the electrode material to obtain a second electrode whose top surface is flush with the top surface of the interlayer dielectric layer.
[0012] In some embodiments, forming a conductive structure in the first through hole includes: forming a first metal barrier layer covering the inner surface of the first through hole and the top surface of the substrate in the first through hole; forming a conductive layer that at least fills the first through hole, and the conductive layer and the first metal barrier layer are used to jointly constitute a conductive structure.
[0013] In some embodiments, during the process of forming a conductive structure in the first through hole, a conductive structure is simultaneously formed in the second through hole; a protective layer covering the conductive structure and the top surface of the interlayer dielectric layer is formed; a patterned photoresist layer is formed on the protective layer, and the patterned photoresist layer includes an opening pattern that exposes the conductive structure in the second through hole; the conductive structure in the second through hole is etched based on the patterned photoresist layer to remove the conductive structure in the second through hole.
[0014] In some embodiments, the substrate includes a conductive block located in the second region; the conductive block is used as an etching stop layer to etch and remove the conductive structure in the second through hole.
[0015] In some embodiments, under the same etching conditions, the etching rates of the conductive layer and the first metal barrier layer are greater than the etching rate of the interlayer dielectric layer.
[0016] In some embodiments, a bottom surface of the second through hole is located inside a top surface of the conductive block.
[0017] In a second aspect, the present application also provides a memory, which is prepared using any of the above-mentioned memory preparation methods.
[0018] The memory includes a substrate, a dielectric layer, and an interlayer dielectric layer, wherein the interlayer dielectric layer is located on the top surface of the dielectric layer, and the metal connection structure on the bottom surface of the conductive structure and the metal connection structure on the bottom surface of the storage structure are both located in the substrate; the conductive structure and the storage structure both penetrate the interlayer dielectric layer and the dielectric layer is in contact with the metal connection structure on the bottom surface of the conductive structure. In the memory in the above embodiment, the simplified process flow effectively reduces the production cost by reducing the production steps and reducing the complexity of the operation, thereby improving the market competitiveness of the memory prepared by the process. At the same time, the simplification of steps and the simplification of operations can shorten the production cycle of the memory without reducing the high performance and stability of the memory, providing potential for its long-term use and further development. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0020] Figure 1-Figure 4 It is a schematic diagram of the structures corresponding to each step in the preparation method of an embedded RRAM;
[0021] Figure 5 is a flow chart of a memory preparation method provided in an embodiment;
[0022] Figure 6 is a schematic cross-sectional view of a structure obtained after an initial through hole is formed in step S402 in a memory manufacturing method provided in an embodiment;
[0023] Figure 7 is a schematic cross-sectional view of a structure obtained after a through hole is formed in step S404 in a memory manufacturing method provided in an embodiment;
[0024] Figure 8 is a schematic cross-sectional view of a structure obtained after forming a first metal barrier layer in step S6022 in a memory manufacturing method provided in an embodiment;
[0025] Fig. 9 It is a schematic cross-sectional view of a structure obtained after a conductive layer is formed in step S6024 in a memory manufacturing method provided in an embodiment;
[0026] Fig.10 is a schematic cross-sectional view of a structure obtained after a protective layer is formed in step S6042 in a memory manufacturing method provided in an embodiment;
[0027] Fig.11 It is a schematic cross-sectional view of a structure obtained after the conductive structure in the second through hole is removed in step S6044 in a memory manufacturing method provided in an embodiment;
[0028] Fig.12 It is a schematic cross-sectional view of a structure obtained after a storage structure is formed in step S6046 in a memory preparation method provided in an embodiment.
[0029] Description of Reference Numerals
[0030] 10. Substrate; 11. Dielectric layer; 12. Interlayer dielectric layer; 13. Protective layer; 20. Metal connection structure; 201. Conductive block; 202. Connection barrier layer; 311. First initial through hole; 321. Second initial through hole 321; 31. First through hole; 32. Second through hole; 40. Conductive structure; 401. First metal barrier layer; 402. Conductive layer; 50. Storage structure; 501. First electrode; 502. Resistive layer; 503. Second electrode. DETAILED DESCRIPTION
[0031] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0033] It should be understood that when an element or layer is referred to as "on ...", "connected to" or "coupled to" other elements or layers, it can be directly on, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.
[0034] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0035] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0036] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic representations of idealized embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the invention.
[0037] Typically, RRAM is configured to be embedded in an interlayer dielectric layer between several conductive metal lines established in the back-end process. However, in order to match the ever-shrinking process node, the thickness of the interlayer dielectric layer between the conductive metal lines is also continuously reduced.
[0038] In order to ensure certain electrical performance requirements of RRAM, in traditional technology, the first electrode in RRAM is placed in whole or in part in the through hole of the interlayer dielectric layer on the conductive block, so that the first electrode can be made very thin, thereby reducing the height of RRAM in the CMOS back-end process and facilitating integration.
[0039] As can be seen from the background technology, the process of embedding RRAM into CMOS is very complicated. It is necessary to make the CMOS part after making the RRAM separately. Figure 1-Figure 4 This is a schematic diagram of the structure corresponding to each step in the preparation method of embedded RRAM. Figure 1 , providing a substrate 10, on which a dielectric layer 11 and an interlayer dielectric layer 12 are formed, and using a mask, exposing and patterning the second through hole 32 in the second region. Figure 2 , using a photomask, the resistive layer 502 and the second electrode 503 are exposed and patterned to form a storage structure 50. Figure 3 , filling the interlayer dielectric layer 12. Please refer to Figure 4 , photolithography and filling are also performed on the first region to obtain a conductive structure 40 .
[0040] It is not difficult to find that this preparation method inevitably requires multiple lithography steps, which increases the process complexity and cost. In addition, multiple lithography steps will also increase the risk of alignment errors, which will lead to RRAM device performance degradation or even device failure.
[0041] Based on this, the present application embodiment provides a memory preparation method, including: step S20-step S60, for example, refer to Figure 5 .
[0042] Step S20: providing a substrate, the substrate comprising a first region and a second region arranged at intervals along a first direction parallel to a top surface of the substrate; the top surface of the substrate comprising a dielectric layer partially located in the first region and in the second region.
[0043] For example, the substrate may include but is not limited to at least one of a silicon substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon on insulator (SOI) substrate, a silicon on diamond (SOD) substrate, and a strained layer silicon substrate deposited on a germanium silicon wafer. At the same time, it may also include but is not limited to a dielectric layer composed of a low-K dielectric material, for example, silicon oxide doped with carbon, phosphorus or boron, and a composite material of the three. The transistor logic gate (metal connection structure) obtained by the normal CMOS process of the front-end process is respectively located in the first region and the second region of the dielectric layer in the substrate.
[0044] The metal connection structure includes a conductive block and a connection barrier layer that wraps the bottom and side surfaces of the conductive block. The conductive block includes, but is not limited to, copper (Cu), and the connection barrier layer includes, but is not limited to, titanium nitride (TiN) and tantalum nitride (TaN). By way of example, in this embodiment, by providing a connection barrier layer including the bottom and side surfaces of the conductive block, the metal material in the conductive block can be prevented from diffusing into the substrate outside the metal connection structure, and because the connection barrier layer has an adhesive effect, the conductive block can be more easily adhered to the surface of the connection barrier layer, thereby being more conducive to the formation of the conductive block.
[0045] By way of example, the material of the dielectric layer may include but is not limited to an insulating material. For example, the dielectric layer may be a silicon nitride layer, a silicon carbonitride layer, a silicon oxycarbide layer, or a fluorosilicate glass layer.
[0046] For example, the first area corresponds to a logic area, and the second area corresponds to a storage area, wherein the structural components in the first area are used to implement data calculation, and the structures in the second area are used to implement data storage.
[0047] Step S40: forming an interlayer dielectric layer on the dielectric layer; and synchronously forming a first through hole located in the first area and a second through hole located in the second area based on the same photomask, wherein both the first through hole and the second through hole penetrate the interlayer dielectric layer and the dielectric layer along the second direction.
[0048] For example, the interlayer dielectric layer may include, but is not limited to, at least one of hafnium oxide (HfOx), aluminum oxide (AlOx), hafnium aluminum oxide (HfAlO), and tantalum oxide (TaOx).
[0049] Step S60: After forming a conductive structure in the first through hole, forming a storage structure in the second through hole, the storage structure comprising a first electrode, a resistive switching layer, and a second electrode sequentially stacked along the second direction.
[0050] For example, the first electrode and the second electrode may include but are not limited to a copper electrode, a tungsten electrode, a tantalum nitride electrode, a titanium nitride electrode, etc. The materials of the first electrode and the second electrode may also be specifically selected according to the type of the conductive filament.
[0051] For example, the resistive layer may include but is not limited to a metal oxide layer, for example, the resistive layer may be a hafnium oxide (HfOx) layer, an aluminum oxide (AlOx) layer, a tantalum oxide (TaOx) layer, or a combination of the above layers. In this embodiment, there is no specific restriction on the materials of the resistive layer, the first electrode, and the second electrode, as long as they are compatible with the CMOS process.
[0052] The resistive layer is sandwiched between the first electrode and the second electrode. By applying current or voltage pulses to the electrodes, the oxygen vacancies in the resistive layer change, causing the resistance value of the resistive layer to change between a high resistance state and a low resistance state, thereby realizing the function of storing data.
[0053] It is understood that unless otherwise expressly stated herein, Figure 5 There is no strict order restriction for the execution of the steps described in the method, and the steps can be executed in other orders. Moreover, at least a part of the steps described may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.
[0054] The memory obtained after steps S20-S60 can be referred to Fig.12 In order to facilitate understanding of this application, Fig.12 An example of a memory prepared by the preparation method of the present application. It should be noted that the diagram provided in this embodiment only illustrates the basic concept of the present disclosure in a schematic manner. Although the diagram only shows the material layers related to the present disclosure rather than the number, shape and size of the material layers in actual implementation, the number and proportion of each material layer in actual implementation may be changed arbitrarily, and the layout of the material layers may also be more complicated.
[0055] In some embodiments, step S20 further includes: forming a dielectric layer 11 and an interlayer dielectric layer 12 (not shown) covering the top surface of the substrate 10 .
[0056] For example, a stacked dielectric layer 11 and an interlayer dielectric layer 12 may be sequentially formed on the substrate 10 by, but not limited to, a molecular beam epitaxy (MBE) process, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process.
[0057] For example, before forming the dielectric layer 11 , the process further includes forming a metal connection structure 20 in the substrate 10 .
[0058] For example, in some embodiments, the substrate includes a transistor fabricated by a front-end process, which may be fabricated by, but not limited to, an ion implantation process, wherein the transistor is typically a planar MOS transistor.
[0059] See also Figure 6-Figure 7 In some embodiments, step S40 further comprises:
[0060] Step S402 : forming a first initial through hole 311 and a second initial through hole 321 .
[0061] For example, see Figure 6 The first initial through holes 311 and the second initial through holes 321 spaced apart from each other along the first direction ox may be formed in the interlayer dielectric layer 12 by, but not limited to, a wet etching process or a dry etching process.
[0062] A patterned photoresist layer is formed on the top surface of the interlayer dielectric layer 12 based on the same mask, and the patterned photoresist layer includes a first opening located in the first area and a second opening located in the second area, the first opening is used to define a first through hole 31, and the second opening is used to define a second through hole 32; based on the patterned photoresist layer, the interlayer dielectric layer 12 is patterned to form a first initial through hole 311 located in the first area and a second initial through hole 321 located in the second area.
[0063] The patterned photoresist layer is achieved by coating photoresist, exposing, developing and other steps using a self-aligned double patterning (SADP) process or a self-aligned quadruple patterning (SAQP) process.
[0064] The first preliminary through hole 311, the second preliminary through hole 321, and the center line of the metal connection structure 20 in the oy direction are located on the same straight line. The interval between the first region and the second region in the ox direction is not specifically limited here either.
[0065] Step S404: etching and increasing the openings of the first initial through hole 311 and the second initial through hole 321 to obtain the first through hole 31 and the second through hole 32 with a “T-shaped” longitudinal section.
[0066] For example, see Figure 7 The back etching process also uses either dry etching or wet etching. Among them, dry etching is usually divided into three types: plasma etching (PE), sputtering etching and reactive ion etching (RIE); the etching solution of the wet etching process can be a mixed solution of hydrofluoric acid and hydrogen peroxide. The specific selection should be based on different processing objects, requirements and actual conditions.
[0067] The first through hole 31 and the second through hole 32 penetrate the interlayer dielectric layer 12 and the dielectric layer 11 , and the bottom surfaces of the first through hole 31 and the second through hole 32 are located within the top surface of the conductive block 201 .
[0068] For example, in some embodiments, step S404 also includes a step of removing the patterned photoresist layer, which will not be described in detail herein.
[0069] See also Figure 8-Figure 12 In some embodiments, step S60 further comprises:
[0070] Step S602 : forming a conductive structure 40 in the first through hole 31 .
[0071] Step S604 : forming a storage structure 50 in the second through hole 32 .
[0072] See also Figure 8-Figure 9 In some embodiments, step S602 further includes:
[0073] Step S6022 : forming a first metal barrier layer 401 covering the inner surface of the first through hole 31 and the top surface of the substrate 10 in the first through hole 31 .
[0074] For example, see Figure 8The first metal barrier layer 401 may be formed in the first through hole 31 by any of the methods including but not limited to electron beam evaporation (E-beam evaporation), pulsed laser deposition (PLD), and sputtering methods such as DC sputtering, RF sputtering, and reactive sputtering. The first metal barrier layer 401 may include but is not limited to titanium nitride (TiN) and tantalum nitride (TaN).
[0075] Step S6024 : forming a conductive layer 402 that at least fills up the first through hole 31 . The conductive layer 402 and the first metal barrier layer 401 are used to together constitute a conductive structure 40 .
[0076] For example, see Fig. 9 , any deposition method is selected to form the structure, wherein the conductive layer 402 may include but is not limited to metal materials such as cobalt (Co), molybdenum (Mo), and rubidium (Rb). During the process of forming the conductive structure 40 in the first through hole 31 , the conductive structure 40 is formed in the second through hole 32 simultaneously.
[0077] See also Figure 10-12 In some embodiments, step S604 further includes:
[0078] Step S6042 : forming a protection layer 13 covering the top surface of the interlayer dielectric layer 12 .
[0079] For example, see Fig.10 , photoresist can be directly used as the protective layer 13. In this case, the protective layer 13 can be directly patterned by photolithography, and the patterned protective layer 13 includes a second opening for removing the conductive structure 40 in the second through hole 32. The protective layer 13 can also be obtained by any deposition method, and then a patterned photoresist layer covering the protective layer 13 is formed, and the patterned photoresist layer includes an opening pattern that exposes the conductive structure 40 in the second through hole 32. The protective layer 13 is used as a mask in the subsequent etching process to protect the integrity of the conductive structure 40 in the first through hole 31. Therefore, there is no specific limitation on the material and thickness of the protective layer 13.
[0080] Step S6044 : etching the conductive structure 40 in the second through hole 32 based on the patterned photoresist layer to remove the conductive structure 40 in the second through hole 32 .
[0081] For example, see Fig.11The conductive structure 40 in the second through hole 32 may be removed by, but is not limited to, a wet etching process or a dry etching process. In the present embodiment, the selected etching process only needs to ensure that, under the same etching conditions, the etching rate of the conductive layer 402 and the first metal barrier layer 401 is greater than the etching rate of the interlayer dielectric layer 12, so that when the conductive layer 402 and the first metal barrier layer 401 are removed, the integrity of the interlayer dielectric layer 12 is ensured. At this time, the conductive block 201 is an etching stop layer.
[0082] Step S6046 : forming a first electrode 501 , a resistive layer 502 and a second electrode 503 sequentially stacked along the oy direction in the second through hole 32 , wherein the first electrode 501 , the resistive layer 502 and the second electrode 503 together constitute a storage structure 50 .
[0083] For example, see Fig.12 It should be noted that the longitudinal section of the second through hole 32 is "T-shaped", that is, the second through hole 32 contains steps. Electron beam evaporation (E-beam evaporation), pulsed laser deposition (Pulsed Laser Deposition, PLD), and sputtering methods such as DC sputtering, radio frequency sputtering, and reactive sputtering can be used, but are not limited to any one of the methods, to form a first electrode filling the step plane opening in the second through hole 32 with the top surface of the conductive block 201 in the second through hole 32, and then any deposition method is used to form a resistive layer 502 and a second electrode 503 in the second through hole 32 in the oy direction above the first electrode 501. Subsequently, a planarization process such as chemical mechanical polishing (CMP) is used to remove all material layers above the top surface of the interlayer dielectric layer 12 along the ox direction to expose the top surface of the conductive structure 40 and the storage structure 50, and obtain the following. Fig. 9 A storage structure 50 is shown.
[0084] The resistive layer 502 is disposed between the first electrode 501 and the second electrode 503 . On this basis, a pulse voltage is applied to the resistive layer 502 , thereby generating a large resistance difference to store data.
[0085] In some embodiments, after forming the conductive structure 40 and the storage structure 50 in the interlayer dielectric layer 12, the step includes: forming a plurality of metal connection structures 20, the metal connection structure 20 including a conductive block 201 and a connection barrier layer 202 wrapping the bottom and side surfaces of the conductive block 201, wherein the plurality of metal connection structures 20 are respectively located on the top and bottom surfaces of the conductive structure 40 and the top and bottom surfaces of the storage structure 50.
[0086] In some embodiments, the preparation method can also be used to prepare other embedded memories, and it is only necessary to adjust the material layer constituting the storage structure in the second through hole 32 accordingly.
[0087] See also Fig.12 The present application provides a memory, which is prepared using the above-mentioned preparation method.
[0088] The memory of the present application includes a substrate 10, a dielectric layer 11, an interlayer dielectric layer 12, a conductive structure 40 and a storage structure 50, wherein the conductive structure 40 includes a conductive layer 402 and a first metal barrier layer 401 wrapping the bottom and side surfaces of the conductive layer 402, and the storage structure 50 includes a first electrode 501, a resistive layer 502, and a second electrode 503, wherein the resistive layer 502 is located between the first electrode 501 and the second electrode 503, wherein the top and bottom surfaces of the conductive structure 40 and the storage structure 50 are flush, and the interlayer dielectric layer 12 circumferentially surrounds the conductive structure 40 and the storage structure 50. The memory embeds a portion of the first electrode 501 of the storage structure 50 into the dielectric layer 11, and overall reduces the height of the storage structure 50 in the interlayer dielectric layer, that is, it will not affect the back-end process of the logic circuit area, and the total stacking thickness can meet the electrical performance requirements of the RRAN, and can also meet the requirements of the increasingly smaller process nodes.
[0089] The memory and the preparation method thereof of the present application have the following unexpected effects:
[0090] The present application provides a novel method for preparing RRAM, in which a first through hole and a second through hole are formed synchronously in an interlayer dielectric layer based on the same mask, and a conductive structure is formed in the first through hole at one time, which saves the number of masks and reduces the preparation cost. When preparing the storage structure, it is only necessary to etch back and reopen the second through hole, and fill the second through hole in sequence to form a first electrode, a resistive layer, and a second electrode, and the preparation of the storage structure can be completed. With the help of specific architectural technology, RRAM is stacked on the logic gate of CMOS, which can realize the technology of increasing memory storage on the basis of CMOS ultra-dense logic. The simplified process flow reduces the production steps and reduces the complexity of operation, effectively reduces the production cost, and improves the market competitiveness of the memory prepared by this process. At the same time, the simplification of steps and operations can shorten the production cycle of the memory without reducing the high performance and stability of the memory, providing potential for its long-term use and further development.
[0091] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0092] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.
Claims
1. A memory preparation method, characterized in that: include: Providing a substrate, the substrate comprising a first region and a second region arranged at intervals along a first direction parallel to a top surface of the substrate; the top surface of the substrate comprising a dielectric layer partially located in the first region and partially located in the second region; forming an interlayer dielectric layer on the dielectric layer; Based on the same photomask, a first through hole located in the first area and a second through hole located in the second area are simultaneously formed, wherein the first through hole and the second through hole both penetrate the interlayer dielectric layer and the dielectric layer along a second direction; After forming a conductive structure in the first through hole, forming a storage structure in the second through hole, the storage structure comprising a first electrode, a resistive switching layer and a second electrode sequentially stacked along the second direction.
2. The memory manufacturing method according to claim 1, characterized in that: Forming the first through hole and the second through hole includes: Forming a patterned photoresist layer on the top surface of the interlayer dielectric layer based on the same photomask, wherein the patterned photoresist layer includes a first opening located in the first area and a second opening located in the second area, wherein the first opening is used to define the first through hole, and the second opening is used to define the second through hole; Patterning the interlayer dielectric layer based on the patterned photoresist layer to form a first initial through hole located in the first area and a second initial through hole located in the second area; The openings of the first initial through hole and the second initial through hole are etched and increased to obtain the first through hole and the second through hole with a "T-shaped" longitudinal section.
3. The memory manufacturing method according to claim 2, characterized in that: The second through hole comprises a step therein; A storage structure is formed in the second through hole, comprising: forming a first electrode in the second through hole to fill the step plane opening in the second through hole; The resistive layer and the second electrode are sequentially formed above the first electrode in the second through hole.
4. The memory manufacturing method according to claim 3, characterized in that: Forming the resistive switching layer and the second electrode includes: Filling a resistive material above the first electrode in the second through hole; Etching back the resistive material to obtain a resistive layer whose top surface is lower than the top surface of the interlayer dielectric layer; Filling an electrode material above the resistance change layer in the second through hole; The electrode material is planarized to obtain a second electrode whose top surface is flush with the top surface of the interlayer dielectric layer.
5. The memory manufacturing method according to any one of claims 1 to 4, characterized in that: Forming a conductive structure in the first through hole includes: forming a first metal barrier layer covering the inner surface of the first through hole and the top surface of the substrate in the first through hole; A conductive layer that at least fills the first through hole is formed, and the conductive layer and the first metal barrier layer are used to jointly constitute the conductive structure.
6. The memory manufacturing method according to claim 5, characterized in that: During the process of forming the conductive structure in the first through hole, a conductive structure is simultaneously formed in the second through hole; forming a protective layer covering the conductive structure and the top surface of the interlayer dielectric layer; A patterned photoresist layer is formed on the protective layer, wherein the patterned photoresist layer includes an opening pattern exposing the conductive structure in the second through hole; The conductive structure in the second through hole is etched based on the patterned photoresist layer to remove the conductive structure in the second through hole.
7. The memory manufacturing method according to claim 6, characterized in that: The substrate includes a conductive block located in the second region; The conductive block is used as an etching stop layer to etch and remove the conductive structure in the second through hole.
8. The memory manufacturing method according to claim 7, characterized in that: Under the same etching conditions, the etching rates of the conductive layer and the first metal barrier layer are greater than the etching rate of the interlayer dielectric layer.
9. The memory manufacturing method according to claim 7, characterized in that: The bottom surface of the second through hole is located inside the top surface of the conductive block.
10. A memory, characterized in that: The memory is prepared by the memory preparation method according to any one of claims 1 to 9.