Manufacturing method of trench capacitor and semiconductor device

Abstract

The invention provides a manufacturing method of a trench capacitor and a semiconductor device, and the method comprises the steps: taking a patterned mask layer as a mask to etch a part of a second conductive layer to form an upper electrode plate, taking an etching barrier layer as a process stop layer to execute a maskless etching process, and etching an isolation dielectric layer to form an isolation structure covering the side wall of the upper electrode plate, and etching the intermediate dielectric layer and the first conductive layer to form the inter-polar-plate dielectric layer and the lower polar plate, so that the trench capacitor and an isolation structure which covers the side wall of the upper polar plate and prevents the upper polar plate and the lower polar plate from being in short circuit at the edges of the polar plates can be formed through one photomask, the use of the photomask is reduced, and the manufacturing cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for manufacturing a trench capacitor and a semiconductor device. Background Art

[0002] CMOS image sensors (CIS) have been used in many fields, such as machine vision, automobiles, analytical instruments, and absorption imaging. In such application fields, wider dynamic range (WDR) performance and better signal-to-noise ratio (SNR) can improve sensing accuracy under a wide range of lighting conditions. So far, several WDR technologies have been reported, among which the lateral overflow integrated capacitor (LOFIC) technology accumulates overflow electrons from the photodiode (PD) and the floating diffusion area (FD), which helps to increase the dynamic range of the image sensor and achieve clear display of high-brightness images. A CMOS image sensor with a resolution of more than 120 dB introduces a trench lateral overflow integrated capacitor (trench LOFIC) to improve the signal-to-noise ratio at the signal switching point. In the prior art, a trench MIM (metal-insulator-metal, metal layer-dielectric layer-metal layer) capacitor is used as a trench LOFIC. The trench capacitor increases the area of ​​the dielectric layer and increases the capacitance value of the capacitor.

[0003] In the process development of trench capacitors, there are many technical difficulties that need to be overcome. Among them, in order to avoid short-circuiting between the upper plate and the lower plate of the trench capacitor at the edge of the plate, two masks are required to form the trench capacitor, one of which is used to form the upper plate, and the other is used to form the lower plate and the plate sidewall isolation structure. The use of multiple masks greatly increases the manufacturing cost. Summary of the invention

[0004] The object of the present invention is to provide a method for manufacturing a trench capacitor and a semiconductor device, so as to solve the problem in the prior art that two masks are needed to form a trench capacitor, which greatly increases the manufacturing cost.

[0005] In order to solve the above technical problems, the present invention provides a method for manufacturing a trench capacitor, the method for manufacturing a trench capacitor comprising: Providing a front-end structure, wherein a first dielectric layer and a second dielectric layer are sequentially formed on the front-end structure, a first conductive structure and a second conductive structure are formed in the first dielectric layer, a groove is formed in the second dielectric layer, and the groove exposes the first conductive structure; forming a first conductive layer, an intermediate dielectric layer, and a second conductive layer in sequence on the second dielectric layer, wherein the first conductive layer, the intermediate dielectric layer, and the second conductive layer extend to cover the surface of the groove; forming a third dielectric layer on the second conductive layer, wherein the third dielectric layer fills the trench; forming an etching stop layer on the third dielectric layer; forming a patterned mask layer on the etch stop layer by using a photolithography process; Using the patterned mask layer as a mask, etching a portion of the etching barrier layer, a portion of the third dielectric layer, and a portion of the second conductive layer to form an upper electrode plate, exposing a portion of the intermediate dielectric layer, and removing the patterned mask layer; forming an isolation dielectric layer, wherein the isolation dielectric layer covers the etching stop layer, the sidewall of the upper plate and the intermediate dielectric layer; and, A maskless etching process is performed using the etching barrier layer as a process stop layer, the isolation dielectric layer is etched to form an isolation structure covering the side wall of the upper plate, the intermediate dielectric layer and the first conductive layer are etched to form an inter-plate dielectric layer and a lower plate, and a portion of the second dielectric layer is exposed.

[0006] Optionally, in the method for manufacturing the trench capacitor, the inter-plate dielectric layer protrudes from the upper plate, and the isolation structure extends to cover the sidewalls of the etch stop layer and the third dielectric layer and the surface of the inter-plate dielectric layer protruding from the upper plate.

[0007] Optionally, in the manufacturing method of the trench capacitor, in the maskless etching process performed with the etch barrier layer as a process stop layer, a partial thickness of the second dielectric layer is also etched so that the second dielectric layer includes a first portion located under the lower plate and an exposed second portion, wherein the thickness of the first portion is greater than the thickness of the second portion.

[0008] Optionally, in the method for manufacturing the trench capacitor, the method for manufacturing the trench capacitor further includes: forming a fourth dielectric layer, wherein the fourth dielectric layer covers the etching stop layer, the isolation structure and the second dielectric layer; forming a first opening exposing the upper electrode plate and a second opening exposing the second conductive structure in the fourth dielectric layer; and, A connection structure is formed, wherein the connection structure is connected to the upper electrode plate through the first opening and is connected to the second conductive structure through the second opening.

[0009] Optionally, in the method for manufacturing the trench capacitor, the isolation dielectric layer is a stacked multi-layer structure.

[0010] Optionally, in the method for manufacturing the trench capacitor, the isolation dielectric layer includes a stacked oxide layer and a nitride layer.

[0011] Optionally, in the method for manufacturing the trench capacitor, the material of the etching stop layer is silicon nitride, the material of the third dielectric layer is silicon oxide, and the material of the second dielectric layer includes silicon oxide.

[0012] The present invention also provides a semiconductor device, comprising: A front-end structure, wherein a first dielectric layer and a second dielectric layer are sequentially formed on the front-end structure, a first conductive structure and a second conductive structure are formed in the first dielectric layer, a groove is formed in the second dielectric layer, and the groove exposes the first conductive structure; A trench capacitor covering the surface of the trench and extending to cover a portion of the upper surface of the second dielectric layer, the trench capacitor comprising a lower plate, an inter-plate dielectric layer and an upper plate stacked in sequence; and An isolation structure covers the side wall of the upper plate.

[0013] Optionally, in the semiconductor device, the semiconductor device also includes: a third dielectric layer and an etch barrier layer covering the upper plate; the inter-plate dielectric layer protrudes from the upper plate, and the isolation structure extends to cover the side walls of the etch barrier layer and the third dielectric layer and the surface of the inter-plate dielectric layer protruding from the upper plate.

[0014] Optionally, in the semiconductor device, the semiconductor device further includes: a fourth dielectric layer covering the etching stop layer, the isolation structure and the second dielectric layer, wherein the fourth dielectric layer is formed with a first opening exposing the upper electrode plate and a second opening exposing the second conductive structure; and A connection structure is connected to the upper electrode plate through the first opening, and is connected to the second conductive structure through the second opening.

[0015] In the manufacturing method and semiconductor device of the trench capacitor provided by the present invention, a portion of the second conductive layer is etched using a patterned mask layer as a mask to form an upper electrode plate, a maskless etching process is performed using an etching barrier layer as a process stop layer, an isolation dielectric layer is etched to form an isolation structure covering the side wall of the upper electrode plate, and an intermediate dielectric layer and a first conductive layer are etched to form an inter-electrode dielectric layer and a lower electrode plate. A trench capacitor and an isolation structure covering the side wall of the upper electrode plate and preventing the upper electrode plate and the lower electrode plate from short-circuiting at the edge of the electrode plate can be formed by a single photomask, thereby reducing the use of a photomask and lowering the manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a cross-sectional schematic diagram of a structure after an etching stop layer is formed in the method for manufacturing a trench capacitor according to an embodiment of the present invention.

[0017] Figure 2 It is a cross-sectional schematic diagram of the structure after forming an isolation dielectric layer in the method for manufacturing a trench capacitor according to an embodiment of the present invention.

[0018] Figure 3 It is a schematic cross-sectional view of the structure after the trench capacitor is formed in the method for manufacturing the trench capacitor according to the embodiment of the present invention.

[0019] Figure 4 FIG. 4 is a schematic cross-sectional view of a structure after forming a connection structure in a method for manufacturing a trench capacitor according to an embodiment of the present invention.

[0020] The reference numerals are described as follows: 100-front end structure; 110-first dielectric layer; 111-first NDC material layer; 112-first silicon oxide material layer; 120-second dielectric layer; 120A-first portion; 120B-second portion; 121-second NDC material layer; 122-second silicon oxide material layer; 130-first conductive structure; 131-second conductive structure; 140-groove; 150-first conductive layer; 151-middle dielectric layer; 152-second Two conductive layers; 160-third dielectric layer; 170-etching barrier layer; 180-patterned mask layer; 190-upper plate; 191-inter-plate dielectric layer; 192-lower plate; 193-trench capacitor; 200-isolation dielectric layer; 201-oxide layer; 202-nitride layer; 210-isolation structure; 220-fourth dielectric layer; 230-first opening; 231-second opening; 240-connection structure; 10-semiconductor device. DETAILED DESCRIPTION

[0021] In order to form the upper plate and the lower plate of the trench capacitor and the isolation structure to avoid short circuit at the edge of the plate, the prior art requires two masks, one for forming the upper plate and one for forming the lower plate and the plate sidewall isolation structure. The use of multiple masks greatly increases the manufacturing cost.

[0022] The present application utilizes a photomask to form a trench capacitor and an isolation structure that covers the sidewall of an upper plate and prevents the upper plate and the lower plate from being short-circuited at the edge of the plate, thereby reducing the use of photomasks and lowering manufacturing costs.

[0023] The following is a further detailed description of the manufacturing method of the trench capacitor and the semiconductor device proposed in the present invention in combination with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are in a very simplified form and are not in precise proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0024] The terms used in the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. Unless otherwise defined in the present application document, the technical terms or scientific terms used in the present invention should be the common meaning understood by people with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the present specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limit, but indicate that there is at least one. "Multiple" or "several" means two or more. Unless otherwise specified, words such as "upper / upper layer", "lower / lower layer" and the like are only for the convenience of explanation and are not limited to one position or one spatial orientation. Words such as "include" or "comprise" and the like mean that the elements or objects appearing in front of "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and the like are not limited to physical or mechanical connections, and can include electrical connections, whether direct or indirect. The singular forms "a", "said" and "the" used in the present specification and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0025] For details, please refer to Figures 1 to 4 , which is a schematic cross-sectional view of a structure formed by executing the method for manufacturing a trench capacitor according to an embodiment of the present invention.

[0026] like Figure 1 As shown, a front-end structure 100 is provided, and the front-end structure 100 can be formed by a semiconductor front-end process. The front-end structure 100 can include, for example, a semiconductor substrate (not shown in the figure), a photodiode (not shown in the figure) formed in the semiconductor substrate, and the like.

[0027] A first dielectric layer 110 and a second dielectric layer 120 are sequentially formed on the front-end structure 100, a first conductive structure 130 and a second conductive structure 131 are formed in the first dielectric layer 110, a groove 140 is formed in the second dielectric layer 120, and the groove 140 exposes the first conductive structure 130. In other embodiments of the present application, before forming the first dielectric layer 110, other structures may be formed on the front-end structure 100, for example, one or more dielectric layers (not shown in the figure) may be formed on the front-end structure 100, and a conductive structure may be formed in each of the dielectric layers.

[0028] The materials of the first dielectric layer 110 and the second dielectric layer 120 may be the same or different; the first dielectric layer 110 and the second dielectric layer 120 may be a single-layer structure or a stacked multi-layer structure. In the embodiment of the present application, the first dielectric layer 110 includes a stacked first NDC (Nitride Doped Silicon Carbide) material layer 111 and a first silicon oxide material layer 112, and the second dielectric layer 120 includes a stacked second NDC material layer 121 and a second silicon oxide material layer 122.

[0029] The first conductive structure 130 and the second conductive structure 131 may be made of the same material and may be formed by the same process steps. Specifically, the first conductive structure 130 and the second conductive structure 131 may include a diffusion barrier layer (not shown in the figure) and a metal layer (not shown in the figure), the material of the metal layer is, for example, copper, and further, the copper metal layer may include a copper seed layer and a copper electroplating layer.

[0030] like Figure 1 As shown, in the embodiment of the present application, two grooves 140 are formed in the second dielectric layer 120, and each groove 140 exposes the first conductive structure 130. Specifically, the groove 140 extends from the surface of the second silicon oxide material layer 122 to the bottom of the second NDC material layer 121, exposing the first conductive structure 130.

[0031] Please continue to refer to Figure 1 Then, a first conductive layer 150, an intermediate dielectric layer 151 and a second conductive layer 152 are sequentially formed on the second dielectric layer 120, wherein the first conductive layer 150 extends to cover the surface of the groove 140, the intermediate dielectric layer 151 covers the first conductive layer 150, and the second conductive layer 152 covers the intermediate dielectric layer 151, that is, the intermediate dielectric layer 151 and the second conductive layer 152 also extend to cover the surface of the groove 140.

[0032] In the embodiment of the present application, the first conductive layer 150 and the second conductive layer 152 are made of the same material, titanium nitride; the material of the intermediate dielectric layer 151 is a high dielectric constant (high K) material. In other embodiments of the present application, the first conductive layer 150 and the second conductive layer 152 may also be other conductive materials.

[0033] Next, a third dielectric layer 160 is formed on the second conductive layer 152, and the third dielectric layer 160 fills the groove 140. In the embodiment of the present application, the third dielectric layer 160 fills the groove 140 and protrudes from the groove 140. The third dielectric layer 160 can be formed by a deposition process, and its material is silicon oxide.

[0034] like Figure 1 As shown, in the embodiment of the present application, then, an etch stop layer 170 is formed on the third dielectric layer 160, and the etch stop layer 170 covers the third dielectric layer 160, which can be formed by a deposition process. Here, the etch stop layer 170 is made of silicon nitride.

[0035] Next, a patterned mask layer 180 is formed on the etch stop layer 170 by using a photolithography process, and the patterned mask layer 180 covers a portion of the etch stop layer 170. In the embodiment of the present application, the projection of the patterned mask layer 180 on the second dielectric layer 120 covers the groove 140.

[0036] Please refer to Figure 2 , using the patterned mask layer 180 as a mask, a portion of the etching stop layer 170, a portion of the third dielectric layer 160 and a portion of the second conductive layer 152 are etched to form an upper plate 190. The etching stops on the surface of the intermediate dielectric layer 151, exposing a portion of the intermediate dielectric layer 151. In the embodiment of the present application, using the patterned mask layer 180 as a mask, the etching stop layer 170, the third dielectric layer 160 and the second conductive layer 152 can be etched by one or more etching processes. By etching a portion of the etching stop layer 170, a portion of the third dielectric layer 160 and a portion of the second conductive layer 152, a step difference is formed on the surface of the device structure, and the exposed surface of the etching stop layer 170 is higher than the exposed surface of the intermediate dielectric layer 151. Here, the upper plate 190 of the trench capacitor is formed by using a photomask.

[0037] Next, the patterned mask layer 180 is removed. An isolation dielectric layer 200 is formed, and the isolation dielectric layer 200 covers the remaining etching stop layer 170, the sidewall of the upper plate 190 and the intermediate dielectric layer 151. The isolation dielectric layer 200 can be a single-layer structure or a stacked multi-layer structure. In the embodiment of the present application, the isolation dielectric layer 200 includes a stacked oxide layer 201 and a nitride layer 202. Figure 2As shown, the oxide layer 201 covers the etch stop layer 170, and extends to cover the sidewall of the upper plate 190 and the intermediate dielectric layer 151, and the nitride layer 202 covers the oxide layer 201. The surface of the portion of the isolation dielectric layer 200 covering the etch stop layer 170 is higher than the surface of the portion of the isolation dielectric layer 200 covering the intermediate dielectric layer 151, and the surface height of the isolation dielectric layer 200 gradually decreases along the etch stop layer 170, the sidewall of the upper plate 190 and the intermediate dielectric layer 151.

[0038] like Figure 3 As shown, in the embodiment of the present application, then, a maskless etching process is performed with the etching barrier layer 170 as a process stop layer, the isolation dielectric layer 200 is etched to form an isolation structure 210 covering the side wall of the upper plate 190, and the intermediate dielectric layer 151 and the first conductive layer 150 are etched to form an inter-plate dielectric layer 191 and a lower plate 192, thereby obtaining a trench capacitor 193. Here, the side wall of the inter-plate dielectric layer 191 is flush with the side wall of the lower plate 192. At the same time, a portion of the second dielectric layer 120 is exposed.

[0039] Here, the lower plate 192 of the trench capacitor 193 and the isolation structure 210 for preventing the upper plate 190 and the lower plate 192 from shorting at the plate edge are formed by a maskless etching process. Therefore, in the manufacturing method of the trench capacitor provided in the embodiment of the present application, the trench capacitor 193 and the isolation structure 210 for covering the side wall of the upper plate 190 and preventing the upper plate 190 and the lower plate 192 from shorting at the plate edge can be formed by a photomask, which reduces the use of photomasks and reduces manufacturing costs.

[0040] Please continue to refer to Figure 3 , the inter-plate dielectric layer 191 protrudes from the upper plate 190, the isolation structure 210 extends to cover the sidewalls of the etch stop layer 170 and the third dielectric layer 160, and the surface of the inter-plate dielectric layer 191 protruding from the upper plate 190. That is, here, the isolation structure 210 extends from the sidewall of the etch stop layer 170 to cover the sidewall of the third dielectric layer 160, the sidewall of the upper plate 190, and the surface of the inter-plate dielectric layer 191. Among them, the surface height of the isolation structure 210 gradually decreases from the sidewall of the etch stop layer 170 to the surface of the inter-plate dielectric layer 191.

[0041] In the embodiment of the present application, in the maskless etching process performed with the etching barrier layer 170 as the process stop layer, a partial thickness of the second dielectric layer 120 is also etched, so that the second dielectric layer 120 includes a first portion 120A located under the lower electrode 192 and an exposed second portion 120B, wherein the thickness of the first portion 120A is greater than the thickness of the second portion 120B. In the embodiment of the present application, specifically, a partial thickness of the second silicon oxide material layer 122 is removed by etching. By removing a partial thickness of the second dielectric layer 120, the process margin for forming the lower electrode 192 is increased, the process is simplified, and the manufacturing cost is reduced.

[0042] Please refer to Figure 4 Furthermore, the manufacturing method of the trench capacitor further includes: forming a fourth dielectric layer 220, wherein the fourth dielectric layer 220 covers the etching stop layer 170, the isolation structure 210 and the second dielectric layer 120, that is, the fourth dielectric layer 220 covers the surface of the device structure. The fourth dielectric layer 220 can be formed by a deposition process, and its material is, for example, silicon oxide.

[0043] Next, a first opening 230 exposing the upper electrode plate 190 and a second opening 231 exposing the second conductive structure 131 are formed in the fourth dielectric layer 220. Specifically, the first opening 230 extends from the surface of the fourth dielectric layer 220 to the etching stop layer 170 and the third dielectric layer 160, exposing the upper electrode plate 190. The second opening 231 extends from the surface of the fourth dielectric layer 220 to the second dielectric layer 120, exposing the second conductive structure 131. Here, a patterned mask layer can be formed by a photolithography process, and then the first opening 230 and the second opening 231 can be formed by one or more etching processes.

[0044] Please continue to refer to Figure 4 , forming a connection structure 240, the connection structure 240 is connected to the upper electrode plate 190 through the first opening 230, and is connected to the second conductive structure 131 through the second opening 231. Specifically, the connection structure 240 can be formed by depositing a conductive material layer (not shown in the figure). The conductive material layer fills the first opening 230 and the second opening 231 and extends to cover the surface of the fourth dielectric layer 220, and then, the conductive material layer is etched to form the connection structure 240.

[0045] Please continue to refer to Figure 3 and Figure 4Accordingly, an embodiment of the present application further provides a semiconductor device, the semiconductor device 10 comprising: a front-end structure 100, a first dielectric layer 110 and a second dielectric layer 120 are sequentially formed on the front-end structure 100, a first conductive structure 130 and a second conductive structure 131 are formed in the first dielectric layer 110, a groove 140 is formed in the second dielectric layer 120, the groove 140 exposes the first conductive structure 130; a trench capacitor 193 covering the surface of the groove 140 and extending to cover a portion of the upper surface of the second dielectric layer 120, the trench capacitor 193 comprising a lower plate 192, an inter-plate dielectric layer 191 and an upper plate 190 stacked in sequence; and an isolation structure 210 covering the side wall of the upper plate 190.

[0046] like Figure 3 and Figure 4 As shown, the semiconductor device 10 further includes: a third dielectric layer 160 and an etching stop layer 170 covering the upper plate 190; the inter-plate dielectric layer 191 protrudes from the upper plate 190, and the isolation structure 210 extends to cover the sidewalls of the etching stop layer 170 and the third dielectric layer 160, as well as the surface of the inter-plate dielectric layer 191 protruding from the upper plate 190. In the embodiment of the present application, the inner surface of the isolation structure 210 extends from the sidewall of the etching stop layer 170 to cover the sidewall of the third dielectric layer 160, the sidewall of the upper plate 190 and the surface of the inter-plate dielectric layer 191, forming an "L" shape. The height of the outer surface of the isolation structure 210 gradually decreases from the sidewall of the etching stop layer 170 to the surface of the inter-plate dielectric layer 191.

[0047] like Figure 4 As shown, further, the semiconductor device 10 also includes: a fourth dielectric layer 220 covering the etching stop layer 170, the isolation structure 210 and the second dielectric layer 120, and a first opening 230 exposing the upper electrode plate 190 and a second opening 231 exposing the second conductive structure 131 are formed in the fourth dielectric layer 220; and a connecting structure 240, the connecting structure 240 is connected to the upper electrode plate 190 through the first opening 230, and is connected to the second conductive structure 131 through the second opening 231.

[0048] In the embodiment of the present application, a trench capacitor 193 and an isolation structure 210 covering the side wall of the upper plate 190 and preventing the upper plate 190 and the lower plate 192 from short-circuiting at the edge of the plates can be formed by a single photomask, thereby reducing the use of photomasks and lowering manufacturing costs.

[0049] In the present application, references to "one embodiment" or "some embodiments" mean that features, structures, or characteristics described in conjunction with the embodiment are included in at least one embodiment, at least some embodiments, of the present application. Therefore, the appearance of the phrases "in one embodiment" or "in some embodiments" in various places of the present application does not necessarily refer to the same or the same embodiments. In addition, in one or more embodiments, features, structures, or characteristics may be combined in any suitable combination and / or sub-combination.

[0050] Although some specific embodiments of the present application have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present application. The various embodiments of the present application may be combined in any manner without departing from the spirit and scope of the present application. It will also be appreciated by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present application. The scope of the present application is defined by the appended claims.

Claims

1. A method for manufacturing a trench capacitor, characterized in that: The method for manufacturing the trench capacitor comprises: Providing a front-end structure, wherein a first dielectric layer and a second dielectric layer are sequentially formed on the front-end structure, a first conductive structure and a second conductive structure are formed in the first dielectric layer, a groove is formed in the second dielectric layer, and the groove exposes the first conductive structure; forming a first conductive layer, an intermediate dielectric layer, and a second conductive layer in sequence on the second dielectric layer, wherein the first conductive layer, the intermediate dielectric layer, and the second conductive layer extend to cover the surface of the groove; forming a third dielectric layer on the second conductive layer, wherein the third dielectric layer fills the trench; forming an etching stop layer on the third dielectric layer; forming a patterned mask layer on the etch stop layer by using a photolithography process; Using the patterned mask layer as a mask, etching a portion of the etching barrier layer, a portion of the third dielectric layer, and a portion of the second conductive layer to form an upper electrode plate, exposing a portion of the intermediate dielectric layer, and removing the patterned mask layer; forming an isolation dielectric layer, wherein the isolation dielectric layer covers the etching stop layer, the sidewall of the upper plate and the intermediate dielectric layer; and, A maskless etching process is performed using the etching barrier layer as a process stop layer, the isolation dielectric layer is etched to form an isolation structure covering the side wall of the upper plate, the intermediate dielectric layer and the first conductive layer are etched to form an inter-plate dielectric layer and a lower plate, and a portion of the second dielectric layer is exposed.

2. The method for manufacturing a trench capacitor according to claim 1, wherein: The inter-plate dielectric layer protrudes from the upper plate, and the isolation structure extends to cover the sidewalls of the etching stop layer and the third dielectric layer as well as the surface of the inter-plate dielectric layer protruding from the upper plate.

3. The method for manufacturing a trench capacitor according to claim 1, wherein: In the maskless etching process performed with the etching barrier layer as a process stop layer, a partial thickness of the second dielectric layer is also etched so that the second dielectric layer includes a first portion located under the lower electrode plate and an exposed second portion, wherein the thickness of the first portion is greater than the thickness of the second portion.

4. The method for manufacturing a trench capacitor according to any one of claims 1 to 3, wherein: The method for manufacturing the trench capacitor further includes: forming a fourth dielectric layer, wherein the fourth dielectric layer covers the etching stop layer, the isolation structure and the second dielectric layer; forming a first opening exposing the upper electrode plate and a second opening exposing the second conductive structure in the fourth dielectric layer; and, A connection structure is formed, wherein the connection structure is connected to the upper electrode plate through the first opening and is connected to the second conductive structure through the second opening.

5. The method for manufacturing a trench capacitor according to any one of claims 1 to 3, wherein: The isolation dielectric layer is a stacked multi-layer structure.

6. The method for manufacturing a trench capacitor according to any one of claims 1 to 3, wherein: The isolation dielectric layer includes a stacked oxide layer and a nitride layer.

7. The method for manufacturing a trench capacitor according to any one of claims 1 to 3, wherein: The material of the etching stop layer is silicon nitride, the material of the third dielectric layer is silicon oxide, and the material of the second dielectric layer includes silicon oxide.

8. A semiconductor device, characterized in that: The semiconductor device comprises: A front-end structure, wherein a first dielectric layer and a second dielectric layer are sequentially formed on the front-end structure, a first conductive structure and a second conductive structure are formed in the first dielectric layer, a groove is formed in the second dielectric layer, and the groove exposes the first conductive structure; A trench capacitor covering the surface of the trench and extending to cover a portion of the upper surface of the second dielectric layer, the trench capacitor comprising a lower plate, an inter-plate dielectric layer and an upper plate stacked in sequence; and An isolation structure covers the side wall of the upper plate.

9. The semiconductor device according to claim 8, characterized in that The semiconductor device also includes: a third dielectric layer and an etch stop layer covering the upper plate; the inter-plate dielectric layer protrudes from the upper plate, and the isolation structure extends to cover the side walls of the etch stop layer and the third dielectric layer and the surface of the inter-plate dielectric layer protruding from the upper plate.

10. The semiconductor device according to claim 9, wherein: The semiconductor device further comprises: a fourth dielectric layer covering the etching stop layer, the isolation structure and the second dielectric layer, wherein the fourth dielectric layer is formed with a first opening exposing the upper electrode plate and a second opening exposing the second conductive structure; and A connection structure is connected to the upper electrode plate through the first opening, and is connected to the second conductive structure through the second opening.

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