FFT hardware acceleration circuit of complex multiplication unit based on three-section CORDIC algorithm

Abstract

The invention relates to an FFT hardware acceleration circuit of a complex multiplication unit based on a three-section CORDIC algorithm, and belongs to the field of wireless communication circuits. The circuit comprises an address generation unit, a random storage unit, a rotation angle generation unit, a complex multiplication unit based on a three-section CORDIC algorithm, a radix-4 butterfly unit, an output processing unit and a reverse order unit. Wherein the complex multiplication unit based on the three-section CORDIC algorithm adopts a pipeline structure, the iteration process is divided into three stages, an ROM table is used for storing a pre-calculated iteration result, and complex multiplication operation is achieved through angle dual-polarization coding and shift addition operation. Compared with a traditional FFT algorithm, the method has the advantages of being high in operation speed, small in storage pressure, small in resource consumption and the like, and is suitable for signal processing tasks in the fields of wireless communication, image processing and the like. The method aims at solving the problems that a traditional FFT algorithm is large in calculation amount, large in storage pressure, slow in operation and large in resource consumption.

Description

Technical Field

[0001] The invention belongs to the field of wireless communication circuits and relates to an FFT hardware acceleration circuit of a complex multiplication unit based on a three-segment CORDIC algorithm. Background Art

[0002] FFT is widely used in various fields such as communication and image processing, and often occupies most of the chip area in the hardware implementation system. Improving FFT processing speed, reducing storage pressure, and low latency have become research hotspots in the field of digital signal processing.

[0003] The CORDIC algorithm is a numerical approximation iterative algorithm used to calculate some commonly used basic operation functions and arithmetic operations. The basic idea is to deflect continuously according to a series of angles related to the operation base, so as to approximate the required rotation angle, and decompose a series of complex mathematical operations into some simple and easy-to-implement basic operations in hardware, such as addition and shift, so as to reduce the complexity of the design and save hardware resources. This algorithm was first proposed by JD Volder and others in the design of American aviation control systems in 1959. In 1971, JSWalther extended it to the calculation of various elementary functions and proposed a unified CORDIC algorithm form, which unified circular rotation, hyperbolic rotation, and linear rotation into the same CORDIC iterative equation, so that the same hardware can realize multifunctional operations, thus showing a broad application prospect. The functions that the CORDIC algorithm can calculate include multiplication, division, square root, sine, cosine, inverse tangent, vector rotation (i.e. complex multiplication) and exponential operations. In recent years, with the continuous development of VLSI technology, the CORDIC algorithm has attracted more and more attention from scientific researchers, and the research and application of this algorithm has become more and more extensive. At present, the CORDIC algorithm has been successfully used in many fields such as FFT, DCT and other signal processing, image processing, and linear systems.

[0004] The commonly used complex multiplication operation is a traditional FFT hardware, which restricts the operating frequency of the circuit system, and at the same time requires more hardware resources, and is sometimes even difficult to implement. The CORDIC algorithm was created to solve these problems. It starts with the algorithm itself and decomposes it into some simple shift and add operations, thereby improving the system's operating speed. At the same time, the CORDIC algorithm is a regularized algorithm, which meets the hardware's requirements for algorithm modularization and regularization, can give full play to the hardware advantages and utilize hardware resources, and is an ideal solution for combining algorithms with hardware. Summary of the invention

[0005] In view of this, an object of the present invention is to provide an FFT hardware acceleration circuit of a complex multiplication unit based on a three-stage CORDIC algorithm.

[0006] In order to achieve the above object, the present invention provides the following technical solutions:

[0007] An FFT hardware acceleration circuit of a complex multiplication unit based on a three-stage CORDIC algorithm, comprising:

[0008] The address generating unit is respectively connected with the random storage unit, the rotation angle generating unit, the complex multiplication unit based on the three-stage CORDIC algorithm, the radix-quad butterfly unit, the output processing unit and the reverse order unit, and is used to control the working timing of the overall circuit;

[0009] A random storage unit, including a real memory and an imaginary memory, having a read and write port, connected to the address generation unit, and used for storing the operation data of the complex multiplication unit based on the three-stage CORDIC algorithm;

[0010] A rotation angle generating unit, connected to the address generating unit, for generating a rotation angle required for FFT operation;

[0011] A complex multiplication unit based on a three-stage CORDIC algorithm includes an angle bipolar encoding, a shift-addition unit, a merging and iterating unit, a ROM table, and an angle interval mapping, wherein an input end is connected to a rotation angle generating unit, and an output end is connected to a base-four butterfly unit, for performing complex multiplication operations;

[0012] A radix-quad butterfly unit, whose input end is connected to a random storage unit and a complex multiplication unit based on a three-stage CORDIC algorithm, and whose output end is connected to a reversal unit, is used to perform an FFT operation;

[0013] An output processing unit, connected to the radix-quad butterfly unit, for processing the FFT operation result;

[0014] The reversing unit is connected to the radix-quad butterfly unit and the output processing unit, and is used for reversing the FFT operation result.

[0015] Furthermore, in the complex multiplication unit based on the three-stage CORDIC algorithm, angle polarization coding is used to perform angle polarization re-coding on the input angle, so as to perform folding mapping by utilizing the symmetry of the sine and cosine functions.

[0016] Furthermore, in the complex multiplication unit based on the three-stage CORDIC algorithm, the shift-addition unit is used to perform shift-addition operations to realize complex multiplication operations.

[0017] Furthermore, in the complex multiplication unit based on the three-stage CORDIC algorithm, the merging iteration unit is used to divide the iteration process into three stages to improve the operation efficiency.

[0018] Furthermore, in the complex multiplication unit based on the three-stage CORDIC algorithm, the ROM table is used to store pre-calculated iteration results to speed up the calculation process.

[0019] Furthermore, in the complex multiplication unit based on the three-segment CORDIC algorithm, the angle interval mapping is used to determine the addressing address of the ROM table according to the value of the input angle.

[0020] Furthermore, the complex multiplication unit based on the three-stage CORDIC algorithm adopts a pipeline structure, including three operation channels of x, y and θ, each channel includes multiple operation stages, and each operation stage consists of two adders, two shifters and a decision device.

[0021] Further, the working process of the FFT hardware acceleration circuit is as follows:

[0022] The address generation unit generates an initialization signal and inputs the time domain data into the random storage unit for initialization;

[0023] The address generating unit generates a first-level operation indication signal to control the base quad-butterfly unit and the rotation angle generating unit to perform the first-level operation;

[0024] Perform the second level, third level, and so on until the log4N level of operations in sequence;

[0025] The address generating unit generates an output result valid signal, and controls the reverse order unit to perform reverse order processing on the data processed by the radix-quad butterfly unit and output the data.

[0026] The beneficial effects of the present invention are:

[0027] (1) The three-stage CORDIC algorithm decomposes complex multiplication into simple shift-add operations and uses a pipeline structure for parallel processing, which significantly improves the FFT operation speed.

[0028] (2) Using ROM tables to store pre-calculated iteration results reduces the data storage requirements during the calculation process and effectively reduces storage pressure.

[0029] (3) The CORDIC algorithm decomposes complex mathematical operations into simple hardware operations, reducing hardware resource consumption and improving circuit integration.

[0030] (4) The use of pipeline structure and ROM table reduces power consumption during the calculation process and extends the battery life of the device.

[0031] (5) The CORDIC algorithm has a high degree of regularization and is easy to implement in hardware, which reduces the difficulty of circuit design.

[0032] (6) The present invention can be used in various FFT algorithms and has good versatility.

[0033] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0035] Figure 1 This is a schematic diagram of three-stage CORDIC complex multiplication;

[0036] Figure 2 It is a schematic diagram of the merged iterative structure;

[0037] Figure 3 It is a schematic diagram of the multiplication pipeline structure;

[0038] Figure 4 It is the operation flow chart of the present invention. DETAILED DESCRIPTION

[0039] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0040] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0041] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0042] See also Figure 1 to Figure 4 The present invention provides an FFT hardware acceleration circuit of a complex multiplication unit based on a three-stage CORDIC algorithm. Aiming at the problems of high storage pressure, slow operation and large resource consumption caused by excessive number of calculation points in the traditional FFF algorithm, a complex multiplication unit based on a three-stage CORDIC algorithm is proposed.

[0043] To achieve the above purpose, the technical solution of the present invention is: an FFT hardware acceleration circuit for the field of signal processing, including an address generation unit, a random storage unit, a rotation angle generation unit, a complex multiplication unit based on a three-segment CORDIC algorithm, a radix-quad butterfly unit, an output processing unit and a reversing unit.

[0044] The address generating unit is respectively connected with the random storage unit, the rotation angle generating unit, the complex multiplication unit based on the three-stage CORDIC algorithm, the radix-quad butterfly unit, the output processing unit and the reverse order unit, and is used to control the working timing of the overall circuit.

[0045] The random storage unit includes a real memory and an imaginary memory, and also includes two ports for reading and writing. The read and write addresses are given by the address generation unit, and the operation data of the complex multiplication unit based on the three-stage CORDIC algorithm is stored.

[0046] The input end of the radix-quad butterfly operation unit receives the read data of the real memory and the imaginary memory, which includes the time domain data in the random memory unit or the operation intermediate data. The output end of the radix-quad butterfly operation unit is connected to the input end of the complex multiplication unit based on the three-stage CORDIC algorithm, and the calculated data input is sent to the complex multiplication unit based on the three-stage CORDIC algorithm.

[0047] The complex multiplication unit based on the three-stage CORDIC algorithm comprises five parts: angle polarization coding, shift addition unit, merging and iteration unit, ROM table and angle interval mapping.

[0048] Unlike the basic CORDIC algorithm, θ is not selected n= arctan(2 -n ) Instead of performing rotation superposition at special angles like this, first perform coordinate rotation starting from the initial angle β0, and then select the rotation angle each time as 2 -2 rad, 2 - 3 rad, ···, 2 -k rad and other angles, that is, the rotation direction is directly determined by the bit value r k when represented in the binary form of θ. When r k = 1, rotate counterclockwise by 2 -k rad, and when r k = -1, rotate clockwise by 2 -k rad. Expand tan(2 -k ) using Taylor series to get:

[0049]

[0050] When 2 -k is small enough (k > N / 3), where k represents the iteration series and N represents the angle coding bit width, tan(2 -k ) ≈ 2 -k can be approximated. Here, k is the iteration series and N is the angle coding bit width. The resulting approximation error can be less than the quantization error caused by the finite precision representation of N, without affecting the calculation accuracy. When k < N / 3, the iteration results after various possible rotation combinations of the high-order bit values such as 2 -2 rad, 2 -3 rad, ···, 2 -5 rad for the initial angle can be calculated in advance and stored in the ROM, and the results are directly addressed by the high-order bit values for the next iteration operation. Based on the above analysis, the three-stage CORDIC complex multiplication algorithm divides the iteration into three stages to complete.

[0051] The complex multiplication operation of the complex multiplication unit based on the three-stage CORDIC algorithm is carried out according to the following steps:

[0052] Step 1: Determine the rotation angle of the required rotation factor according to the number of points in the FFT operation and send it to the CORDIC complex multiplication unit.

[0053]

[0054] Among them, β represents the input angle, b k represents the coding bit value, and β0 represents the coding initial angle;

[0055] Step 2: For the input angle of [0,π / 4), angle polarization recoding is performed, and the coding conversion is as shown above. Where β is the input angle, bk is the coding bit value, and β0 is the initial coding angle. For the input angle of (π / 4,π / 2), due to the symmetry of the sine and cosine functions, the corresponding sine and cosine values ​​are obtained by folding mapping, as shown in Table 1.

[0056] Table 1

[0057]

[0058] Step 3: When the number of iterations is less than or equal to N / 3, a lookup table is established to address the sine and cosine values ​​of this stage. When the number of iterations is greater than N / 3 and less than (N-1) / 2, the encoded binary decimal is used for step-by-step iteration. When the number of iterations is greater than (N-1) / 2, the rotation angle is very small and can be ignored, so the iterations of this stage can be merged. The stage processing is shown in the following formula, where x i+n is the real part value of the i+nth level iteration, y i+n is the imaginary part value of the i+nth level iteration, x i is the real part of the i-th level iteration, y i is the imaginary part value of the i-th level iteration, r i is the polarization encoding position.

[0059]

[0060] Among them, x i+n represents the real part value of the i+nth level iteration, y i+n represents the imaginary part of the i+nth level iteration, x i represents the real part of the i-th level iteration, y i represents the imaginary part of the i-th level iteration, r i Indicates the position of the polarization code; the embodiment of the present invention discloses an FFT hardware acceleration circuit of a complex multiplication unit based on a three-segment CORDIC algorithm, such as Figure 3 The following steps are shown:

[0061] The address generating unit first generates an initialization signal, and the time domain data that needs to be subjected to N-point FFT operation is input into one of the real random storage unit and the imaginary random storage unit for initialization; after the input is completed, the address generating unit generates a first-level operation indication signal, which is respectively input into the MUX selection unit, the radix-four butterfly operation unit and the rotation angle generation unit, and at the same time, the required address is generated according to the address rule of the first-level operation; after the first-level operation is completed, the FFT processor module enters the second-level operation, and the address generating unit generates a second-level operation indication signal, which is respectively input into the MUX selection unit, the radix-four butterfly operation unit and the rotation angle generation unit, and at the same time, the required address is generated according to the address rule of the second-level operation, and the entire FFT processor module will perform the operation according to the second level; according to this step, when the FFT processor completes the operation of the log4Nth level, the address generating unit will generate an output result valid signal, and the reverse processing unit will read the data processed by the radix-four butterfly unit, perform reverse processing, and then output it.

[0062] like Figure 1 As shown, the complex multiplication unit based on the three-stage CORDIC algorithm includes five parts: angle polarization coding, shift addition unit, merging iteration unit, ROM table and angle interval mapping. The complex multiplication unit based on the three-stage CORDIC algorithm proposed in this paper is used for FFT operation. It does not require complex multiplication operation. Only 10 rotations and 8 complex additions are needed to complete the operation of a radix-4 FFT unit. The figure represents the real part and imaginary part of the input data, respectively, and represents the angle value of the rotation factor for operation.

[0063] like Figure 2 and Figure 3 As shown, the complex multiplication unit based on the three-stage CORDIC algorithm adopts a pipeline structure, which is divided into three operation channels, x, y and θ. The x channel corresponds to the real part of the time domain data, the y channel corresponds to the imaginary part of the time domain data, and θ corresponds to the required rotation factor angle. The number of pipeline stages is determined according to the data accuracy requirements. Each stage of operation is composed of two adders, two shifters and a decision device, wherein the shift number of the shifter at each stage is equivalent to the current stage minus 1, and the input of each x-way adder is the x-way data of this stage and the x-way shift of this stage. The output of the x-path shifter is the data of the y-path at this level. Similarly, the input of each level of the y-path adder is the y-path data of this level and the output of the y-path shifter at this level. The input of the y-path shifter is the data of the x-path at this level. The θ-path is the encoded angle value. The rotation direction is determined by each bit value. The judgment output is connected to the x-path and y-path adders at this level and the adder of the z-path at the next level to determine whether to perform addition or subtraction operations. The output of each level of the x-path adder is connected to the x-path adder and the y-path shifter at the next level.

[0064] Example

[0065] FFT points: N=1024

[0066] Complex multiplication unit structure: 10-stage pipeline structure

[0067] Rotation angle: β0 = arctan(2 -4 )=0.061009216465617

[0068] ROM table: store β0 through 2 -2 ,2 -3 ,…,2 -5 Iterative results after various possible rotation combinations of equal high-order bit values.

[0069] Operation process:

[0070] Initialization: Store 1024 points of time domain data into the real part memory and the imaginary part memory respectively.

[0071] First-level operation: The address generation unit generates a control signal, and the radix-quad butterfly unit and the rotation angle generation unit perform the first-level operation.

[0072] Second-level operation: The address generation unit generates a control signal, and the radix-quad butterfly unit and the rotation angle generation unit perform the second-level operation.

[0073] Third-level operation: The address generation unit generates a control signal, and the radix-quad butterfly unit and the rotation angle generation unit perform the third-level operation.

[0074] Fourth-level operation: The address generation unit generates a control signal, and the radix-quad butterfly unit and the rotation angle generation unit perform the fourth-level operation.

[0075] Fifth-level operation: The address generation unit generates a control signal, and the radix-quad butterfly unit and the rotation angle generation unit perform the fifth-level operation.

[0076] Output: The address generation unit generates an output result valid signal, and the reversal unit reverses the data processed by the radix-quad butterfly unit and outputs a 1024-point FFT result.

[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. An FFT hardware acceleration circuit based on a complex multiplication unit of a three-stage CORDIC algorithm, characterized in that: include: The address generating unit is respectively connected with the random storage unit, the rotation angle generating unit, the complex multiplication unit based on the three-stage CORDIC algorithm, the radix-quad butterfly unit, the output processing unit and the reverse order unit, and is used to control the working timing of the overall circuit; A random storage unit, including a real memory and an imaginary memory, having a read and write port, connected to the address generation unit, and used for storing the operation data of the complex multiplication unit based on the three-stage CORDIC algorithm; A rotation angle generating unit, connected to the address generating unit, for generating a rotation angle required for FFT operation; A complex multiplication unit based on a three-stage CORDIC algorithm includes an angle bipolar encoding, a shift-addition unit, a merging and iterating unit, a ROM table, and an angle interval mapping, wherein an input end is connected to a rotation angle generating unit, and an output end is connected to a base-four butterfly unit, for performing complex multiplication operations; A radix-quad butterfly unit, whose input end is connected to a random storage unit and a complex multiplication unit based on a three-stage CORDIC algorithm, and whose output end is connected to a reversal unit, is used to perform an FFT operation; An output processing unit, connected to the radix-quad butterfly unit, for processing the FFT operation result; The reversing unit is connected to the radix-quad butterfly unit and the output processing unit, and is used for reversing the FFT operation result.

2. The FFT hardware acceleration circuit of the complex multiplication unit based on the three-stage CORDIC algorithm according to claim 1, characterized in that: In the complex multiplication unit based on the three-stage CORDIC algorithm, angle polarization coding is used to perform angle polarization re-coding on the input angle, so as to perform folding mapping by utilizing the symmetry of the sine and cosine functions.

3. The FFT hardware acceleration circuit of the complex multiplication unit based on the three-stage CORDIC algorithm according to claim 1, characterized in that: In the complex multiplication unit based on the three-stage CORDIC algorithm, the shift-addition unit is used to perform shift-addition operations to realize complex multiplication operations.

4. The FFT hardware acceleration circuit of the complex multiplication unit based on the three-stage CORDIC algorithm according to claim 1, characterized in that: In the complex multiplication unit based on the three-stage CORDIC algorithm, the merging iteration unit is used to divide the iteration process into three stages to improve the operation efficiency.

5. The FFT hardware acceleration circuit of the complex multiplication unit based on the three-stage CORDIC algorithm according to claim 1, characterized in that: In the complex multiplication unit based on the three-stage CORDIC algorithm, the ROM table is used to store pre-calculated iteration results to speed up the calculation process.

6. The FFT hardware acceleration circuit of the complex multiplication unit based on the three-stage CORDIC algorithm according to claim 1, characterized in that: In the complex multiplication unit based on the three-segment CORDIC algorithm, the angle interval mapping is used to determine the addressing address of the ROM table according to the value of the input angle.

7. The FFT hardware acceleration circuit of the complex multiplication unit based on the three-stage CORDIC algorithm according to claim 1, characterized in that: The complex multiplication unit based on the three-stage CORDIC algorithm adopts a pipeline structure, including three operation channels of x, y and θ, each channel includes multiple operation stages, and each operation stage consists of two adders, two shifters and a decision device.

8. The FFT hardware acceleration circuit of the complex multiplication unit based on the three-stage CORDIC algorithm according to claim 1, characterized in that: The working process of the FFT hardware acceleration circuit is as follows: The address generation unit generates an initialization signal and inputs the time domain data into the random storage unit for initialization; The address generating unit generates a first-level operation indication signal to control the base quad-butterfly unit and the rotation angle generating unit to perform the first-level operation; Perform the second level, third level, and so on until the log4N level of operations in sequence; The address generating unit generates an output result valid signal, and controls the reverse order unit to perform reverse order processing on the data processed by the radix-quad butterfly unit and output the data.

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