Packaging process resistant to high electric field breakdown
Through inverted packaging process and bonding technology, the problem of easy breakdown at high voltages of traditional positive packaging power devices is solved, and higher breakdown resistance and reliability are achieved. By setting periodic electrode patterns on wafers and substrates, it is possible to achieve periodic electrode patterns. and channels, etching and grinding of metal layers using sacrificial and functional materials, forming thickened electrode patterns, and electrical connections are achieved by welding or bonding, filling the package insulation layer to increase electrode spacing.
Patent Information
- Application Number
- CN202310791649.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-30
- Publication Date
- 2024-12-31
AI Technical Summary
Traditional positive-packaged power devices are prone to breakdown at high voltages, and the welding process causes device contamination, affecting reliability.
Using inverted packaging technology and bonding technology, the thickened electrode pattern is formed by setting periodic metal electrode patterns and channels on wafers and substrates, and the etching and grinding of metal layers is employed using sacrificial materials and functional materials, forming thickened electrode patterns and through welding or Bonding enables electrical connections, and finally fills the package insulation layer to increase the electrode spacing.
It effectively reduces device pollution, improves breakdown resistance, enhances electrical and thermal performance, and improves device reliability.
Smart Images
Figure CN119230424A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a chip packaging technology, in particular to a packaging process resistant to high electric field breakdown. Background Art
[0002] As a third-generation semiconductor material, gallium nitride (GaN) material has the advantages of wide bandgap, high breakdown electric field, and high output power. In addition, GaN material has low on-resistance when working under high voltage, which makes GaN-based power devices also show higher gain. At the same time, GaN-based power devices have high electron mobility and electron saturation rate, which ensures the high gain of the device in Ka, Q and even W bands. Therefore, GaN-based power device preparation technology has become a hot spot in the current power device field.
[0003] Traditional silicon-based power semiconductor devices and their materials can no longer meet the current industry's development needs for high-frequency, high-temperature, high-power, high-efficiency, harsh environment-resistant and miniaturized power semiconductor devices, and every breakthrough comes at a high price. At present, people have turned their attention to the third-generation semiconductor materials represented by silicon carbide (SiC) and gallium nitride (GaN). They have the advantages of wide bandgap, high breakdown electric field strength, high saturated electron mobility, large thermal conductivity, small dielectric constant, and strong radiation resistance. Combined with excellent switching performance, temperature stability and low electromagnetic interference (EMI), they are more suitable for next-generation power conversion such as solar inverters, power supplies, electric vehicles and industrial power. The use of sapphire substrates with smaller lattice mismatch to grow nitride power devices can obtain excellent epitaxial quality and mature technology. Whether the existing power devices are vertically conductive or horizontally conductive, most of them are based on positive packaging to achieve work, that is, they are all on a fixed frame, through the main processes such as solid crystal, wire bonding, plastic sealing, electroplating, and molding, The power chip is encapsulated in a specific patch packaging form.
[0004] The main problem with this type of positive packaged power device is that the device package needs to be bonded to a heat sink for heat dissipation, the overall volume is large, and the electrodes of the power device need to be electrically connected to the base through wire bonding, so the long-term reliability of the device is problematic. The flip-package technology combined with the bonding technology can achieve wire-free packaging, greatly reducing the package volume, achieving superior electrical and thermal performance, and greatly improving the reliability of the device.
[0005] In conventional bonding or welding processes, the solder will volatilize in the subsequent processing, and then adhere to and contaminate the device interface, which will cause the device to break down under high voltage, affecting the reliability of the device. For example, between the high-voltage device high-voltage and low-voltage electrode pads, or high-density such as large-capacity memory, although the voltage difference is not large, the distance is very close. Summary of the invention
[0006] The technical problem to be solved by the present invention is to provide a packaging form which can reduce device pollution and withstand high electric field breakdown.
[0007] In order to solve the above technical problems, the technical solution of the present invention is: a packaging process resistant to high electric field breakdown, the innovation of which is that it includes three parts: chip production, substrate processing and bonding process. Chip production: S11: a periodic metal electrode pattern is disposed on a first surface of the wafer, and a layer of sacrificial material covering the first surface and the periodic electrode pattern is disposed on the wafer; S12: etching, etching a first channel corresponding to the periodic metal electrode pattern on the surface of the sacrificial material, and the bottom of the first channel extends downward to the surface of the periodic metal electrode pattern, and cleaning is performed after etching; S13: a metal layer is provided on the surface of the sacrificial material by sputtering, evaporation or electroplating, and the metal layer is simultaneously filled into the first channel to contact the periodic metal electrode pattern; S14: polishing, polishing the metal layer to remove the metal layer on the surface of the sacrificial material, leaving the metal layer in the first channel, the metal layer in the first channel and the periodic metal electrode pattern forming an overall thickened metal electrode pattern; S15: cutting, cutting the wafer and the sacrificial material and thickened metal electrode pattern thereon to obtain a discrete device semi-finished product, wherein the discrete device semi-finished product includes, from bottom to top, a chip, a chip-level sacrificial layer, and a chip-level electrode extending upward from the chip-level substrate to the upper surface of the sacrificial layer; Substrate processing: S21: a substrate electrode is printed on the upper surface of the substrate, and a layer of functional material covering the surface of the substrate and the substrate electrode is also provided on the substrate; S22: etching a second channel on the functional material facing the substrate electrode, and cleaning to remove impurities generated by etching; S23: making a connecting electrode, making a connecting electrode in contact with the substrate electrode in the second channel, and the upper surface of the connecting electrode is not lower than the upper surface of the functional material; Lamination process: S31: flipping the discrete device semi-finished product onto the upper surface of the substrate, separating the functional material of the sacrificial layer of the discrete device semi-finished product facing the substrate, and controlling the chip-level electrode of the discrete device semi-finished product to align with the connecting electrode of the second channel, and electrically connecting the chip-level electrode with the substrate electrode by welding or bonding; S32: removing sacrificial materials between the chip and the substrate; S33: Filling a packaging insulation layer between the chip and the substrate.
[0008] Specifically, the substrate is an aluminum oxide, aluminum nitride or ceramic substrate.
[0009] Preferably, in step S32, a wet etching process is used to remove the sacrificial material.
[0010] Specifically, the sacrificial material of the wafer is PI material or low-quality silicon dioxide material. During the manufacturing process of the chip, an etching protection layer is provided between the wafer and the sacrificial material. The etching protection layer is first covered on the first surface of the wafer and the periodic electrode pattern, and then the sacrificial material is covered on the etching protection layer.
[0011] Specifically, the functional material layer is a sacrificial material that can be removed by etching or a thermally conductive insulating material that cannot be removed by etching.
[0012] Preferably, when the functional material is a sacrificial material that can be etched and removed, in S32, the sacrificial material between the chip and the substrate is removed, including the chip-level sacrificial layer on the chip surface and the sacrificial material on the substrate surface.
[0013] Preferably, in step S23, the connecting electrode is a solder ball, and the solder ball protrudes out of the second channel to be higher than the functional material on the surface.
[0014] Preferably, during the soldering process of step S31, the pressure of the discrete device semi-finished product on the surface of the substrate is controlled so that the solder ball expands in the width direction to 105-130% of the diameter of the second channel.
[0015] More specifically, in step S23, a metal connection layer is first formed on the surface of the functional material by sputtering, evaporation or electroplating, and the metal connection layer is simultaneously filled into the second channel; then the metal connection layer on the surface of the functional material layer is removed by grinding to obtain a connecting electrode.
[0016] The advantages of the present invention are: Through the process of the present invention, the cleanliness between the substrate and the chip is greatly guaranteed, and contamination and residue are avoided, which can effectively reduce the contamination of the bonding interface and solve the breakdown problem when the device is working, thereby improving the device's anti-breakdown capability; at the same time, by utilizing the setting of the sacrificial material in the process, as well as the setting of the first and second channels on the substrate and the chip, the electrical connection distance between the electrodes is increased, thereby solving the problem of easy breakdown and heat dissipation caused by the chip and the substrate electrodes being too close after bonding, thereby improving the device's working reliability. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 Schematic diagram of the chip manufacturing process flow of the first embodiment of the present invention.
[0018] Figure 2 Schematic diagram of the substrate processing process flow of the first embodiment of the present invention.
[0019] Figure 3 Schematic diagram of the bonding process flow of the first embodiment of the present invention.
[0020] Figure 4 Schematic diagram of the chip manufacturing process flow of the second embodiment of the present invention.
[0021] Figure 5 Schematic diagram of the substrate processing process flow of the second embodiment of the present invention.
[0022] Figure 6 It is a schematic diagram of the bonding process flow of the second embodiment of the present invention. Implementation Example
[0023] The packaging process of this embodiment includes three parts: chip manufacturing, substrate processing and bonding process. Chip production: Figure 1 As shown, S11: A periodic metal electrode pattern 12 is provided on the first surface of the wafer 11, and a layer of sacrificial material 13 covering the first surface and the periodic electrode pattern 12 is provided on the wafer 11; the sacrificial material 13 is a PI material or a low-quality silicon dioxide material; the periodic metal electrode pattern 12 corresponds to the substrate electrode 22 on the substrate 21 to be mounted later. In this embodiment, the wafer material is gallium nitride as the substrate, and an epitaxial layer of aluminum gallium nitride or other materials is epitaxially grown on the substrate to finally form a wafer with a full-structure epitaxial layer structure; the thickness of the sacrificial material 13 is 500-900 microns; S12: etching, etching a first channel 14 corresponding to the periodic metal electrode pattern 12 on the surface of the sacrificial material 13, and the bottom of the first channel 14 extends downward to the surface of the periodic metal electrode pattern 12, and cleaning is performed after etching; Cleaning after metal etching is mainly to ensure the cleanliness between the electrode and the chip PAD, specifically: EKC cleaning: cleaning after metal corrosion and through-hole corrosion dry stripping, removing the polymer remaining on the edge of the pattern due to dry etching; cleaning parameters are: ratio: EKC265 / IPA; temperature: EKC265@65℃ & IPA room temperature; the process is: EKC tank 30min, IPAⅠ tank 2min, IPAⅡ tank 2min, flush 10 times and spin dry.
[0024] S13: A metal layer 15 is disposed on the surface of the sacrificial material 13 by sputtering, evaporation or electroplating, and the metal layer 15 is simultaneously filled into the first channel 14 and contacts the periodic metal electrode pattern 12; the metal layer 15 is composed of four layers of aluminum, nickel, copper and gold in the first channel 14 from bottom to top, so as to form good adhesion and good electrical interconnection.
[0025] S14: polishing, polishing the metal layer 15 to remove the metal layer on the surface of the sacrificial material 13, leaving the metal layer in the first channel 14, the metal layer in the first channel 14 and the periodic metal electrode pattern forming an overall thickened metal electrode pattern; S15: Cutting, cutting the wafer 11 and the sacrificial material 13 and thickened metal electrode pattern thereon to obtain a discrete device semi-finished product 1, which includes, from bottom to top, a chip 1a, a chip-level sacrificial layer 1b, and a chip-level electrode 1c extending upward from the chip-level substrate to the upper surface of the sacrificial layer.
[0026] Substrate treatment: Figure 2 As shown, S21: The upper surface of the substrate 21 is printed with a substrate electrode 22, and a layer of functional material 23 covering the surface of the substrate 21 and the substrate electrode 22 is also provided on the substrate 21; in this embodiment, the substrate 21 is an aluminum oxide, aluminum nitride or ceramic substrate, and the functional material 23 on the substrate 21 is a sacrificial material that can be etched and removed, such as a PI material or a low-quality silicon dioxide material. Of course, the position of the substrate electrode 22 can correspond to the chip-level electrode 1c of the discrete device semi-finished product 1 to be mounted later. The thickness of the functional material 23 is 500~900 microns; S22: etching a second channel 24 on the functional material 23 facing the substrate electrode 22, and cleaning to remove impurities generated by etching; S23: making a connection electrode 25, making a connection electrode 25 in contact with the substrate electrode in the second channel, and the upper surface of the connection electrode is not lower than the upper surface of the functional material; in this embodiment, the connection electrode 25 is a solder ball, and the solder ball is made in the second channel 24, and the solder ball is controlled to protrude from the second channel 24 to be higher than the functional material 23 on the surface; Lamination process: Figure 3 As shown, S31: Flip the discrete device semi-finished product 1 on the upper surface of the substrate 21, with the chip-level sacrificial layer 1b of the discrete device semi-finished product 1 facing the functional material 23 of the substrate 21, and control the chip-level electrode 1c of the discrete device semi-finished product 1 to align with the connection electrode 25 of the second channel, that is, align with the solder ball, and electrically connect the chip-level electrode 1c with the substrate electrode 22 by welding; control the pressure of the discrete device semi-finished product 1 on the surface of the substrate 21 so that the solder ball expands to 105~130% of the diameter of the second channel in the width direction, and is controlled to be 105~110% in this embodiment. The welding method is selected according to the actual situation, such as reflow soldering, eutectic soldering, and metal direct bonding.
[0027] S32: removing the sacrificial material between the chip 1a and the substrate 21. In this embodiment, the functional material 23 and the chip-level sacrificial layer 1b are also sacrificial materials. Therefore, a wet etching process is used in this step to simultaneously remove the chip-level sacrificial layer 1b and the functional material 23. In this embodiment, the corrosive solvent used in the wet etching process is ethanolamine, and the temperature is 150°C.
[0028] S33: Fill the packaging insulation layer 3 between the chip 1a and the substrate 21. In this embodiment, white glue is used as the packaging insulation layer 3. Before filling the packaging insulation layer 3, the peripheral area of the solder ball of the expanded part can be removed by micro-etching. Example
[0029] The packaging process of this embodiment includes three parts: chip manufacturing, substrate processing and bonding process. Chip production: Figure 4 As shown, S11: A periodic metal electrode pattern 12 is provided on the first surface of the wafer 11, and then an etching protection layer 16 covering the first surface and the periodic electrode pattern 12 is provided on the wafer 11, and then a sacrificial material 13 is covered on the etching protection layer 16. The periodic metal electrode pattern 12 corresponds to the substrate electrode 22 on the substrate 21 to be mounted later. In this embodiment, the sacrificial material 13 is a PI material or a low-quality silicon dioxide material. The material of the etching protection layer 16 is silicon dioxide. It should be noted that the periodic metal electrode pattern 12 can be flush with the first surface of the wafer 11, or slightly higher than the first surface of the wafer 11, but needs to be lower than the upper surface of the etching protection layer 16.
[0030] S12: etching, etching a first channel 14 corresponding to the periodic metal electrode pattern 12 on the surface of the sacrificial material 13, and the bottom of the first channel 14 extends downward to the surface of the periodic metal electrode pattern 12 in or below the etching protection layer 16, and cleaning is performed after etching; S13: a metal layer 15 is formed on the surface of the sacrificial material 13 by sputtering, evaporation or electroplating, and the metal layer 15 is simultaneously filled into the first channel 14 and contacts the periodic metal electrode pattern 12; S14: polishing, polishing the metal layer to remove the metal layer on the surface of the sacrificial material 13, leaving the metal layer 15 in the first channel 14, the metal layer 15 in the first channel 14 and the periodic metal electrode pattern 12 forming an integral thickened metal electrode pattern; S15: cutting, cutting the wafer 11 and the sacrificial material 13 and the thickened metal electrode pattern thereon to obtain a discrete device semi-finished product, wherein the discrete device semi-finished product includes, from bottom to top, a chip 1a, a chip-level etching protection layer 1d, a chip-level sacrificial layer 1b, and a chip-level electrode 1c extending upward from the chip-level substrate to the upper surface of the sacrificial layer; Substrate treatment: Figure 5 As shown, S21: A substrate electrode 22 is printed on the upper surface of the substrate 21, and a layer of functional material 23 covering the surface of the substrate 21 and the substrate electrode 22 is also provided on the substrate 21; in this embodiment, the substrate 21 is aluminum oxide, aluminum nitride or a ceramic substrate, and the functional material 23 on the substrate 21 is the same as in Example 1, and is also a sacrificial material that can be removed by etching, specifically a PI material or a low-quality silicon dioxide material.
[0031] S22: etching a second channel 24 facing the substrate electrode on the functional material 23, and cleaning to remove impurities generated by etching; S23: Make a connecting electrode 25, and make a connecting electrode 25 in contact with the substrate electrode in the second channel. In this embodiment, the connecting electrode 25 is a solder ball, and the solder ball 25 is made in the second channel 24, and the solder ball 25 is controlled to protrude from the second channel 24 to be higher than the functional material 23 on the surface.
[0032] Lamination process: Figure 6 As shown, S31: Flip the discrete device semi-finished product 1 on the upper surface of the substrate 21, separate the chip-level sacrificial layer 1b of the discrete device semi-finished product 1 facing the functional material 23 of the substrate 21, and control the chip-level electrode of the discrete device semi-finished product 1 to align with the solder ball of the second channel 24, and electrically connect the chip-level electrode 1c to the substrate electrode 22 by welding; control the pressure of the discrete device semi-finished product 1 on the surface of the substrate 21 so that the solder ball expands in the width direction to 125~130% of the diameter of the second channel.
[0033] S32: removing the chip-level sacrificial layer 1b and the functional material 23 between the chip 1a and the substrate 21. In this embodiment, the chip-level sacrificial layer 1b and the functional material 23 are removed by a wet etching process; S33: filling a packaging insulation layer 3 between the chip and the substrate. In this embodiment, white glue is used as the packaging insulation layer 3. Example
[0034] The process of this embodiment includes three parts: chip manufacturing, substrate processing and bonding process. The chip manufacturing is the same as that of Embodiment 1 or 2, except that: Substrate processing: S21: The substrate electrode 22 is printed on the upper surface of the substrate 21, and a layer of functional material 23 covering the surface of the substrate 21 and the substrate electrode 22 is provided on the surface of the substrate 21; in this embodiment, the substrate 21 is an aluminum oxide, aluminum nitride or ceramic substrate, and the functional material 23 is a thermally conductive insulating material that cannot be etched and removed, such as silicon nitride, aluminum nitride, diamond or black colloid, which has high insulation and thermal conductivity. Of course, the position of the substrate electrode 22 can correspond to the chip-level electrode 1c of the discrete device semi-finished product 1 to be mounted later.
[0035] S22: etching a second channel 24 facing the substrate electrode 22 on the insulating layer material 23, and cleaning to remove impurities generated by etching; S23: Make a connecting electrode 25, and make a connecting electrode 25 in contact with the substrate electrode in the second channel, and the upper surface of the connecting electrode is not lower than the upper surface of the functional material. In this embodiment, first, a metal connecting layer is formed on the surface of the functional material by sputtering, evaporation or electroplating, and the metal connecting layer is filled into the second channel 24 at the same time; then, the metal connecting layer on the surface of the functional material layer is removed by grinding to obtain the connecting electrode 25.
[0036] Fitting treatment: S31: flipping the discrete device semi-finished product onto the upper surface of the substrate, separating the functional material of the sacrificial layer of the discrete device semi-finished product facing the substrate, and controlling the chip-level electrode of the discrete device semi-finished product to align with the connecting electrode of the second channel, and electrically connecting the chip-level electrode with the substrate electrode by bonding; S32: removing the sacrificial material between the chip and the substrate. In this embodiment, the functional material 23 is a thermally conductive insulating material that cannot be removed by etching. Therefore, this step only removes the chip-level sacrificial layer 1b.
[0037] S33: Filling a packaging insulation layer between the chip and the substrate. Example
[0038] The high electric field breakdown resistant packaging process of this embodiment includes not only chip manufacturing, substrate processing and bonding processes, but also the manufacturing of transition isolation devices: During chip manufacturing: a discrete device semi-finished product 1 is obtained, which includes, from bottom to top, a chip 1a, a chip-level sacrificial layer 1b, and a chip-level electrode 1c extending upward from a chip-level substrate to the upper surface of the sacrificial layer.
[0039] During substrate processing, a substrate electrode 22 is printed on the upper surface of the prepared substrate 21, and a functional material 23 covers the surface of the substrate 21 and the substrate electrode 22. A connecting electrode 25 is arranged in the second channel 24, and the bottom end of the connecting electrode 25 is electrically connected to the substrate electrode 22, and the upper end of the connecting electrode 25 is not lower than the upper surface of the functional material.
[0040] The discrete device semi-finished product and substrate structure obtained by chip manufacturing and substrate processing in this embodiment are the same as those in Embodiment 1, 2 or 3, and will not be repeated here.
[0041] Fabrication of a transition isolation device: fabricating an insulating member 31, opening a hole on the insulating member 31 that passes through the upper and lower surfaces of the insulating member, and arranging a transition metal electrode 32 in the hole; Lamination process: The insulating member 31 is disposed between the substrate and the discrete device semi-finished product, and the transition metal electrodes 32 on the upper and lower surfaces of the insulating member are respectively aligned with the connection electrodes 25 on the substrate, and are bonded by eutectic welding.
Claims
1. A packaging process resistant to high electric field breakdown, characterized in that: It includes three parts: chip production, substrate processing and bonding process. Chip production: S11: a periodic metal electrode pattern is disposed on a first surface of the wafer, and a layer of sacrificial material covering the first surface and the periodic electrode pattern is disposed on the wafer; S12： Etching, etching a first channel corresponding to the periodic metal electrode pattern on the surface of the sacrificial material, with the bottom of the first channel extending downward to the surface of the periodic metal electrode pattern, and cleaning after etching; S13: a metal layer is provided on the surface of the sacrificial material by sputtering, evaporation or electroplating, and the metal layer is simultaneously filled into the first channel to contact the periodic metal electrode pattern; S14: polishing, polishing the metal layer to remove the metal layer on the surface of the sacrificial material, leaving the metal layer in the first channel, the metal layer in the first channel and the periodic metal electrode pattern forming an overall thickened metal electrode pattern; S15: cutting, cutting the wafer and the sacrificial material and thickened metal electrode pattern thereon to obtain a discrete device semi-finished product, wherein the discrete device semi-finished product includes, from bottom to top, a chip, a chip-level sacrificial layer, and a chip-level electrode extending upward from the chip-level substrate to the upper surface of the sacrificial layer; Substrate processing: S21: a substrate electrode is printed on the upper surface of the substrate, and a layer of functional material covering the surface of the substrate and the substrate electrode is also provided on the substrate; S22: etching a second channel on the functional material facing the substrate electrode, and cleaning to remove impurities generated by etching; S23: making a connecting electrode, making a connecting electrode in contact with the substrate electrode in the second channel, and the upper surface of the connecting electrode is not lower than the upper surface of the functional material; Lamination process: S31: flipping the discrete device semi-finished product onto the upper surface of the substrate, separating the functional material of the sacrificial layer of the discrete device semi-finished product facing the substrate, and controlling the chip-level electrode of the discrete device semi-finished product to align with the connecting electrode of the second channel, and electrically connecting the chip-level electrode with the substrate electrode by welding or bonding; S32: removing sacrificial materials between the chip and the substrate; S33: Filling a packaging insulation layer between the chip and the substrate.
2. The packaging process for withstanding high electric field breakdown according to claim 1, characterized in that: The substrate is aluminum oxide, aluminum nitride or a ceramic substrate.
3. The packaging process for withstanding high electric field breakdown according to claim 1, characterized in that: In step S32, a wet etching process is used to remove the sacrificial material.
4. The packaging process for withstanding high electric field breakdown according to claim 1, characterized in that: The sacrificial material of the wafer is PI material or low-quality silicon dioxide material.
5. The packaging process for withstanding high electric field breakdown according to claim 1, characterized in that: During the manufacturing process of the chip, an etching protection layer is provided between the wafer and the sacrificial material. The etching protection layer is firstly covered on the first surface of the wafer and the periodic electrode pattern, and then the sacrificial material is covered on the etching protection layer.
6. The packaging process for withstanding high electric field breakdown according to claim 1, characterized in that: The functional material layer is a sacrificial material that can be removed by etching or a thermally conductive insulating material that cannot be removed by etching.
7. The packaging process for withstanding high electric field breakdown according to claim 6, characterized in that: When the functional material is a sacrificial material that can be removed by etching, in S32, the sacrificial material between the chip and the substrate is removed, including the chip-level sacrificial layer on the chip surface and the sacrificial material on the substrate surface.
8. The packaging process for withstanding high electric field breakdown according to claim 1, characterized in that: In the step S23, the connection electrode is a solder ball, and the solder ball protrudes out of the second channel to be higher than the functional material on the surface.
9. The packaging process for withstanding high electric field breakdown according to claim 8, characterized in that: During the soldering process of step S31 , the pressure of the discrete device semi-finished product on the surface of the substrate is controlled so that the solder ball expands in the width direction to 105-130% of the diameter of the second channel.
10. The packaging process for withstanding high electric field breakdown according to claim 1, characterized in that: In the step S23, a metal connection layer is first formed on the surface of the functional material by sputtering, evaporation or electroplating, and the metal connection layer is simultaneously filled into the second channel; then the metal connection layer on the surface of the functional material layer is removed by grinding to obtain a connecting electrode.